decoder.isa revision 2100
111923Sandreas.sandberg@arm.com// -*- mode:c++ -*- 211923Sandreas.sandberg@arm.com 311923Sandreas.sandberg@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 411923Sandreas.sandberg@arm.com// All rights reserved. 511923Sandreas.sandberg@arm.com// 611923Sandreas.sandberg@arm.com// Redistribution and use in source and binary forms, with or without 711923Sandreas.sandberg@arm.com// modification, are permitted provided that the following conditions are 811923Sandreas.sandberg@arm.com// met: redistributions of source code must retain the above copyright 911923Sandreas.sandberg@arm.com// notice, this list of conditions and the following disclaimer; 1011923Sandreas.sandberg@arm.com// redistributions in binary form must reproduce the above copyright 1111923Sandreas.sandberg@arm.com// notice, this list of conditions and the following disclaimer in the 1211923Sandreas.sandberg@arm.com// documentation and/or other materials provided with the distribution; 132889Sbinkertn@umich.edu// neither the name of the copyright holders nor the names of its 142889Sbinkertn@umich.edu// contributors may be used to endorse or promote products derived from 152889Sbinkertn@umich.edu// this software without specific prior written permission. 162889Sbinkertn@umich.edu// 172889Sbinkertn@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182889Sbinkertn@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192889Sbinkertn@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202889Sbinkertn@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212889Sbinkertn@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222889Sbinkertn@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232889Sbinkertn@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242889Sbinkertn@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252889Sbinkertn@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262889Sbinkertn@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272889Sbinkertn@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282889Sbinkertn@umich.edu 292889Sbinkertn@umich.edudecode OPCODE default Unknown::unknown() { 302889Sbinkertn@umich.edu 312889Sbinkertn@umich.edu format LoadAddress { 322889Sbinkertn@umich.edu 0x08: lda({{ Ra = Rb + disp; }}); 332889Sbinkertn@umich.edu 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 342889Sbinkertn@umich.edu } 352889Sbinkertn@umich.edu 362889Sbinkertn@umich.edu format LoadOrNop { 372889Sbinkertn@umich.edu 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 382889Sbinkertn@umich.edu 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 392889Sbinkertn@umich.edu 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 402889Sbinkertn@umich.edu 0x23: ldt({{ Fa = Mem.df; }}); 4112563Sgabeblack@google.com 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 4212563Sgabeblack@google.com 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 434850Snate@binkert.org 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 444850Snate@binkert.org {{ fault = xc->copySrcTranslate(EA); }}, 454850Snate@binkert.org inst_flags = [IsMemRef, IsLoad, IsCopy]); 464850Snate@binkert.org } 474850Snate@binkert.org 484850Snate@binkert.org format LoadOrPrefetch { 492889Sbinkertn@umich.edu 0x28: ldl({{ Ra.sl = Mem.sl; }}); 502889Sbinkertn@umich.edu 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 518327Sgblack@eecs.umich.edu // IsFloating flag on lds gets the prefetch to disassemble 525470Snate@binkert.org // using f31 instead of r31... funcitonally it's unnecessary 538333Snate@binkert.org 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 548333Snate@binkert.org pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 552889Sbinkertn@umich.edu } 568234Snate@binkert.org 578234Snate@binkert.org format Store { 588234Snate@binkert.org 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 592889Sbinkertn@umich.edu 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 608234Snate@binkert.org 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 618234Snate@binkert.org 0x2d: stq({{ Mem.uq = Ra.uq; }}); 628234Snate@binkert.org 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 638234Snate@binkert.org 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 642889Sbinkertn@umich.edu 0x27: stt({{ Mem.df = Fa; }}); 6511923Sandreas.sandberg@arm.com 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 6611923Sandreas.sandberg@arm.com {{ fault = xc->copy(EA); }}, 678234Snate@binkert.org inst_flags = [IsMemRef, IsStore, IsCopy]); 688234Snate@binkert.org } 698234Snate@binkert.org 708234Snate@binkert.org format StoreCond { 718234Snate@binkert.org 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 728234Snate@binkert.org {{ 738234Snate@binkert.org uint64_t tmp = write_result; 742889Sbinkertn@umich.edu // see stq_c 758234Snate@binkert.org Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 768234Snate@binkert.org }}, mem_flags = LOCKED); 778234Snate@binkert.org 0x2f: stq_c({{ Mem.uq = Ra; }}, 788234Snate@binkert.org {{ 798234Snate@binkert.org uint64_t tmp = write_result; 808234Snate@binkert.org // If the write operation returns 0 or 1, then 818234Snate@binkert.org // this was a conventional store conditional, 828234Snate@binkert.org // and the value indicates the success/failure 838234Snate@binkert.org // of the operation. If another value is 848234Snate@binkert.org // returned, then this was a Turbolaser 858234Snate@binkert.org // mailbox access, and we don't update the 8611923Sandreas.sandberg@arm.com // result register at all. 8711923Sandreas.sandberg@arm.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 8811923Sandreas.sandberg@arm.com }}, mem_flags = LOCKED); 8911923Sandreas.sandberg@arm.com } 9012012Sgabeblack@google.com 9112012Sgabeblack@google.com format IntegerOperate { 9212012Sgabeblack@google.com 938234Snate@binkert.org 0x10: decode INTFUNC { // integer arithmetic operations 948234Snate@binkert.org 958234Snate@binkert.org 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 968234Snate@binkert.org 0x40: addlv({{ 978234Snate@binkert.org uint32_t tmp = Ra.sl + Rb_or_imm.sl; 988234Snate@binkert.org // signed overflow occurs when operands have same sign 998234Snate@binkert.org // and sign of result does not match. 1008234Snate@binkert.org if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1018234Snate@binkert.org fault = IntegerOverflowFault; 1028234Snate@binkert.org Rc.sl = tmp; 1032889Sbinkertn@umich.edu }}); 1048234Snate@binkert.org 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1058234Snate@binkert.org 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1068234Snate@binkert.org 1078234Snate@binkert.org 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1085773Snate@binkert.org 0x60: addqv({{ 1098234Snate@binkert.org uint64_t tmp = Ra + Rb_or_imm; 1108234Snate@binkert.org // signed overflow occurs when operands have same sign 1118234Snate@binkert.org // and sign of result does not match. 1128234Snate@binkert.org if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1138664SAli.Saidi@ARM.com fault = IntegerOverflowFault; 1148664SAli.Saidi@ARM.com Rc = tmp; 1158998Suri.wiener@arm.com }}); 1168998Suri.wiener@arm.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 11711431Ssascha.bischoff@arm.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 11811418Ssascha.bischoff@arm.com 11911418Ssascha.bischoff@arm.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1202889Sbinkertn@umich.edu 0x49: sublv({{ 1218234Snate@binkert.org uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1228234Snate@binkert.org // signed overflow detection is same as for add, 12311299Ssteve.reinhardt@amd.com // except we need to look at the *complemented* 12411299Ssteve.reinhardt@amd.com // sign bit of the subtrahend (Rb), i.e., if the initial 12511299Ssteve.reinhardt@amd.com // signs are the *same* then no overflow can occur 1268234Snate@binkert.org if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1279960Sandreas.hansson@arm.com fault = IntegerOverflowFault; 1288234Snate@binkert.org Rc.sl = tmp; 1299960Sandreas.hansson@arm.com }}); 13011299Ssteve.reinhardt@amd.com 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 13111304Ssteve.reinhardt@amd.com 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 13211338SMichael.Lebeane@amd.com 13311338SMichael.Lebeane@amd.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1349960Sandreas.hansson@arm.com 0x69: subqv({{ 1359960Sandreas.hansson@arm.com uint64_t tmp = Ra - Rb_or_imm; 1369960Sandreas.hansson@arm.com // signed overflow detection is same as for add, 1379960Sandreas.hansson@arm.com // except we need to look at the *complemented* 1388234Snate@binkert.org // sign bit of the subtrahend (Rb), i.e., if the initial 1398234Snate@binkert.org // signs are the *same* then no overflow can occur 1402889Sbinkertn@umich.edu if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1418234Snate@binkert.org fault = IntegerOverflowFault; 1428234Snate@binkert.org Rc = tmp; 1438234Snate@binkert.org }}); 1448234Snate@binkert.org 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1456171Snate@binkert.org 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1468234Snate@binkert.org 1478234Snate@binkert.org 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1488234Snate@binkert.org 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1498234Snate@binkert.org 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1508234Snate@binkert.org 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 15113671Sandreas.sandberg@arm.com 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1528234Snate@binkert.org 1538234Snate@binkert.org 0x0f: cmpbge({{ 1548234Snate@binkert.org int hi = 7; 1556171Snate@binkert.org int lo = 0; 1568219Snate@binkert.org uint64_t tmp = 0; 1578327Sgblack@eecs.umich.edu for (int i = 0; i < 8; ++i) { 1589512Sandreas@sandberg.pp.se tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1599512Sandreas@sandberg.pp.se hi += 8; 1609512Sandreas@sandberg.pp.se lo += 8; 1619512Sandreas@sandberg.pp.se } 1629512Sandreas@sandberg.pp.se Rc = tmp; 1639512Sandreas@sandberg.pp.se }}); 1648219Snate@binkert.org } 1658219Snate@binkert.org 1669512Sandreas@sandberg.pp.se 0x11: decode INTFUNC { // integer logical operations 1679512Sandreas@sandberg.pp.se 1689512Sandreas@sandberg.pp.se 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1699512Sandreas@sandberg.pp.se 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1709512Sandreas@sandberg.pp.se 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1719512Sandreas@sandberg.pp.se 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1729512Sandreas@sandberg.pp.se 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1739512Sandreas@sandberg.pp.se 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1749512Sandreas@sandberg.pp.se 1759512Sandreas@sandberg.pp.se // conditional moves 1769512Sandreas@sandberg.pp.se 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 17711635SCurtis.Dunham@arm.com 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1789512Sandreas@sandberg.pp.se 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1799512Sandreas@sandberg.pp.se 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1809512Sandreas@sandberg.pp.se 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1819512Sandreas@sandberg.pp.se 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1829512Sandreas@sandberg.pp.se 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1839512Sandreas@sandberg.pp.se 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 1849512Sandreas@sandberg.pp.se 1859512Sandreas@sandberg.pp.se // For AMASK, RA must be R31. 1869512Sandreas@sandberg.pp.se 0x61: decode RA { 1879512Sandreas@sandberg.pp.se 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1888219Snate@binkert.org } 1899512Sandreas@sandberg.pp.se 1909512Sandreas@sandberg.pp.se // For IMPLVER, RA must be R31 and the B operand 1919512Sandreas@sandberg.pp.se // must be the immediate value 1. 1928219Snate@binkert.org 0x6c: decode RA { 1938219Snate@binkert.org 31: decode IMM { 19413671Sandreas.sandberg@arm.com 1: decode INTIMM { 19513671Sandreas.sandberg@arm.com // return EV5 for FULL_SYSTEM and EV6 otherwise 19613674Sandreas.sandberg@arm.com 1: implver({{ 19713674Sandreas.sandberg@arm.com#if FULL_SYSTEM 19813671Sandreas.sandberg@arm.com Rc = 1; 19913671Sandreas.sandberg@arm.com#else 20013671Sandreas.sandberg@arm.com Rc = 2; 20113671Sandreas.sandberg@arm.com#endif 20213671Sandreas.sandberg@arm.com }}); 2038234Snate@binkert.org } 2048245Snate@binkert.org } 2058245Snate@binkert.org } 2065801Snate@binkert.org 2075801Snate@binkert.org#if FULL_SYSTEM 2085801Snate@binkert.org // The mysterious 11.25... 2094167Sbinkertn@umich.edu 0x25: WarnUnimpl::eleven25(); 2104042Sbinkertn@umich.edu#endif 2115801Snate@binkert.org } 2125799Snate@binkert.org 2135799Snate@binkert.org 0x12: decode INTFUNC { 21411923Sandreas.sandberg@arm.com 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2158234Snate@binkert.org 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2168234Snate@binkert.org 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2178234Snate@binkert.org 2188234Snate@binkert.org 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2198234Snate@binkert.org 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2208234Snate@binkert.org 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 22113663Sandreas.sandberg@arm.com 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2228234Snate@binkert.org 2238245Snate@binkert.org 0x52: mskwh({{ 2248245Snate@binkert.org int bv = Rb_or_imm<2:0>; 2259983Sstever@gmail.com Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2269983Sstever@gmail.com }}); 2279983Sstever@gmail.com 0x62: msklh({{ 2289983Sstever@gmail.com int bv = Rb_or_imm<2:0>; 2295524Sstever@gmail.com Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2305524Sstever@gmail.com }}); 2315524Sstever@gmail.com 0x72: mskqh({{ 2325524Sstever@gmail.com int bv = Rb_or_imm<2:0>; 2335524Sstever@gmail.com Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2345524Sstever@gmail.com }}); 2355524Sstever@gmail.com 2365524Sstever@gmail.com 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2375524Sstever@gmail.com 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 23812563Sgabeblack@google.com 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2395524Sstever@gmail.com 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2405524Sstever@gmail.com 24112563Sgabeblack@google.com 0x5a: extwh({{ 2425524Sstever@gmail.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 24312563Sgabeblack@google.com 0x6a: extlh({{ 2445524Sstever@gmail.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2455524Sstever@gmail.com 0x7a: extqh({{ 2465524Sstever@gmail.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2475524Sstever@gmail.com 2485524Sstever@gmail.com 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2495524Sstever@gmail.com 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2505524Sstever@gmail.com 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2515524Sstever@gmail.com 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2525524Sstever@gmail.com 2535524Sstever@gmail.com 0x57: inswh({{ 2545524Sstever@gmail.com int bv = Rb_or_imm<2:0>; 2555524Sstever@gmail.com Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2562889Sbinkertn@umich.edu }}); 2574850Snate@binkert.org 0x67: inslh({{ 2584850Snate@binkert.org int bv = Rb_or_imm<2:0>; 2594850Snate@binkert.org Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 26012563Sgabeblack@google.com }}); 26112563Sgabeblack@google.com 0x77: insqh({{ 26212563Sgabeblack@google.com int bv = Rb_or_imm<2:0>; 26312563Sgabeblack@google.com Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2645801Snate@binkert.org }}); 2654850Snate@binkert.org 2664850Snate@binkert.org 0x30: zap({{ 2675801Snate@binkert.org uint64_t zapmask = 0; 26812563Sgabeblack@google.com for (int i = 0; i < 8; ++i) { 26912563Sgabeblack@google.com if (Rb_or_imm<i:>) 2704850Snate@binkert.org zapmask |= (mask(8) << (i * 8)); 2712889Sbinkertn@umich.edu } 2722889Sbinkertn@umich.edu Rc = Ra & ~zapmask; 27312563Sgabeblack@google.com }}); 27412563Sgabeblack@google.com 0x31: zapnot({{ 2752889Sbinkertn@umich.edu uint64_t zapmask = 0; 2762889Sbinkertn@umich.edu for (int i = 0; i < 8; ++i) { 2772889Sbinkertn@umich.edu if (!Rb_or_imm<i:>) 27812563Sgabeblack@google.com zapmask |= (mask(8) << (i * 8)); 27912563Sgabeblack@google.com } 28012563Sgabeblack@google.com Rc = Ra & ~zapmask; 28112563Sgabeblack@google.com }}); 2822889Sbinkertn@umich.edu } 2838232Snate@binkert.org 2844053Sbinkertn@umich.edu 0x13: decode INTFUNC { // integer multiplies 28513671Sandreas.sandberg@arm.com 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2868232Snate@binkert.org 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2874053Sbinkertn@umich.edu 0x30: umulh({{ 2885473Snate@binkert.org uint64_t hi, lo; 2895473Snate@binkert.org mul128(Ra, Rb_or_imm, hi, lo); 2905473Snate@binkert.org Rc = hi; 29112563Sgabeblack@google.com }}, IntMultOp); 2925473Snate@binkert.org 0x40: mullv({{ 2935473Snate@binkert.org // 32-bit multiply with trap on overflow 2945473Snate@binkert.org int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2955473Snate@binkert.org int64_t Rbx = Rb_or_imm.sl; 29612563Sgabeblack@google.com int64_t tmp = Rax * Rbx; 2975473Snate@binkert.org // To avoid overflow, all the upper 32 bits must match 2985473Snate@binkert.org // the sign bit of the lower 32. We code this as 2995473Snate@binkert.org // checking the upper 33 bits for all 0s or all 1s. 3005473Snate@binkert.org uint64_t sign_bits = tmp<63:31>; 3015473Snate@binkert.org if (sign_bits != 0 && sign_bits != mask(33)) 30212563Sgabeblack@google.com fault = IntegerOverflowFault; 3035473Snate@binkert.org Rc.sl = tmp<31:0>; 30412563Sgabeblack@google.com }}, IntMultOp); 30512563Sgabeblack@google.com 0x60: mulqv({{ 30612563Sgabeblack@google.com // 64-bit multiply with trap on overflow 30712563Sgabeblack@google.com uint64_t hi, lo; 3085473Snate@binkert.org mul128(Ra, Rb_or_imm, hi, lo); 3092889Sbinkertn@umich.edu // all the upper 64 bits must match the sign bit of 3102889Sbinkertn@umich.edu // the lower 64 3112889Sbinkertn@umich.edu if (!((hi == 0 && lo<63:> == 0) || 3125470Snate@binkert.org (hi == mask(64) && lo<63:> == 1))) 3135470Snate@binkert.org fault = IntegerOverflowFault; 3145470Snate@binkert.org Rc = lo; 3155470Snate@binkert.org }}, IntMultOp); 3165470Snate@binkert.org } 31710134Sstan.czerniawski@arm.com 31812563Sgabeblack@google.com 0x1c: decode INTFUNC { 31912563Sgabeblack@google.com 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 32012563Sgabeblack@google.com 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3215801Snate@binkert.org 0x32: ctlz({{ 32212563Sgabeblack@google.com uint64_t count = 0; 3235456Ssaidi@eecs.umich.edu uint64_t temp = Rb; 32412563Sgabeblack@google.com if (temp<63:32>) temp >>= 32; else count += 32; 32512563Sgabeblack@google.com if (temp<31:16>) temp >>= 16; else count += 16; 32612563Sgabeblack@google.com if (temp<15:8>) temp >>= 8; else count += 8; 32712563Sgabeblack@google.com if (temp<7:4>) temp >>= 4; else count += 4; 3285528Sstever@gmail.com if (temp<3:2>) temp >>= 2; else count += 2; 32910758Ssteve.reinhardt@amd.com if (temp<1:1>) temp >>= 1; else count += 1; 33010758Ssteve.reinhardt@amd.com if ((temp<0:0>) != 0x1) count += 1; 33112563Sgabeblack@google.com Rc = count; 33212563Sgabeblack@google.com }}, IntAluOp); 3332889Sbinkertn@umich.edu 3342889Sbinkertn@umich.edu 0x33: cttz({{ 3352889Sbinkertn@umich.edu uint64_t count = 0; 3362922Sktlim@umich.edu uint64_t temp = Rb; 33712563Sgabeblack@google.com if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3384053Sbinkertn@umich.edu if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3395470Snate@binkert.org if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3402889Sbinkertn@umich.edu if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3412889Sbinkertn@umich.edu if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3425801Snate@binkert.org if (!(temp<0:0> & ULL(0x1))) count += 1; 3432889Sbinkertn@umich.edu Rc = count; 3442889Sbinkertn@umich.edu }}, IntAluOp); 3452889Sbinkertn@umich.edu 3462889Sbinkertn@umich.edu format FailUnimpl { 3472889Sbinkertn@umich.edu 0x30: ctpop(); 34811878Sandreas.sandberg@arm.com 0x31: perr(); 3492889Sbinkertn@umich.edu 0x34: unpkbw(); 35011923Sandreas.sandberg@arm.com 0x35: unpkbl(); 35111923Sandreas.sandberg@arm.com 0x36: pkwb(); 35211923Sandreas.sandberg@arm.com 0x37: pklb(); 35311923Sandreas.sandberg@arm.com 0x38: minsb8(); 35411923Sandreas.sandberg@arm.com 0x39: minsw4(); 35511923Sandreas.sandberg@arm.com 0x3a: minub8(); 35611923Sandreas.sandberg@arm.com 0x3b: minuw4(); 35711923Sandreas.sandberg@arm.com 0x3c: maxub8(); 35811923Sandreas.sandberg@arm.com 0x3d: maxuw4(); 35911923Sandreas.sandberg@arm.com 0x3e: maxsb8(); 36011923Sandreas.sandberg@arm.com 0x3f: maxsw4(); 36111923Sandreas.sandberg@arm.com } 36211923Sandreas.sandberg@arm.com 36312012Sgabeblack@google.com format BasicOperateWithNopCheck { 36412012Sgabeblack@google.com 0x70: decode RB { 36512012Sgabeblack@google.com 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3662889Sbinkertn@umich.edu } 3675801Snate@binkert.org 0x78: decode RB { 3683645Sbinkertn@umich.edu 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3699960Sandreas.hansson@arm.com FloatCvtOp); 3702889Sbinkertn@umich.edu } 3718232Snate@binkert.org } 37213671Sandreas.sandberg@arm.com } 3734053Sbinkertn@umich.edu } 3745586Snate@binkert.org 3755586Snate@binkert.org // Conditional branches. 3768232Snate@binkert.org format CondBranch { 3775586Snate@binkert.org 0x39: beq({{ cond = (Ra == 0); }}); 3785586Snate@binkert.org 0x3d: bne({{ cond = (Ra != 0); }}); 3795586Snate@binkert.org 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 3805586Snate@binkert.org 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3818232Snate@binkert.org 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3828232Snate@binkert.org 0x3a: blt({{ cond = (Ra.sq < 0); }}); 38312563Sgabeblack@google.com 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3845586Snate@binkert.org 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3854053Sbinkertn@umich.edu 3865586Snate@binkert.org 0x31: fbeq({{ cond = (Fa == 0); }}); 3878232Snate@binkert.org 0x35: fbne({{ cond = (Fa != 0); }}); 3885586Snate@binkert.org 0x36: fbge({{ cond = (Fa >= 0); }}); 3898232Snate@binkert.org 0x37: fbgt({{ cond = (Fa > 0); }}); 3904053Sbinkertn@umich.edu 0x33: fble({{ cond = (Fa <= 0); }}); 3919960Sandreas.hansson@arm.com 0x32: fblt({{ cond = (Fa < 0); }}); 39213671Sandreas.sandberg@arm.com } 3939960Sandreas.hansson@arm.com 3949960Sandreas.hansson@arm.com // unconditional branches 3954074Sbinkertn@umich.edu format UncondBranch { 3965799Snate@binkert.org 0x30: br(); 3974042Sbinkertn@umich.edu 0x34: bsr(IsCall); 39811338SMichael.Lebeane@amd.com } 39913671Sandreas.sandberg@arm.com 40011338SMichael.Lebeane@amd.com // indirect branches 40111338SMichael.Lebeane@amd.com 0x1a: decode JMPFUNC { 40211338SMichael.Lebeane@amd.com format Jump { 4039960Sandreas.hansson@arm.com 0: jmp(); 4044042Sbinkertn@umich.edu 1: jsr(IsCall); 4059960Sandreas.hansson@arm.com 2: ret(IsReturn); 40613671Sandreas.sandberg@arm.com 3: jsr_coroutine(IsCall, IsReturn); 4075799Snate@binkert.org } 4082889Sbinkertn@umich.edu } 4092889Sbinkertn@umich.edu 4102889Sbinkertn@umich.edu // Square root and integer-to-FP moves 4112891Sbinkertn@umich.edu 0x14: decode FP_SHORTFUNC { 4125604Snate@binkert.org // Integer to FP register moves must have RB == 31 41313670Sandreas.sandberg@arm.com 0x4: decode RB { 4145604Snate@binkert.org 31: decode FP_FULLFUNC { 4155604Snate@binkert.org format BasicOperateWithNopCheck { 4163887Sbinkertn@umich.edu 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4172899Sbinkertn@umich.edu 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4182899Sbinkertn@umich.edu 0x014: FailUnimpl::itoff(); // VAX-format conversion 4192899Sbinkertn@umich.edu } 4202899Sbinkertn@umich.edu } 4215604Snate@binkert.org } 4225604Snate@binkert.org 4235604Snate@binkert.org // Square root instructions must have FA == 31 4245604Snate@binkert.org 0xb: decode FA { 4255604Snate@binkert.org 31: decode FP_TYPEFUNC { 4265604Snate@binkert.org format FloatingPointOperate { 4275604Snate@binkert.org#if SS_COMPATIBLE_FP 42812563Sgabeblack@google.com 0x0b: sqrts({{ 42912563Sgabeblack@google.com if (Fb < 0.0) 4305604Snate@binkert.org fault = ArithmeticFault; 4315604Snate@binkert.org Fc = sqrt(Fb); 43212563Sgabeblack@google.com }}, FloatSqrtOp); 4335604Snate@binkert.org#else 4345604Snate@binkert.org 0x0b: sqrts({{ 4355604Snate@binkert.org if (Fb.sf < 0.0) 4365604Snate@binkert.org fault = ArithmeticFault; 4372899Sbinkertn@umich.edu Fc.sf = sqrt(Fb.sf); 43813671Sandreas.sandberg@arm.com }}, FloatSqrtOp); 4392889Sbinkertn@umich.edu#endif 4402889Sbinkertn@umich.edu 0x2b: sqrtt({{ 4412889Sbinkertn@umich.edu if (Fb < 0.0) 4428219Snate@binkert.org fault = ArithmeticFault; 4432889Sbinkertn@umich.edu Fc = sqrt(Fb); 4442889Sbinkertn@umich.edu }}, FloatSqrtOp); 4452889Sbinkertn@umich.edu } 4462889Sbinkertn@umich.edu } 4478234Snate@binkert.org } 4488234Snate@binkert.org 44912563Sgabeblack@google.com // VAX-format sqrtf and sqrtg are not implemented 4502889Sbinkertn@umich.edu 0xa: FailUnimpl::sqrtfg(); 45112563Sgabeblack@google.com } 4522889Sbinkertn@umich.edu 45312563Sgabeblack@google.com // IEEE floating point 4542889Sbinkertn@umich.edu 0x16: decode FP_SHORTFUNC_TOP2 { 455 // The top two bits of the short function code break this 456 // space into four groups: binary ops, compares, reserved, and 457 // conversions. See Table 4-12 of AHB. There are different 458 // special cases in these different groups, so we decode on 459 // these top two bits first just to select a decode strategy. 460 // Most of these instructions may have various trapping and 461 // rounding mode flags set; these are decoded in the 462 // FloatingPointDecode template used by the 463 // FloatingPointOperate format. 464 465 // add/sub/mul/div: just decode on the short function code 466 // and source type. All valid trapping and rounding modes apply. 467 0: decode FP_TRAPMODE { 468 // check for valid trapping modes here 469 0,1,5,7: decode FP_TYPEFUNC { 470 format FloatingPointOperate { 471#if SS_COMPATIBLE_FP 472 0x00: adds({{ Fc = Fa + Fb; }}); 473 0x01: subs({{ Fc = Fa - Fb; }}); 474 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 475 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 476#else 477 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 478 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 479 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 480 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 481#endif 482 483 0x20: addt({{ Fc = Fa + Fb; }}); 484 0x21: subt({{ Fc = Fa - Fb; }}); 485 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 486 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 487 } 488 } 489 } 490 491 // Floating-point compare instructions must have the default 492 // rounding mode, and may use the default trapping mode or 493 // /SU. Both trapping modes are treated the same by M5; the 494 // only difference on the real hardware (as far a I can tell) 495 // is that without /SU you'd get an imprecise trap if you 496 // tried to compare a NaN with something else (instead of an 497 // "unordered" result). 498 1: decode FP_FULLFUNC { 499 format BasicOperateWithNopCheck { 500 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 501 FloatCmpOp); 502 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 503 FloatCmpOp); 504 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 505 FloatCmpOp); 506 0x0a4, 0x5a4: cmptun({{ // unordered 507 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 508 }}, FloatCmpOp); 509 } 510 } 511 512 // The FP-to-integer and integer-to-FP conversion insts 513 // require that FA be 31. 514 3: decode FA { 515 31: decode FP_TYPEFUNC { 516 format FloatingPointOperate { 517 0x2f: decode FP_ROUNDMODE { 518 format FPFixedRounding { 519 // "chopped" i.e. round toward zero 520 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 521 Chopped); 522 // round to minus infinity 523 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 524 MinusInfinity); 525 } 526 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 527 } 528 529 // The cvtts opcode is overloaded to be cvtst if the trap 530 // mode is 2 or 6 (which are not valid otherwise) 531 0x2c: decode FP_FULLFUNC { 532 format BasicOperateWithNopCheck { 533 // trap on denorm version "cvtst/s" is 534 // simulated same as cvtst 535 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 536 } 537 default: cvtts({{ Fc.sf = Fb; }}); 538 } 539 540 // The trapping mode for integer-to-FP conversions 541 // must be /SUI or nothing; /U and /SU are not 542 // allowed. The full set of rounding modes are 543 // supported though. 544 0x3c: decode FP_TRAPMODE { 545 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 546 } 547 0x3e: decode FP_TRAPMODE { 548 0,7: cvtqt({{ Fc = Fb.sq; }}); 549 } 550 } 551 } 552 } 553 } 554 555 // misc FP operate 556 0x17: decode FP_FULLFUNC { 557 format BasicOperateWithNopCheck { 558 0x010: cvtlq({{ 559 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 560 }}); 561 0x030: cvtql({{ 562 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 563 }}); 564 565 // We treat the precise & imprecise trapping versions of 566 // cvtql identically. 567 0x130, 0x530: cvtqlv({{ 568 // To avoid overflow, all the upper 32 bits must match 569 // the sign bit of the lower 32. We code this as 570 // checking the upper 33 bits for all 0s or all 1s. 571 uint64_t sign_bits = Fb.uq<63:31>; 572 if (sign_bits != 0 && sign_bits != mask(33)) 573 fault = IntegerOverflowFault; 574 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 575 }}); 576 577 0x020: cpys({{ // copy sign 578 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 579 }}); 580 0x021: cpysn({{ // copy sign negated 581 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 582 }}); 583 0x022: cpyse({{ // copy sign and exponent 584 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 585 }}); 586 587 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 588 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 589 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 590 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 591 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 592 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 593 594 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 595 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 596 } 597 } 598 599 // miscellaneous mem-format ops 600 0x18: decode MEMFUNC { 601 format WarnUnimpl { 602 0x8000: fetch(); 603 0xa000: fetch_m(); 604 0xe800: ecb(); 605 } 606 607 format MiscPrefetch { 608 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 609 {{ xc->writeHint(EA, 64, memAccessFlags); }}, 610 mem_flags = NO_FAULT, 611 inst_flags = [IsMemRef, IsDataPrefetch, 612 IsStore, MemWriteOp]); 613 } 614 615 format BasicOperate { 616 0xc000: rpcc({{ 617#if FULL_SYSTEM 618 /* Rb is a fake dependency so here is a fun way to get 619 * the parser to understand that. 620 */ 621 Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0); 622 623#else 624 Ra = curTick; 625#endif 626 }}); 627 628 // All of the barrier instructions below do nothing in 629 // their execute() methods (hence the empty code blocks). 630 // All of their functionality is hard-coded in the 631 // pipeline based on the flags IsSerializing, 632 // IsMemBarrier, and IsWriteBarrier. In the current 633 // detailed CPU model, the execute() function only gets 634 // called at fetch, so there's no way to generate pipeline 635 // behavior at any other stage. Once we go to an 636 // exec-in-exec CPU model we should be able to get rid of 637 // these flags and implement this behavior via the 638 // execute() methods. 639 640 // trapb is just a barrier on integer traps, where excb is 641 // a barrier on integer and FP traps. "EXCB is thus a 642 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 643 // them the same though. 644 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 645 0x0400: excb({{ }}, IsSerializing, No_OpClass); 646 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 647 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 648 } 649 650#if FULL_SYSTEM 651 format BasicOperate { 652 0xe000: rc({{ 653 Ra = xc->readIntrFlag(); 654 xc->setIntrFlag(0); 655 }}, IsNonSpeculative); 656 0xf000: rs({{ 657 Ra = xc->readIntrFlag(); 658 xc->setIntrFlag(1); 659 }}, IsNonSpeculative); 660 } 661#else 662 format FailUnimpl { 663 0xe000: rc(); 664 0xf000: rs(); 665 } 666#endif 667 } 668 669#if FULL_SYSTEM 670 0x00: CallPal::call_pal({{ 671 if (!palValid || 672 (palPriv 673 && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 674 // invalid pal function code, or attempt to do privileged 675 // PAL call in non-kernel mode 676 fault = UnimplementedOpcodeFault; 677 } 678 else { 679 // check to see if simulator wants to do something special 680 // on this PAL call (including maybe suppress it) 681 bool dopal = xc->simPalCheck(palFunc); 682 683 if (dopal) { 684 AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); 685 xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); 686 NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 687 } 688 } 689 }}, IsNonSpeculative); 690#else 691 0x00: decode PALFUNC { 692 format EmulatedCallPal { 693 0x00: halt ({{ 694 SimExit(curTick, "halt instruction encountered"); 695 }}, IsNonSpeculative); 696 0x83: callsys({{ 697 xc->syscall(); 698 }}, IsNonSpeculative); 699 // Read uniq reg into ABI return value register (r0) 700 0x9e: rduniq({{ R0 = Runiq; }}); 701 // Write uniq reg with value from ABI arg register (r16) 702 0x9f: wruniq({{ Runiq = R16; }}); 703 } 704 } 705#endif 706 707#if FULL_SYSTEM 708 format HwLoad { 709 0x1b: decode HW_LDST_QUAD { 710 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 711 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 712 } 713 } 714 715 format HwStore { 716 0x1f: decode HW_LDST_COND { 717 0: decode HW_LDST_QUAD { 718 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 719 {{ Mem.ul = Ra<31:0>; }}, L); 720 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 721 {{ Mem.uq = Ra.uq; }}, Q); 722 } 723 724 1: FailUnimpl::hw_st_cond(); 725 } 726 } 727 728 format HwMoveIPR { 729 0x19: hw_mfpr({{ 730 // this instruction is only valid in PAL mode 731 if (!xc->inPalMode()) { 732 fault = UnimplementedOpcodeFault; 733 } 734 else { 735 Ra = xc->readIpr(ipr_index, fault); 736 } 737 }}); 738 0x1d: hw_mtpr({{ 739 // this instruction is only valid in PAL mode 740 if (!xc->inPalMode()) { 741 fault = UnimplementedOpcodeFault; 742 } 743 else { 744 xc->setIpr(ipr_index, Ra); 745 if (traceData) { traceData->setData(Ra); } 746 } 747 }}); 748 } 749 750 format BasicOperate { 751 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing); 752 753 // M5 special opcodes use the reserved 0x01 opcode space 754 0x01: decode M5FUNC { 755 0x00: arm({{ 756 AlphaPseudo::arm(xc->xcBase()); 757 }}, IsNonSpeculative); 758 0x01: quiesce({{ 759 AlphaPseudo::quiesce(xc->xcBase()); 760 }}, IsNonSpeculative); 761 0x10: ivlb({{ 762 AlphaPseudo::ivlb(xc->xcBase()); 763 }}, No_OpClass, IsNonSpeculative); 764 0x11: ivle({{ 765 AlphaPseudo::ivle(xc->xcBase()); 766 }}, No_OpClass, IsNonSpeculative); 767 0x20: m5exit_old({{ 768 AlphaPseudo::m5exit_old(xc->xcBase()); 769 }}, No_OpClass, IsNonSpeculative); 770 0x21: m5exit({{ 771 AlphaPseudo::m5exit(xc->xcBase(), R16); 772 }}, No_OpClass, IsNonSpeculative); 773 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }}); 774 0x40: resetstats({{ 775 AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 776 }}, IsNonSpeculative); 777 0x41: dumpstats({{ 778 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 779 }}, IsNonSpeculative); 780 0x42: dumpresetstats({{ 781 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 782 }}, IsNonSpeculative); 783 0x43: m5checkpoint({{ 784 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 785 }}, IsNonSpeculative); 786 0x50: m5readfile({{ 787 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 788 }}, IsNonSpeculative); 789 0x51: m5break({{ 790 AlphaPseudo::debugbreak(xc->xcBase()); 791 }}, IsNonSpeculative); 792 0x52: m5switchcpu({{ 793 AlphaPseudo::switchcpu(xc->xcBase()); 794 }}, IsNonSpeculative); 795 0x53: m5addsymbol({{ 796 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 797 }}, IsNonSpeculative); 798 799 } 800 } 801#endif 802} 803