decoder.isa revision 10474
12068SN/A// -*- mode:c++ -*- 22068SN/A 39829Sandreas.hansson@arm.com// Copyright (c) 2013 ARM Limited 49829Sandreas.hansson@arm.com// All rights reserved 59829Sandreas.hansson@arm.com// 69829Sandreas.hansson@arm.com// The license below extends only to copyright in the software and shall 79829Sandreas.hansson@arm.com// not be construed as granting a license to any other intellectual 89829Sandreas.hansson@arm.com// property including but not limited to intellectual property relating 99829Sandreas.hansson@arm.com// to a hardware implementation of the functionality of the software 109829Sandreas.hansson@arm.com// licensed hereunder. You may use the software subject to the license 119829Sandreas.hansson@arm.com// terms below provided that you ensure that this notice is replicated 129829Sandreas.hansson@arm.com// unmodified and in its entirety in all distributions of the software, 139829Sandreas.hansson@arm.com// modified or unmodified, in source code or in binary form. 149829Sandreas.hansson@arm.com// 152188SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 162068SN/A// All rights reserved. 172068SN/A// 182068SN/A// Redistribution and use in source and binary forms, with or without 192068SN/A// modification, are permitted provided that the following conditions are 202068SN/A// met: redistributions of source code must retain the above copyright 212068SN/A// notice, this list of conditions and the following disclaimer; 222068SN/A// redistributions in binary form must reproduce the above copyright 232068SN/A// notice, this list of conditions and the following disclaimer in the 242068SN/A// documentation and/or other materials provided with the distribution; 252068SN/A// neither the name of the copyright holders nor the names of its 262068SN/A// contributors may be used to endorse or promote products derived from 272068SN/A// this software without specific prior written permission. 282068SN/A// 292068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu// 412665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 422068SN/A 432649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 442649Ssaidi@eecs.umich.edu// 452649Ssaidi@eecs.umich.edu// The actual decoder specification 462649Ssaidi@eecs.umich.edu// 472649Ssaidi@eecs.umich.edu 482068SN/Adecode OPCODE default Unknown::unknown() { 492068SN/A 502068SN/A format LoadAddress { 512068SN/A 0x08: lda({{ Ra = Rb + disp; }}); 522068SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 532068SN/A } 542068SN/A 552068SN/A format LoadOrNop { 568588Sgblack@eecs.umich.edu 0x0a: ldbu({{ Ra_uq = Mem_ub; }}); 578588Sgblack@eecs.umich.edu 0x0c: ldwu({{ Ra_uq = Mem_uw; }}); 588588Sgblack@eecs.umich.edu 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 598588Sgblack@eecs.umich.edu 0x23: ldt({{ Fa = Mem_df; }}); 608588Sgblack@eecs.umich.edu 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC); 618588Sgblack@eecs.umich.edu 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC); 622068SN/A } 632068SN/A 642068SN/A format LoadOrPrefetch { 658588Sgblack@eecs.umich.edu 0x28: ldl({{ Ra_sl = Mem_sl; }}); 668588Sgblack@eecs.umich.edu 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT); 672068SN/A // IsFloating flag on lds gets the prefetch to disassemble 682068SN/A // using f31 instead of r31... funcitonally it's unnecessary 698588Sgblack@eecs.umich.edu 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }}, 702075SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 712068SN/A } 722068SN/A 732068SN/A format Store { 748588Sgblack@eecs.umich.edu 0x0e: stb({{ Mem_ub = Ra<7:0>; }}); 758588Sgblack@eecs.umich.edu 0x0d: stw({{ Mem_uw = Ra<15:0>; }}); 768588Sgblack@eecs.umich.edu 0x2c: stl({{ Mem_ul = Ra<31:0>; }}); 778588Sgblack@eecs.umich.edu 0x2d: stq({{ Mem_uq = Ra_uq; }}); 788588Sgblack@eecs.umich.edu 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }}); 798588Sgblack@eecs.umich.edu 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }}); 808588Sgblack@eecs.umich.edu 0x27: stt({{ Mem_df = Fa; }}); 812068SN/A } 822068SN/A 832068SN/A format StoreCond { 848588Sgblack@eecs.umich.edu 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }}, 852068SN/A {{ 862069SN/A uint64_t tmp = write_result; 872068SN/A // see stq_c 882068SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 894027Sstever@eecs.umich.edu if (tmp == 1) { 904027Sstever@eecs.umich.edu xc->setStCondFailures(0); 914027Sstever@eecs.umich.edu } 926076Sgblack@eecs.umich.edu }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 938588Sgblack@eecs.umich.edu 0x2f: stq_c({{ Mem_uq = Ra; }}, 942068SN/A {{ 952069SN/A uint64_t tmp = write_result; 962068SN/A // If the write operation returns 0 or 1, then 972068SN/A // this was a conventional store conditional, 982068SN/A // and the value indicates the success/failure 992068SN/A // of the operation. If another value is 1002068SN/A // returned, then this was a Turbolaser 1012068SN/A // mailbox access, and we don't update the 1022068SN/A // result register at all. 1032068SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 1044027Sstever@eecs.umich.edu if (tmp == 1) { 1054027Sstever@eecs.umich.edu // clear failure counter... this is 1064027Sstever@eecs.umich.edu // non-architectural and for debugging 1074027Sstever@eecs.umich.edu // only. 1084027Sstever@eecs.umich.edu xc->setStCondFailures(0); 1094027Sstever@eecs.umich.edu } 1106076Sgblack@eecs.umich.edu }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 1112068SN/A } 1122068SN/A 1132068SN/A format IntegerOperate { 1142068SN/A 1157799Sgblack@eecs.umich.edu 0x10: decode INTFUNC { // integer arithmetic operations 1162068SN/A 1178588Sgblack@eecs.umich.edu 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }}); 1182068SN/A 0x40: addlv({{ 1198588Sgblack@eecs.umich.edu int32_t tmp = Ra_sl + Rb_or_imm_sl; 1202068SN/A // signed overflow occurs when operands have same sign 1212068SN/A // and sign of result does not match. 1228588Sgblack@eecs.umich.edu if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 12310474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 1248588Sgblack@eecs.umich.edu Rc_sl = tmp; 1252068SN/A }}); 1268588Sgblack@eecs.umich.edu 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }}); 1278588Sgblack@eecs.umich.edu 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }}); 1282068SN/A 1292068SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1302068SN/A 0x60: addqv({{ 1312068SN/A uint64_t tmp = Ra + Rb_or_imm; 1322068SN/A // signed overflow occurs when operands have same sign 1332068SN/A // and sign of result does not match. 1342068SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 13510474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 1362068SN/A Rc = tmp; 1372068SN/A }}); 1382068SN/A 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1392068SN/A 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1402068SN/A 1418588Sgblack@eecs.umich.edu 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }}); 1422068SN/A 0x49: sublv({{ 1438588Sgblack@eecs.umich.edu int32_t tmp = Ra_sl - Rb_or_imm_sl; 1442068SN/A // signed overflow detection is same as for add, 1452068SN/A // except we need to look at the *complemented* 1462068SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1472068SN/A // signs are the *same* then no overflow can occur 1488588Sgblack@eecs.umich.edu if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 14910474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 1508588Sgblack@eecs.umich.edu Rc_sl = tmp; 1512068SN/A }}); 1528588Sgblack@eecs.umich.edu 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }}); 1538588Sgblack@eecs.umich.edu 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }}); 1542068SN/A 1552068SN/A 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1562068SN/A 0x69: subqv({{ 1572068SN/A uint64_t tmp = Ra - Rb_or_imm; 1582068SN/A // signed overflow detection is same as for add, 1592068SN/A // except we need to look at the *complemented* 1602068SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1612068SN/A // signs are the *same* then no overflow can occur 1622068SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 16310474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 1642068SN/A Rc = tmp; 1652068SN/A }}); 1662068SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1672068SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1682068SN/A 1692068SN/A 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1708588Sgblack@eecs.umich.edu 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }}); 1718588Sgblack@eecs.umich.edu 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }}); 1728588Sgblack@eecs.umich.edu 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }}); 1738588Sgblack@eecs.umich.edu 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }}); 1742068SN/A 1752068SN/A 0x0f: cmpbge({{ 1762068SN/A int hi = 7; 1772068SN/A int lo = 0; 1782068SN/A uint64_t tmp = 0; 1792068SN/A for (int i = 0; i < 8; ++i) { 1808588Sgblack@eecs.umich.edu tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i; 1812068SN/A hi += 8; 1822068SN/A lo += 8; 1832068SN/A } 1842068SN/A Rc = tmp; 1852068SN/A }}); 1862068SN/A } 1872068SN/A 1887799Sgblack@eecs.umich.edu 0x11: decode INTFUNC { // integer logical operations 1892068SN/A 1902068SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1912068SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1922068SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1932068SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1942068SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1952068SN/A 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1962068SN/A 1972068SN/A // conditional moves 1982068SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1992068SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 2002068SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 2012068SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 2028588Sgblack@eecs.umich.edu 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }}); 2038588Sgblack@eecs.umich.edu 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }}); 2048588Sgblack@eecs.umich.edu 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }}); 2058588Sgblack@eecs.umich.edu 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }}); 2062068SN/A 2072068SN/A // For AMASK, RA must be R31. 2082068SN/A 0x61: decode RA { 2092068SN/A 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 2102068SN/A } 2112068SN/A 2122068SN/A // For IMPLVER, RA must be R31 and the B operand 2132068SN/A // must be the immediate value 1. 2142068SN/A 0x6c: decode RA { 2152068SN/A 31: decode IMM { 2162068SN/A 1: decode INTIMM { 2178738Sgblack@eecs.umich.edu // return EV5 for FullSystem and EV6 otherwise 2188738Sgblack@eecs.umich.edu 1: implver({{ Rc = FullSystem ? 1 : 2 }}); 2192068SN/A } 2202068SN/A } 2212068SN/A } 2222068SN/A 2232068SN/A // The mysterious 11.25... 2242068SN/A 0x25: WarnUnimpl::eleven25(); 2252068SN/A } 2262068SN/A 2272068SN/A 0x12: decode INTFUNC { 2282068SN/A 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2298588Sgblack@eecs.umich.edu 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }}); 2308588Sgblack@eecs.umich.edu 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }}); 2312068SN/A 2322068SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2332068SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2342068SN/A 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2352068SN/A 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2362068SN/A 2372068SN/A 0x52: mskwh({{ 2382068SN/A int bv = Rb_or_imm<2:0>; 2392068SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2402068SN/A }}); 2412068SN/A 0x62: msklh({{ 2422068SN/A int bv = Rb_or_imm<2:0>; 2432068SN/A Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2442068SN/A }}); 2452068SN/A 0x72: mskqh({{ 2462068SN/A int bv = Rb_or_imm<2:0>; 2472068SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2482068SN/A }}); 2492068SN/A 2508588Sgblack@eecs.umich.edu 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2518588Sgblack@eecs.umich.edu 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2528588Sgblack@eecs.umich.edu 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2538588Sgblack@eecs.umich.edu 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }}); 2542068SN/A 2552068SN/A 0x5a: extwh({{ 2562068SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2572068SN/A 0x6a: extlh({{ 2582068SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2592068SN/A 0x7a: extqh({{ 2602068SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2612068SN/A 2622068SN/A 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2632068SN/A 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2642068SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2652068SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2662068SN/A 2672068SN/A 0x57: inswh({{ 2682068SN/A int bv = Rb_or_imm<2:0>; 2698588Sgblack@eecs.umich.edu Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0; 2702068SN/A }}); 2712068SN/A 0x67: inslh({{ 2722068SN/A int bv = Rb_or_imm<2:0>; 2738588Sgblack@eecs.umich.edu Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0; 2742068SN/A }}); 2752068SN/A 0x77: insqh({{ 2762068SN/A int bv = Rb_or_imm<2:0>; 2778588Sgblack@eecs.umich.edu Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0; 2782068SN/A }}); 2792068SN/A 2802068SN/A 0x30: zap({{ 2812068SN/A uint64_t zapmask = 0; 2822068SN/A for (int i = 0; i < 8; ++i) { 2832068SN/A if (Rb_or_imm<i:>) 2842068SN/A zapmask |= (mask(8) << (i * 8)); 2852068SN/A } 2862068SN/A Rc = Ra & ~zapmask; 2872068SN/A }}); 2882068SN/A 0x31: zapnot({{ 2892068SN/A uint64_t zapmask = 0; 2902068SN/A for (int i = 0; i < 8; ++i) { 2912068SN/A if (!Rb_or_imm<i:>) 2922068SN/A zapmask |= (mask(8) << (i * 8)); 2932068SN/A } 2942068SN/A Rc = Ra & ~zapmask; 2952068SN/A }}); 2962068SN/A } 2972068SN/A 2987799Sgblack@eecs.umich.edu 0x13: decode INTFUNC { // integer multiplies 2998588Sgblack@eecs.umich.edu 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp); 3002068SN/A 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 3012068SN/A 0x30: umulh({{ 3022068SN/A uint64_t hi, lo; 3032068SN/A mul128(Ra, Rb_or_imm, hi, lo); 3042068SN/A Rc = hi; 3052068SN/A }}, IntMultOp); 3062068SN/A 0x40: mullv({{ 3072068SN/A // 32-bit multiply with trap on overflow 3088588Sgblack@eecs.umich.edu int64_t Rax = Ra_sl; // sign extended version of Ra_sl 3098588Sgblack@eecs.umich.edu int64_t Rbx = Rb_or_imm_sl; 3102068SN/A int64_t tmp = Rax * Rbx; 3112068SN/A // To avoid overflow, all the upper 32 bits must match 3122068SN/A // the sign bit of the lower 32. We code this as 3132068SN/A // checking the upper 33 bits for all 0s or all 1s. 3142068SN/A uint64_t sign_bits = tmp<63:31>; 3152068SN/A if (sign_bits != 0 && sign_bits != mask(33)) 31610474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 3178588Sgblack@eecs.umich.edu Rc_sl = tmp<31:0>; 3182068SN/A }}, IntMultOp); 3192068SN/A 0x60: mulqv({{ 3202068SN/A // 64-bit multiply with trap on overflow 3212068SN/A uint64_t hi, lo; 3222068SN/A mul128(Ra, Rb_or_imm, hi, lo); 3232068SN/A // all the upper 64 bits must match the sign bit of 3242068SN/A // the lower 64 3252068SN/A if (!((hi == 0 && lo<63:> == 0) || 3262068SN/A (hi == mask(64) && lo<63:> == 1))) 32710474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 3282068SN/A Rc = lo; 3292068SN/A }}, IntMultOp); 3302068SN/A } 3312068SN/A 3322068SN/A 0x1c: decode INTFUNC { 3338588Sgblack@eecs.umich.edu 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); } 3348588Sgblack@eecs.umich.edu 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); } 3356804Ssroy@cse.usf.edu 3366804Ssroy@cse.usf.edu 0x30: ctpop({{ 3376804Ssroy@cse.usf.edu uint64_t count = 0; 3386804Ssroy@cse.usf.edu for (int i = 0; Rb<63:i>; ++i) { 3396804Ssroy@cse.usf.edu if (Rb<i:i> == 0x1) 3406804Ssroy@cse.usf.edu ++count; 3416804Ssroy@cse.usf.edu } 3426804Ssroy@cse.usf.edu Rc = count; 3436804Ssroy@cse.usf.edu }}, IntAluOp); 3446804Ssroy@cse.usf.edu 3456804Ssroy@cse.usf.edu 0x31: perr({{ 3466804Ssroy@cse.usf.edu uint64_t temp = 0; 3476804Ssroy@cse.usf.edu int hi = 7; 3486804Ssroy@cse.usf.edu int lo = 0; 3496804Ssroy@cse.usf.edu for (int i = 0; i < 8; ++i) { 3508588Sgblack@eecs.umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 3518588Sgblack@eecs.umich.edu uint8_t rb_ub = Rb_uq<hi:lo>; 3526804Ssroy@cse.usf.edu temp += (ra_ub >= rb_ub) ? 3536804Ssroy@cse.usf.edu (ra_ub - rb_ub) : (rb_ub - ra_ub); 3546804Ssroy@cse.usf.edu hi += 8; 3556804Ssroy@cse.usf.edu lo += 8; 3566804Ssroy@cse.usf.edu } 3576804Ssroy@cse.usf.edu Rc = temp; 3586804Ssroy@cse.usf.edu }}); 3596804Ssroy@cse.usf.edu 3602068SN/A 0x32: ctlz({{ 3612068SN/A uint64_t count = 0; 3622068SN/A uint64_t temp = Rb; 3632068SN/A if (temp<63:32>) temp >>= 32; else count += 32; 3642068SN/A if (temp<31:16>) temp >>= 16; else count += 16; 3652068SN/A if (temp<15:8>) temp >>= 8; else count += 8; 3662068SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3672068SN/A if (temp<3:2>) temp >>= 2; else count += 2; 3682068SN/A if (temp<1:1>) temp >>= 1; else count += 1; 3692068SN/A if ((temp<0:0>) != 0x1) count += 1; 3702068SN/A Rc = count; 3712068SN/A }}, IntAluOp); 3722068SN/A 3732068SN/A 0x33: cttz({{ 3742068SN/A uint64_t count = 0; 3752068SN/A uint64_t temp = Rb; 3762068SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3772068SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3782068SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3792068SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3802068SN/A if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3816804Ssroy@cse.usf.edu if (!(temp<0:0> & ULL(0x1))) { 3826804Ssroy@cse.usf.edu temp >>= 1; count += 1; 3836804Ssroy@cse.usf.edu } 3842068SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 3852068SN/A Rc = count; 3862068SN/A }}, IntAluOp); 3872068SN/A 3886804Ssroy@cse.usf.edu 3896804Ssroy@cse.usf.edu 0x34: unpkbw({{ 3908588Sgblack@eecs.umich.edu Rc = (Rb_uq<7:0> 3918588Sgblack@eecs.umich.edu | (Rb_uq<15:8> << 16) 3928588Sgblack@eecs.umich.edu | (Rb_uq<23:16> << 32) 3938588Sgblack@eecs.umich.edu | (Rb_uq<31:24> << 48)); 3946804Ssroy@cse.usf.edu }}, IntAluOp); 3956804Ssroy@cse.usf.edu 3966804Ssroy@cse.usf.edu 0x35: unpkbl({{ 3978588Sgblack@eecs.umich.edu Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32)); 3986804Ssroy@cse.usf.edu }}, IntAluOp); 3996804Ssroy@cse.usf.edu 4006804Ssroy@cse.usf.edu 0x36: pkwb({{ 4018588Sgblack@eecs.umich.edu Rc = (Rb_uq<7:0> 4028588Sgblack@eecs.umich.edu | (Rb_uq<23:16> << 8) 4038588Sgblack@eecs.umich.edu | (Rb_uq<39:32> << 16) 4048588Sgblack@eecs.umich.edu | (Rb_uq<55:48> << 24)); 4056804Ssroy@cse.usf.edu }}, IntAluOp); 4066804Ssroy@cse.usf.edu 4076804Ssroy@cse.usf.edu 0x37: pklb({{ 4088588Sgblack@eecs.umich.edu Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8)); 4096804Ssroy@cse.usf.edu }}, IntAluOp); 4106804Ssroy@cse.usf.edu 4116804Ssroy@cse.usf.edu 0x38: minsb8({{ 4126804Ssroy@cse.usf.edu uint64_t temp = 0; 4136804Ssroy@cse.usf.edu int hi = 63; 4146804Ssroy@cse.usf.edu int lo = 56; 4156804Ssroy@cse.usf.edu for (int i = 7; i >= 0; --i) { 4168588Sgblack@eecs.umich.edu int8_t ra_sb = Ra_uq<hi:lo>; 4178588Sgblack@eecs.umich.edu int8_t rb_sb = Rb_uq<hi:lo>; 4186804Ssroy@cse.usf.edu temp = ((temp << 8) 4198588Sgblack@eecs.umich.edu | ((ra_sb < rb_sb) ? Ra_uq<hi:lo> 4208588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 4216804Ssroy@cse.usf.edu hi -= 8; 4226804Ssroy@cse.usf.edu lo -= 8; 4236804Ssroy@cse.usf.edu } 4246804Ssroy@cse.usf.edu Rc = temp; 4256804Ssroy@cse.usf.edu }}); 4266804Ssroy@cse.usf.edu 4276804Ssroy@cse.usf.edu 0x39: minsw4({{ 4286804Ssroy@cse.usf.edu uint64_t temp = 0; 4296804Ssroy@cse.usf.edu int hi = 63; 4306804Ssroy@cse.usf.edu int lo = 48; 4316804Ssroy@cse.usf.edu for (int i = 3; i >= 0; --i) { 4328588Sgblack@eecs.umich.edu int16_t ra_sw = Ra_uq<hi:lo>; 4338588Sgblack@eecs.umich.edu int16_t rb_sw = Rb_uq<hi:lo>; 4346804Ssroy@cse.usf.edu temp = ((temp << 16) 4358588Sgblack@eecs.umich.edu | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 4368588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 4376804Ssroy@cse.usf.edu hi -= 16; 4386804Ssroy@cse.usf.edu lo -= 16; 4396804Ssroy@cse.usf.edu } 4406804Ssroy@cse.usf.edu Rc = temp; 4416804Ssroy@cse.usf.edu }}); 4426804Ssroy@cse.usf.edu 4436804Ssroy@cse.usf.edu 0x3a: minub8({{ 4446804Ssroy@cse.usf.edu uint64_t temp = 0; 4456804Ssroy@cse.usf.edu int hi = 63; 4466804Ssroy@cse.usf.edu int lo = 56; 4476804Ssroy@cse.usf.edu for (int i = 7; i >= 0; --i) { 4488588Sgblack@eecs.umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 4498588Sgblack@eecs.umich.edu uint8_t rb_ub = Rb_uq<hi:lo>; 4506804Ssroy@cse.usf.edu temp = ((temp << 8) 4518588Sgblack@eecs.umich.edu | ((ra_ub < rb_ub) ? Ra_uq<hi:lo> 4528588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 4536804Ssroy@cse.usf.edu hi -= 8; 4546804Ssroy@cse.usf.edu lo -= 8; 4556804Ssroy@cse.usf.edu } 4566804Ssroy@cse.usf.edu Rc = temp; 4576804Ssroy@cse.usf.edu }}); 4586804Ssroy@cse.usf.edu 4596804Ssroy@cse.usf.edu 0x3b: minuw4({{ 4606804Ssroy@cse.usf.edu uint64_t temp = 0; 4616804Ssroy@cse.usf.edu int hi = 63; 4626804Ssroy@cse.usf.edu int lo = 48; 4636804Ssroy@cse.usf.edu for (int i = 3; i >= 0; --i) { 4648588Sgblack@eecs.umich.edu uint16_t ra_sw = Ra_uq<hi:lo>; 4658588Sgblack@eecs.umich.edu uint16_t rb_sw = Rb_uq<hi:lo>; 4666804Ssroy@cse.usf.edu temp = ((temp << 16) 4678588Sgblack@eecs.umich.edu | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 4688588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 4696804Ssroy@cse.usf.edu hi -= 16; 4706804Ssroy@cse.usf.edu lo -= 16; 4716804Ssroy@cse.usf.edu } 4726804Ssroy@cse.usf.edu Rc = temp; 4736804Ssroy@cse.usf.edu }}); 4746804Ssroy@cse.usf.edu 4756804Ssroy@cse.usf.edu 0x3c: maxub8({{ 4766804Ssroy@cse.usf.edu uint64_t temp = 0; 4776804Ssroy@cse.usf.edu int hi = 63; 4786804Ssroy@cse.usf.edu int lo = 56; 4796804Ssroy@cse.usf.edu for (int i = 7; i >= 0; --i) { 4808588Sgblack@eecs.umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 4818588Sgblack@eecs.umich.edu uint8_t rb_ub = Rb_uq<hi:lo>; 4826804Ssroy@cse.usf.edu temp = ((temp << 8) 4838588Sgblack@eecs.umich.edu | ((ra_ub > rb_ub) ? Ra_uq<hi:lo> 4848588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 4856804Ssroy@cse.usf.edu hi -= 8; 4866804Ssroy@cse.usf.edu lo -= 8; 4876804Ssroy@cse.usf.edu } 4886804Ssroy@cse.usf.edu Rc = temp; 4896804Ssroy@cse.usf.edu }}); 4906804Ssroy@cse.usf.edu 4916804Ssroy@cse.usf.edu 0x3d: maxuw4({{ 4926804Ssroy@cse.usf.edu uint64_t temp = 0; 4936804Ssroy@cse.usf.edu int hi = 63; 4946804Ssroy@cse.usf.edu int lo = 48; 4956804Ssroy@cse.usf.edu for (int i = 3; i >= 0; --i) { 4968588Sgblack@eecs.umich.edu uint16_t ra_uw = Ra_uq<hi:lo>; 4978588Sgblack@eecs.umich.edu uint16_t rb_uw = Rb_uq<hi:lo>; 4986804Ssroy@cse.usf.edu temp = ((temp << 16) 4998588Sgblack@eecs.umich.edu | ((ra_uw > rb_uw) ? Ra_uq<hi:lo> 5008588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 5016804Ssroy@cse.usf.edu hi -= 16; 5026804Ssroy@cse.usf.edu lo -= 16; 5036804Ssroy@cse.usf.edu } 5046804Ssroy@cse.usf.edu Rc = temp; 5056804Ssroy@cse.usf.edu }}); 5066804Ssroy@cse.usf.edu 5076804Ssroy@cse.usf.edu 0x3e: maxsb8({{ 5086804Ssroy@cse.usf.edu uint64_t temp = 0; 5096804Ssroy@cse.usf.edu int hi = 63; 5106804Ssroy@cse.usf.edu int lo = 56; 5116804Ssroy@cse.usf.edu for (int i = 7; i >= 0; --i) { 5128588Sgblack@eecs.umich.edu int8_t ra_sb = Ra_uq<hi:lo>; 5138588Sgblack@eecs.umich.edu int8_t rb_sb = Rb_uq<hi:lo>; 5146804Ssroy@cse.usf.edu temp = ((temp << 8) 5158588Sgblack@eecs.umich.edu | ((ra_sb > rb_sb) ? Ra_uq<hi:lo> 5168588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 5176804Ssroy@cse.usf.edu hi -= 8; 5186804Ssroy@cse.usf.edu lo -= 8; 5196804Ssroy@cse.usf.edu } 5206804Ssroy@cse.usf.edu Rc = temp; 5216804Ssroy@cse.usf.edu }}); 5226804Ssroy@cse.usf.edu 5236804Ssroy@cse.usf.edu 0x3f: maxsw4({{ 5246804Ssroy@cse.usf.edu uint64_t temp = 0; 5256804Ssroy@cse.usf.edu int hi = 63; 5266804Ssroy@cse.usf.edu int lo = 48; 5276804Ssroy@cse.usf.edu for (int i = 3; i >= 0; --i) { 5288588Sgblack@eecs.umich.edu int16_t ra_sw = Ra_uq<hi:lo>; 5298588Sgblack@eecs.umich.edu int16_t rb_sw = Rb_uq<hi:lo>; 5306804Ssroy@cse.usf.edu temp = ((temp << 16) 5318588Sgblack@eecs.umich.edu | ((ra_sw > rb_sw) ? Ra_uq<hi:lo> 5328588Sgblack@eecs.umich.edu : Rb_uq<hi:lo>)); 5336804Ssroy@cse.usf.edu hi -= 16; 5346804Ssroy@cse.usf.edu lo -= 16; 5356804Ssroy@cse.usf.edu } 5366804Ssroy@cse.usf.edu Rc = temp; 5376804Ssroy@cse.usf.edu }}); 5382068SN/A 5392068SN/A format BasicOperateWithNopCheck { 5402068SN/A 0x70: decode RB { 5418588Sgblack@eecs.umich.edu 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp); 5422068SN/A } 5432068SN/A 0x78: decode RB { 5448588Sgblack@eecs.umich.edu 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }}, 5452068SN/A FloatCvtOp); 5462068SN/A } 5472068SN/A } 5482068SN/A } 5492068SN/A } 5502068SN/A 5512068SN/A // Conditional branches. 5522068SN/A format CondBranch { 5532068SN/A 0x39: beq({{ cond = (Ra == 0); }}); 5542068SN/A 0x3d: bne({{ cond = (Ra != 0); }}); 5558588Sgblack@eecs.umich.edu 0x3e: bge({{ cond = (Ra_sq >= 0); }}); 5568588Sgblack@eecs.umich.edu 0x3f: bgt({{ cond = (Ra_sq > 0); }}); 5578588Sgblack@eecs.umich.edu 0x3b: ble({{ cond = (Ra_sq <= 0); }}); 5588588Sgblack@eecs.umich.edu 0x3a: blt({{ cond = (Ra_sq < 0); }}); 5592068SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 5602068SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 5612068SN/A 5622068SN/A 0x31: fbeq({{ cond = (Fa == 0); }}); 5632068SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 5642068SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 5652068SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 5662068SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 5672068SN/A 0x32: fblt({{ cond = (Fa < 0); }}); 5682068SN/A } 5692068SN/A 5702068SN/A // unconditional branches 5712068SN/A format UncondBranch { 5722068SN/A 0x30: br(); 5732068SN/A 0x34: bsr(IsCall); 5742068SN/A } 5752068SN/A 5762068SN/A // indirect branches 5772068SN/A 0x1a: decode JMPFUNC { 5782068SN/A format Jump { 5792068SN/A 0: jmp(); 5802068SN/A 1: jsr(IsCall); 5812068SN/A 2: ret(IsReturn); 5822068SN/A 3: jsr_coroutine(IsCall, IsReturn); 5832068SN/A } 5842068SN/A } 5852068SN/A 5862068SN/A // Square root and integer-to-FP moves 5872068SN/A 0x14: decode FP_SHORTFUNC { 5882068SN/A // Integer to FP register moves must have RB == 31 5892068SN/A 0x4: decode RB { 5902068SN/A 31: decode FP_FULLFUNC { 5912068SN/A format BasicOperateWithNopCheck { 5928588Sgblack@eecs.umich.edu 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp); 5938588Sgblack@eecs.umich.edu 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp); 5947799Sgblack@eecs.umich.edu 0x014: FailUnimpl::itoff(); // VAX-format conversion 5952068SN/A } 5962068SN/A } 5972068SN/A } 5982068SN/A 5992068SN/A // Square root instructions must have FA == 31 6002068SN/A 0xb: decode FA { 6012068SN/A 31: decode FP_TYPEFUNC { 6022068SN/A format FloatingPointOperate { 6032068SN/A#if SS_COMPATIBLE_FP 6042068SN/A 0x0b: sqrts({{ 6052068SN/A if (Fb < 0.0) 60610474Sandreas.hansson@arm.com fault = std::make_shared<ArithmeticFault>(); 6072068SN/A Fc = sqrt(Fb); 6082068SN/A }}, FloatSqrtOp); 6092068SN/A#else 6102068SN/A 0x0b: sqrts({{ 6118588Sgblack@eecs.umich.edu if (Fb_sf < 0.0) 61210474Sandreas.hansson@arm.com fault = std::make_shared<ArithmeticFault>(); 6138588Sgblack@eecs.umich.edu Fc_sf = sqrt(Fb_sf); 6142068SN/A }}, FloatSqrtOp); 6152068SN/A#endif 6162068SN/A 0x2b: sqrtt({{ 6172068SN/A if (Fb < 0.0) 61810474Sandreas.hansson@arm.com fault = std::make_shared<ArithmeticFault>(); 6192068SN/A Fc = sqrt(Fb); 6202068SN/A }}, FloatSqrtOp); 6212068SN/A } 6222068SN/A } 6232068SN/A } 6242068SN/A 6252068SN/A // VAX-format sqrtf and sqrtg are not implemented 6262068SN/A 0xa: FailUnimpl::sqrtfg(); 6272068SN/A } 6282068SN/A 6292068SN/A // IEEE floating point 6302068SN/A 0x16: decode FP_SHORTFUNC_TOP2 { 6312068SN/A // The top two bits of the short function code break this 6322068SN/A // space into four groups: binary ops, compares, reserved, and 6332068SN/A // conversions. See Table 4-12 of AHB. There are different 6342068SN/A // special cases in these different groups, so we decode on 6352068SN/A // these top two bits first just to select a decode strategy. 6362068SN/A // Most of these instructions may have various trapping and 6372068SN/A // rounding mode flags set; these are decoded in the 6382068SN/A // FloatingPointDecode template used by the 6392068SN/A // FloatingPointOperate format. 6402068SN/A 6412068SN/A // add/sub/mul/div: just decode on the short function code 6422068SN/A // and source type. All valid trapping and rounding modes apply. 6432068SN/A 0: decode FP_TRAPMODE { 6442068SN/A // check for valid trapping modes here 6452068SN/A 0,1,5,7: decode FP_TYPEFUNC { 6462068SN/A format FloatingPointOperate { 6472068SN/A#if SS_COMPATIBLE_FP 6482068SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 6492068SN/A 0x01: subs({{ Fc = Fa - Fb; }}); 6502068SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 6512068SN/A 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 6522068SN/A#else 6538588Sgblack@eecs.umich.edu 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); 6548588Sgblack@eecs.umich.edu 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); 6558588Sgblack@eecs.umich.edu 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); 6568588Sgblack@eecs.umich.edu 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); 6572068SN/A#endif 6582068SN/A 6592068SN/A 0x20: addt({{ Fc = Fa + Fb; }}); 6602068SN/A 0x21: subt({{ Fc = Fa - Fb; }}); 6612068SN/A 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 6622068SN/A 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 6632068SN/A } 6642068SN/A } 6652068SN/A } 6662068SN/A 6672068SN/A // Floating-point compare instructions must have the default 6682068SN/A // rounding mode, and may use the default trapping mode or 6692068SN/A // /SU. Both trapping modes are treated the same by M5; the 6702068SN/A // only difference on the real hardware (as far a I can tell) 6712068SN/A // is that without /SU you'd get an imprecise trap if you 6722068SN/A // tried to compare a NaN with something else (instead of an 6732068SN/A // "unordered" result). 6742068SN/A 1: decode FP_FULLFUNC { 6752068SN/A format BasicOperateWithNopCheck { 6762068SN/A 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 6772068SN/A FloatCmpOp); 6782068SN/A 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 6792068SN/A FloatCmpOp); 6802068SN/A 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 6812068SN/A FloatCmpOp); 6822068SN/A 0x0a4, 0x5a4: cmptun({{ // unordered 6832068SN/A Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 6842068SN/A }}, FloatCmpOp); 6852068SN/A } 6862068SN/A } 6872068SN/A 6882068SN/A // The FP-to-integer and integer-to-FP conversion insts 6892068SN/A // require that FA be 31. 6902068SN/A 3: decode FA { 6912068SN/A 31: decode FP_TYPEFUNC { 6922068SN/A format FloatingPointOperate { 6932068SN/A 0x2f: decode FP_ROUNDMODE { 6942068SN/A format FPFixedRounding { 6952068SN/A // "chopped" i.e. round toward zero 6968588Sgblack@eecs.umich.edu 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }}, 6972068SN/A Chopped); 6982068SN/A // round to minus infinity 6998588Sgblack@eecs.umich.edu 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }}, 7002068SN/A MinusInfinity); 7012068SN/A } 7028588Sgblack@eecs.umich.edu default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }}); 7032068SN/A } 7042068SN/A 7052068SN/A // The cvtts opcode is overloaded to be cvtst if the trap 7062068SN/A // mode is 2 or 6 (which are not valid otherwise) 7072068SN/A 0x2c: decode FP_FULLFUNC { 7082068SN/A format BasicOperateWithNopCheck { 7092068SN/A // trap on denorm version "cvtst/s" is 7102068SN/A // simulated same as cvtst 7118588Sgblack@eecs.umich.edu 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }}); 7122068SN/A } 7138588Sgblack@eecs.umich.edu default: cvtts({{ Fc_sf = Fb; }}); 7142068SN/A } 7152068SN/A 7162068SN/A // The trapping mode for integer-to-FP conversions 7172068SN/A // must be /SUI or nothing; /U and /SU are not 7182068SN/A // allowed. The full set of rounding modes are 7192068SN/A // supported though. 7202068SN/A 0x3c: decode FP_TRAPMODE { 7218588Sgblack@eecs.umich.edu 0,7: cvtqs({{ Fc_sf = Fb_sq; }}); 7222068SN/A } 7232068SN/A 0x3e: decode FP_TRAPMODE { 7248588Sgblack@eecs.umich.edu 0,7: cvtqt({{ Fc = Fb_sq; }}); 7252068SN/A } 7262068SN/A } 7272068SN/A } 7282068SN/A } 7292068SN/A } 7302068SN/A 7312068SN/A // misc FP operate 7322068SN/A 0x17: decode FP_FULLFUNC { 7332068SN/A format BasicOperateWithNopCheck { 7342068SN/A 0x010: cvtlq({{ 7358588Sgblack@eecs.umich.edu Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>; 7362068SN/A }}); 7372068SN/A 0x030: cvtql({{ 7388588Sgblack@eecs.umich.edu Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 7392068SN/A }}); 7402068SN/A 7412068SN/A // We treat the precise & imprecise trapping versions of 7422068SN/A // cvtql identically. 7432068SN/A 0x130, 0x530: cvtqlv({{ 7442068SN/A // To avoid overflow, all the upper 32 bits must match 7452068SN/A // the sign bit of the lower 32. We code this as 7462068SN/A // checking the upper 33 bits for all 0s or all 1s. 7478588Sgblack@eecs.umich.edu uint64_t sign_bits = Fb_uq<63:31>; 7482068SN/A if (sign_bits != 0 && sign_bits != mask(33)) 74910474Sandreas.hansson@arm.com fault = std::make_shared<IntegerOverflowFault>(); 7508588Sgblack@eecs.umich.edu Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 7512068SN/A }}); 7522068SN/A 7532068SN/A 0x020: cpys({{ // copy sign 7548588Sgblack@eecs.umich.edu Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>; 7552068SN/A }}); 7562068SN/A 0x021: cpysn({{ // copy sign negated 7578588Sgblack@eecs.umich.edu Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>; 7582068SN/A }}); 7592068SN/A 0x022: cpyse({{ // copy sign and exponent 7608588Sgblack@eecs.umich.edu Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>; 7612068SN/A }}); 7622068SN/A 7632068SN/A 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 7642068SN/A 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 7652068SN/A 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 7662068SN/A 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 7672068SN/A 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 7682068SN/A 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 7692068SN/A 7708588Sgblack@eecs.umich.edu 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess); 7718588Sgblack@eecs.umich.edu 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess); 7722068SN/A } 7732068SN/A } 7742068SN/A 7752068SN/A // miscellaneous mem-format ops 7762068SN/A 0x18: decode MEMFUNC { 7772068SN/A format WarnUnimpl { 7782068SN/A 0x8000: fetch(); 7792068SN/A 0xa000: fetch_m(); 7802068SN/A 0xe800: ecb(); 7812068SN/A } 7822068SN/A 7832068SN/A format MiscPrefetch { 7842068SN/A 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 7857725SAli.Saidi@ARM.com {{ ; }}, 7867725SAli.Saidi@ARM.com mem_flags = PREFETCH); 7872068SN/A } 7882068SN/A 7892068SN/A format BasicOperate { 7902068SN/A 0xc000: rpcc({{ 7918560Sgblack@eecs.umich.edu /* Rb is a fake dependency so here is a fun way to get 7928560Sgblack@eecs.umich.edu * the parser to understand that. 7938560Sgblack@eecs.umich.edu */ 7948560Sgblack@eecs.umich.edu uint64_t unused_var M5_VAR_USED = Rb; 7958738Sgblack@eecs.umich.edu Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick(); 7962312SN/A }}, IsUnverifiable); 7972068SN/A 7982068SN/A // All of the barrier instructions below do nothing in 7992068SN/A // their execute() methods (hence the empty code blocks). 8002068SN/A // All of their functionality is hard-coded in the 8012068SN/A // pipeline based on the flags IsSerializing, 8022068SN/A // IsMemBarrier, and IsWriteBarrier. In the current 8032068SN/A // detailed CPU model, the execute() function only gets 8042068SN/A // called at fetch, so there's no way to generate pipeline 8052068SN/A // behavior at any other stage. Once we go to an 8062068SN/A // exec-in-exec CPU model we should be able to get rid of 8072068SN/A // these flags and implement this behavior via the 8082068SN/A // execute() methods. 8092068SN/A 8102068SN/A // trapb is just a barrier on integer traps, where excb is 8112068SN/A // a barrier on integer and FP traps. "EXCB is thus a 8122068SN/A // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 8132068SN/A // them the same though. 8142292SN/A 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 8152292SN/A 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 8162068SN/A 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 8172068SN/A 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 8182068SN/A } 8192068SN/A 8208901Sandreas.hansson@arm.com 0xe000: decode FullSystemInt { 8218560Sgblack@eecs.umich.edu 0: FailUnimpl::rc_se(); 8228560Sgblack@eecs.umich.edu default: BasicOperate::rc({{ 8233454Sgblack@eecs.umich.edu Ra = IntrFlag; 8243454Sgblack@eecs.umich.edu IntrFlag = 0; 8252704Sktlim@umich.edu }}, IsNonSpeculative, IsUnverifiable); 8268560Sgblack@eecs.umich.edu } 8278901Sandreas.hansson@arm.com 0xf000: decode FullSystemInt { 8288560Sgblack@eecs.umich.edu 0: FailUnimpl::rs_se(); 8298560Sgblack@eecs.umich.edu default: BasicOperate::rs({{ 8303454Sgblack@eecs.umich.edu Ra = IntrFlag; 8313454Sgblack@eecs.umich.edu IntrFlag = 1; 8322704Sktlim@umich.edu }}, IsNonSpeculative, IsUnverifiable); 8332068SN/A } 8342068SN/A } 8352068SN/A 8368901Sandreas.hansson@arm.com 0x00: decode FullSystemInt { 8378780Sgblack@eecs.umich.edu 0: decode PALFUNC { 8388780Sgblack@eecs.umich.edu format EmulatedCallPal { 8398780Sgblack@eecs.umich.edu 0x00: halt ({{ 8408780Sgblack@eecs.umich.edu exitSimLoop("halt instruction encountered"); 8418780Sgblack@eecs.umich.edu }}, IsNonSpeculative); 8428780Sgblack@eecs.umich.edu 0x83: callsys({{ 8438780Sgblack@eecs.umich.edu xc->syscall(R0); 8448780Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 8458780Sgblack@eecs.umich.edu // Read uniq reg into ABI return value register (r0) 8468780Sgblack@eecs.umich.edu 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 8478780Sgblack@eecs.umich.edu // Write uniq reg with value from ABI arg register (r16) 8488780Sgblack@eecs.umich.edu 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 8492068SN/A } 8502068SN/A } 8518780Sgblack@eecs.umich.edu default: CallPal::call_pal({{ 8528780Sgblack@eecs.umich.edu if (!palValid || 8538780Sgblack@eecs.umich.edu (palPriv 8548780Sgblack@eecs.umich.edu && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 8558780Sgblack@eecs.umich.edu // invalid pal function code, or attempt to do privileged 8568780Sgblack@eecs.umich.edu // PAL call in non-kernel mode 85710474Sandreas.hansson@arm.com fault = std::make_shared<UnimplementedOpcodeFault>(); 8588780Sgblack@eecs.umich.edu } else { 8598780Sgblack@eecs.umich.edu // check to see if simulator wants to do something special 8608780Sgblack@eecs.umich.edu // on this PAL call (including maybe suppress it) 8618780Sgblack@eecs.umich.edu bool dopal = xc->simPalCheck(palFunc); 8628780Sgblack@eecs.umich.edu 8638780Sgblack@eecs.umich.edu if (dopal) { 8648780Sgblack@eecs.umich.edu xc->setMiscReg(IPR_EXC_ADDR, NPC); 8658780Sgblack@eecs.umich.edu NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 8668780Sgblack@eecs.umich.edu } 8678780Sgblack@eecs.umich.edu } 8688780Sgblack@eecs.umich.edu }}, IsNonSpeculative); 8692068SN/A } 8702068SN/A 8712227SN/A 0x1b: decode PALMODE { 8722227SN/A 0: OpcdecFault::hw_st_quad(); 8732227SN/A 1: decode HW_LDST_QUAD { 8742227SN/A format HwLoad { 8758588Sgblack@eecs.umich.edu 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }}, 8764036Sktlim@umich.edu L, IsSerializing, IsSerializeBefore); 8778588Sgblack@eecs.umich.edu 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }}, 8784036Sktlim@umich.edu Q, IsSerializing, IsSerializeBefore); 8792227SN/A } 8802068SN/A } 8812069SN/A } 8822068SN/A 8832227SN/A 0x1f: decode PALMODE { 8842227SN/A 0: OpcdecFault::hw_st_cond(); 8852227SN/A format HwStore { 8862227SN/A 1: decode HW_LDST_COND { 8872227SN/A 0: decode HW_LDST_QUAD { 8882227SN/A 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 8898588Sgblack@eecs.umich.edu {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 8902227SN/A 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 8918588Sgblack@eecs.umich.edu {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore); 8922227SN/A } 8932227SN/A 8942227SN/A 1: FailUnimpl::hw_st_cond(); 8952068SN/A } 8962068SN/A } 8972068SN/A } 8982068SN/A 8992227SN/A 0x19: decode PALMODE { 9002227SN/A 0: OpcdecFault::hw_mfpr(); 9012227SN/A format HwMoveIPR { 9022227SN/A 1: hw_mfpr({{ 9033469Sgblack@eecs.umich.edu int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 9043464Sgblack@eecs.umich.edu IprToMiscRegIndex[ipr_index] : -1; 9053464Sgblack@eecs.umich.edu if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 9063466Sgblack@eecs.umich.edu miscRegIndex >= NumInternalProcRegs) 90710474Sandreas.hansson@arm.com fault = std::make_shared<UnimplementedOpcodeFault>(); 9083457Sgblack@eecs.umich.edu else 9094172Ssaidi@eecs.umich.edu Ra = xc->readMiscReg(miscRegIndex); 9102336SN/A }}, IsIprAccess); 9112227SN/A } 9122227SN/A } 9132227SN/A 9142227SN/A 0x1d: decode PALMODE { 9152227SN/A 0: OpcdecFault::hw_mtpr(); 9162227SN/A format HwMoveIPR { 9172227SN/A 1: hw_mtpr({{ 9183469Sgblack@eecs.umich.edu int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 9193464Sgblack@eecs.umich.edu IprToMiscRegIndex[ipr_index] : -1; 9203467Sgblack@eecs.umich.edu if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 9213466Sgblack@eecs.umich.edu miscRegIndex >= NumInternalProcRegs) 92210474Sandreas.hansson@arm.com fault = std::make_shared<UnimplementedOpcodeFault>(); 9233457Sgblack@eecs.umich.edu else 9244172Ssaidi@eecs.umich.edu xc->setMiscReg(miscRegIndex, Ra); 9252068SN/A if (traceData) { traceData->setData(Ra); } 9262336SN/A }}, IsIprAccess); 9272227SN/A } 9282068SN/A } 9292068SN/A 9305780Ssteve.reinhardt@amd.com 0x1e: decode PALMODE { 9315780Ssteve.reinhardt@amd.com 0: OpcdecFault::hw_rei(); 9325780Ssteve.reinhardt@amd.com format BasicOperate { 9338457Sksewell@umich.edu 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 9345780Ssteve.reinhardt@amd.com } 9355780Ssteve.reinhardt@amd.com } 9365780Ssteve.reinhardt@amd.com 9372068SN/A format BasicOperate { 9382068SN/A // M5 special opcodes use the reserved 0x01 opcode space 9392068SN/A 0x01: decode M5FUNC { 9402068SN/A 0x00: arm({{ 9414090Ssaidi@eecs.umich.edu PseudoInst::arm(xc->tcBase()); 9422068SN/A }}, IsNonSpeculative); 9432068SN/A 0x01: quiesce({{ 9449829Sandreas.hansson@arm.com // Don't sleep if (unmasked) interrupts are pending 9459829Sandreas.hansson@arm.com Interrupts* interrupts = 9469829Sandreas.hansson@arm.com xc->tcBase()->getCpuPtr()->getInterruptController(); 9479829Sandreas.hansson@arm.com if (interrupts->checkInterrupts(xc->tcBase())) { 9489829Sandreas.hansson@arm.com PseudoInst::quiesceSkip(xc->tcBase()); 9499829Sandreas.hansson@arm.com } else { 9509829Sandreas.hansson@arm.com PseudoInst::quiesce(xc->tcBase()); 9519829Sandreas.hansson@arm.com } 9522292SN/A }}, IsNonSpeculative, IsQuiesce); 9532188SN/A 0x02: quiesceNs({{ 9544090Ssaidi@eecs.umich.edu PseudoInst::quiesceNs(xc->tcBase(), R16); 9552292SN/A }}, IsNonSpeculative, IsQuiesce); 9562188SN/A 0x03: quiesceCycles({{ 9574090Ssaidi@eecs.umich.edu PseudoInst::quiesceCycles(xc->tcBase(), R16); 9582355SN/A }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 9592188SN/A 0x04: quiesceTime({{ 9604090Ssaidi@eecs.umich.edu R0 = PseudoInst::quiesceTime(xc->tcBase()); 9612355SN/A }}, IsNonSpeculative, IsUnverifiable); 9625741Snate@binkert.org 0x07: rpns({{ 9635741Snate@binkert.org R0 = PseudoInst::rpns(xc->tcBase()); 9645741Snate@binkert.org }}, IsNonSpeculative, IsUnverifiable); 9655808Snate@binkert.org 0x09: wakeCPU({{ 9665808Snate@binkert.org PseudoInst::wakeCPU(xc->tcBase(), R16); 9675808Snate@binkert.org }}, IsNonSpeculative, IsUnverifiable); 9685505Snate@binkert.org 0x10: deprecated_ivlb({{ 9695505Snate@binkert.org warn_once("Obsolete M5 ivlb instruction encountered.\n"); 9703680Sstever@eecs.umich.edu }}); 9715505Snate@binkert.org 0x11: deprecated_ivle({{ 9725505Snate@binkert.org warn_once("Obsolete M5 ivlb instruction encountered.\n"); 9733680Sstever@eecs.umich.edu }}); 9745505Snate@binkert.org 0x20: deprecated_exit ({{ 9755505Snate@binkert.org warn_once("deprecated M5 exit instruction encountered.\n"); 9765505Snate@binkert.org PseudoInst::m5exit(xc->tcBase(), 0); 9772068SN/A }}, No_OpClass, IsNonSpeculative); 9782068SN/A 0x21: m5exit({{ 9794090Ssaidi@eecs.umich.edu PseudoInst::m5exit(xc->tcBase(), R16); 9802068SN/A }}, No_OpClass, IsNonSpeculative); 9812358SN/A 0x31: loadsymbol({{ 9824090Ssaidi@eecs.umich.edu PseudoInst::loadsymbol(xc->tcBase()); 9832358SN/A }}, No_OpClass, IsNonSpeculative); 9845505Snate@binkert.org 0x30: initparam({{ 9858555Sgblack@eecs.umich.edu Ra = PseudoInst::initParam(xc->tcBase()); 9865505Snate@binkert.org }}); 9872068SN/A 0x40: resetstats({{ 9884090Ssaidi@eecs.umich.edu PseudoInst::resetstats(xc->tcBase(), R16, R17); 9892068SN/A }}, IsNonSpeculative); 9902068SN/A 0x41: dumpstats({{ 9914090Ssaidi@eecs.umich.edu PseudoInst::dumpstats(xc->tcBase(), R16, R17); 9922068SN/A }}, IsNonSpeculative); 9932068SN/A 0x42: dumpresetstats({{ 9944090Ssaidi@eecs.umich.edu PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 9952068SN/A }}, IsNonSpeculative); 9962068SN/A 0x43: m5checkpoint({{ 9974090Ssaidi@eecs.umich.edu PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 9982068SN/A }}, IsNonSpeculative); 9992068SN/A 0x50: m5readfile({{ 10004090Ssaidi@eecs.umich.edu R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 10012068SN/A }}, IsNonSpeculative); 10022068SN/A 0x51: m5break({{ 10034090Ssaidi@eecs.umich.edu PseudoInst::debugbreak(xc->tcBase()); 10042068SN/A }}, IsNonSpeculative); 10052068SN/A 0x52: m5switchcpu({{ 10064090Ssaidi@eecs.umich.edu PseudoInst::switchcpu(xc->tcBase()); 10072068SN/A }}, IsNonSpeculative); 10082068SN/A 0x53: m5addsymbol({{ 10094090Ssaidi@eecs.umich.edu PseudoInst::addsymbol(xc->tcBase(), R16, R17); 10102068SN/A }}, IsNonSpeculative); 10112188SN/A 0x54: m5panic({{ 10127794Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc = %#x.", PC); 10132188SN/A }}, IsNonSpeculative); 10145952Ssaidi@eecs.umich.edu#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 10155952Ssaidi@eecs.umich.edu 0x55: decode RA { 10165952Ssaidi@eecs.umich.edu 0x00: m5a_old({{ 10177794Sgblack@eecs.umich.edu panic("Deprecated M5 annotate instruction executed " 10187794Sgblack@eecs.umich.edu "at pc = %#x\n", PC); 10195952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10205952Ssaidi@eecs.umich.edu 0x01: m5a_bsm({{ 10215952Ssaidi@eecs.umich.edu CPANN(swSmBegin); 10225952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10235952Ssaidi@eecs.umich.edu 0x02: m5a_esm({{ 10245952Ssaidi@eecs.umich.edu CPANN(swSmEnd); 10255952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10265952Ssaidi@eecs.umich.edu 0x03: m5a_begin({{ 10275952Ssaidi@eecs.umich.edu CPANN(swExplictBegin); 10285952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10295952Ssaidi@eecs.umich.edu 0x04: m5a_end({{ 10305952Ssaidi@eecs.umich.edu CPANN(swEnd); 10315952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10325952Ssaidi@eecs.umich.edu 0x06: m5a_q({{ 10335952Ssaidi@eecs.umich.edu CPANN(swQ); 10345952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10355952Ssaidi@eecs.umich.edu 0x07: m5a_dq({{ 10365952Ssaidi@eecs.umich.edu CPANN(swDq); 10375952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10385952Ssaidi@eecs.umich.edu 0x08: m5a_wf({{ 10395952Ssaidi@eecs.umich.edu CPANN(swWf); 10405952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10415952Ssaidi@eecs.umich.edu 0x09: m5a_we({{ 10425952Ssaidi@eecs.umich.edu CPANN(swWe); 10435952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10445952Ssaidi@eecs.umich.edu 0x0C: m5a_sq({{ 10455952Ssaidi@eecs.umich.edu CPANN(swSq); 10465952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10475952Ssaidi@eecs.umich.edu 0x0D: m5a_aq({{ 10485952Ssaidi@eecs.umich.edu CPANN(swAq); 10495952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10505952Ssaidi@eecs.umich.edu 0x0E: m5a_pq({{ 10515952Ssaidi@eecs.umich.edu CPANN(swPq); 10525952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10535952Ssaidi@eecs.umich.edu 0x0F: m5a_l({{ 10545952Ssaidi@eecs.umich.edu CPANN(swLink); 10555952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10565952Ssaidi@eecs.umich.edu 0x10: m5a_identify({{ 10575952Ssaidi@eecs.umich.edu CPANN(swIdentify); 10585952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10595952Ssaidi@eecs.umich.edu 0x11: m5a_getid({{ 10605952Ssaidi@eecs.umich.edu R0 = CPANN(swGetId); 10615952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10625952Ssaidi@eecs.umich.edu 0x13: m5a_scl({{ 10635952Ssaidi@eecs.umich.edu CPANN(swSyscallLink); 10645952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10655952Ssaidi@eecs.umich.edu 0x14: m5a_rq({{ 10665952Ssaidi@eecs.umich.edu CPANN(swRq); 10675952Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10685952Ssaidi@eecs.umich.edu } // M5 Annotate Operations 10695952Ssaidi@eecs.umich.edu#undef CPANN 10705505Snate@binkert.org 0x56: m5reserved2({{ 10715505Snate@binkert.org warn("M5 reserved opcode ignored"); 10725505Snate@binkert.org }}, IsNonSpeculative); 10735505Snate@binkert.org 0x57: m5reserved3({{ 10745505Snate@binkert.org warn("M5 reserved opcode ignored"); 10755505Snate@binkert.org }}, IsNonSpeculative); 10765505Snate@binkert.org 0x58: m5reserved4({{ 10775505Snate@binkert.org warn("M5 reserved opcode ignored"); 10785505Snate@binkert.org }}, IsNonSpeculative); 10795505Snate@binkert.org 0x59: m5reserved5({{ 10805505Snate@binkert.org warn("M5 reserved opcode ignored"); 10813089Ssaidi@eecs.umich.edu }}, IsNonSpeculative); 10822068SN/A } 10832068SN/A } 10842068SN/A} 1085