branch.isa revision 3953:300d526414e6
1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Control transfer instructions 34// 35 36output header {{ 37 38 /** 39 * Base class for instructions whose disassembly is not purely a 40 * function of the machine instruction (i.e., it depends on the 41 * PC). This class overrides the disassemble() method to check 42 * the PC and symbol table values before re-using a cached 43 * disassembly string. This is necessary for branches and jumps, 44 * where the disassembly string includes the target address (which 45 * may depend on the PC and/or symbol table). 46 */ 47 class PCDependentDisassembly : public AlphaStaticInst 48 { 49 protected: 50 /// Cached program counter from last disassembly 51 mutable Addr cachedPC; 52 /// Cached symbol table pointer from last disassembly 53 mutable const SymbolTable *cachedSymtab; 54 55 /// Constructor 56 PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, 57 OpClass __opClass) 58 : AlphaStaticInst(mnem, _machInst, __opClass), 59 cachedPC(0), cachedSymtab(0) 60 { 61 } 62 63 const std::string & 64 disassemble(Addr pc, const SymbolTable *symtab) const; 65 }; 66 67 /** 68 * Base class for branches (PC-relative control transfers), 69 * conditional or unconditional. 70 */ 71 class Branch : public PCDependentDisassembly 72 { 73 protected: 74 /// Displacement to target address (signed). 75 int32_t disp; 76 77 /// Constructor. 78 Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 79 : PCDependentDisassembly(mnem, _machInst, __opClass), 80 disp(BRDISP << 2) 81 { 82 } 83 84 Addr branchTarget(Addr branchPC) const; 85 86 std::string 87 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 88 }; 89 90 /** 91 * Base class for jumps (register-indirect control transfers). In 92 * the Alpha ISA, these are always unconditional. 93 */ 94 class Jump : public PCDependentDisassembly 95 { 96 protected: 97 98 /// Displacement to target address (signed). 99 int32_t disp; 100 101 public: 102 /// Constructor 103 Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 104 : PCDependentDisassembly(mnem, _machInst, __opClass), 105 disp(BRDISP) 106 { 107 } 108 109 Addr branchTarget(ThreadContext *tc) const; 110 111 std::string 112 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 113 }; 114}}; 115 116output decoder {{ 117 Addr 118 Branch::branchTarget(Addr branchPC) const 119 { 120 return branchPC + 4 + disp; 121 } 122 123 Addr 124 Jump::branchTarget(ThreadContext *tc) const 125 { 126 Addr NPC = tc->readPC() + 4; 127 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); 128 return (Rb & ~3) | (NPC & 1); 129 } 130 131 const std::string & 132 PCDependentDisassembly::disassemble(Addr pc, 133 const SymbolTable *symtab) const 134 { 135 if (!cachedDisassembly || 136 pc != cachedPC || symtab != cachedSymtab) 137 { 138 if (cachedDisassembly) 139 delete cachedDisassembly; 140 141 cachedDisassembly = 142 new std::string(generateDisassembly(pc, symtab)); 143 cachedPC = pc; 144 cachedSymtab = symtab; 145 } 146 147 return *cachedDisassembly; 148 } 149 150 std::string 151 Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 152 { 153 std::stringstream ss; 154 155 ccprintf(ss, "%-10s ", mnemonic); 156 157 // There's only one register arg (RA), but it could be 158 // either a source (the condition for conditional 159 // branches) or a destination (the link reg for 160 // unconditional branches) 161 if (_numSrcRegs > 0) { 162 printReg(ss, _srcRegIdx[0]); 163 ss << ","; 164 } 165 else if (_numDestRegs > 0) { 166 printReg(ss, _destRegIdx[0]); 167 ss << ","; 168 } 169 170#ifdef SS_COMPATIBLE_DISASSEMBLY 171 if (_numSrcRegs == 0 && _numDestRegs == 0) { 172 printReg(ss, 31); 173 ss << ","; 174 } 175#endif 176 177 Addr target = pc + 4 + disp; 178 179 std::string str; 180 if (symtab && symtab->findSymbol(target, str)) 181 ss << str; 182 else 183 ccprintf(ss, "0x%x", target); 184 185 return ss.str(); 186 } 187 188 std::string 189 Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 190 { 191 std::stringstream ss; 192 193 ccprintf(ss, "%-10s ", mnemonic); 194 195#ifdef SS_COMPATIBLE_DISASSEMBLY 196 if (_numDestRegs == 0) { 197 printReg(ss, 31); 198 ss << ","; 199 } 200#endif 201 202 if (_numDestRegs > 0) { 203 printReg(ss, _destRegIdx[0]); 204 ss << ","; 205 } 206 207 ccprintf(ss, "(r%d)", RB); 208 209 return ss.str(); 210 } 211}}; 212 213def template JumpOrBranchDecode {{ 214 return (RA == 31) 215 ? (StaticInst *)new %(class_name)s(machInst) 216 : (StaticInst *)new %(class_name)sAndLink(machInst); 217}}; 218 219def format CondBranch(code) {{ 220 code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; 221 iop = InstObjParams(name, Name, 'Branch', code, 222 ('IsDirectControl', 'IsCondControl')) 223 header_output = BasicDeclare.subst(iop) 224 decoder_output = BasicConstructor.subst(iop) 225 decode_block = BasicDecode.subst(iop) 226 exec_output = BasicExecute.subst(iop) 227}}; 228 229let {{ 230def UncondCtrlBase(name, Name, base_class, npc_expr, flags): 231 # Declare basic control transfer w/o link (i.e. link reg is R31) 232 nolink_code = 'NPC = %s;\n' % npc_expr 233 nolink_iop = InstObjParams(name, Name, base_class, nolink_code, flags) 234 header_output = BasicDeclare.subst(nolink_iop) 235 decoder_output = BasicConstructor.subst(nolink_iop) 236 exec_output = BasicExecute.subst(nolink_iop) 237 238 # Generate declaration of '*AndLink' version, append to decls 239 link_code = 'Ra = NPC & ~3;\n' + nolink_code 240 link_iop = InstObjParams(name, Name + 'AndLink', base_class, 241 link_code, flags) 242 header_output += BasicDeclare.subst(link_iop) 243 decoder_output += BasicConstructor.subst(link_iop) 244 exec_output += BasicExecute.subst(link_iop) 245 246 # need to use link_iop for the decode template since it is expecting 247 # the shorter version of class_name (w/o "AndLink") 248 249 return (header_output, decoder_output, 250 JumpOrBranchDecode.subst(nolink_iop), exec_output) 251}}; 252 253def format UncondBranch(*flags) {{ 254 flags += ('IsUncondControl', 'IsDirectControl') 255 (header_output, decoder_output, decode_block, exec_output) = \ 256 UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags) 257}}; 258 259def format Jump(*flags) {{ 260 flags += ('IsUncondControl', 'IsIndirectControl') 261 (header_output, decoder_output, decode_block, exec_output) = \ 262 UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags) 263}}; 264 265 266