isa.hh revision 8181:f789b9aac5f4
16145SN/A/* 28257SBrad.Beckmann@amd.com * Copyright (c) 2009 The Regents of The University of Michigan 36145SN/A * All rights reserved. 46145SN/A * 56145SN/A * Redistribution and use in source and binary forms, with or without 66145SN/A * modification, are permitted provided that the following conditions are 76145SN/A * met: redistributions of source code must retain the above copyright 86145SN/A * notice, this list of conditions and the following disclaimer; 96145SN/A * redistributions in binary form must reproduce the above copyright 106145SN/A * notice, this list of conditions and the following disclaimer in the 116145SN/A * documentation and/or other materials provided with the distribution; 126145SN/A * neither the name of the copyright holders nor the names of its 136145SN/A * contributors may be used to endorse or promote products derived from 146145SN/A * this software without specific prior written permission. 156145SN/A * 166145SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145SN/A * 286145SN/A * Authors: Gabe Black 298257SBrad.Beckmann@amd.com */ 308257SBrad.Beckmann@amd.com 316145SN/A#ifndef __ARCH_ALPHA_ISA_HH__ 327055SN/A#define __ARCH_ALPHA_ISA_HH__ 337055SN/A 347454SN/A#include <string.h> 357055SN/A 368257SBrad.Beckmann@amd.com#include <string> 378257SBrad.Beckmann@amd.com#include <iostream> 388257SBrad.Beckmann@amd.com 398257SBrad.Beckmann@amd.com#include "arch/alpha/registers.hh" 408257SBrad.Beckmann@amd.com#include "arch/alpha/types.hh" 418257SBrad.Beckmann@amd.com#include "base/types.hh" 426876SN/A 436145SN/Aclass BaseCPU; 448257SBrad.Beckmann@amd.comclass Checkpoint; 457054SN/Aclass EventManager; 467054SN/Aclass ThreadContext; 478257SBrad.Beckmann@amd.com 488257SBrad.Beckmann@amd.comnamespace AlphaISA 498257SBrad.Beckmann@amd.com{ 506145SN/A class ISA 518257SBrad.Beckmann@amd.com { 526145SN/A public: 538257SBrad.Beckmann@amd.com typedef uint64_t InternalProcReg; 546493SN/A 559499Snilay@cs.wisc.edu protected: 568258SBrad.Beckmann@amd.com uint64_t fpcr; // floating point condition codes 578257SBrad.Beckmann@amd.com uint64_t uniq; // process-unique register 586145SN/A bool lock_flag; // lock flag for LL/SC 596145SN/A Addr lock_addr; // lock address for LL/SC 607055SN/A int intr_flag; 618257SBrad.Beckmann@amd.com 626145SN/A InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 637054SN/A 647055SN/A protected: 657054SN/A InternalProcReg readIpr(int idx, ThreadContext *tc); 666145SN/A void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 676145SN/A 688257SBrad.Beckmann@amd.com public: 698257SBrad.Beckmann@amd.com 708257SBrad.Beckmann@amd.com MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); 718257SBrad.Beckmann@amd.com MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 728257SBrad.Beckmann@amd.com 738257SBrad.Beckmann@amd.com void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 748257SBrad.Beckmann@amd.com ThreadID tid = 0); 758257SBrad.Beckmann@amd.com void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 768257SBrad.Beckmann@amd.com ThreadID tid = 0); 778257SBrad.Beckmann@amd.com 788257SBrad.Beckmann@amd.com void 798257SBrad.Beckmann@amd.com clear() 808257SBrad.Beckmann@amd.com { 818257SBrad.Beckmann@amd.com fpcr = 0; 828257SBrad.Beckmann@amd.com uniq = 0; 838257SBrad.Beckmann@amd.com lock_flag = 0; 848257SBrad.Beckmann@amd.com lock_addr = 0; 858257SBrad.Beckmann@amd.com intr_flag = 0; 868257SBrad.Beckmann@amd.com memset(ipr, 0, sizeof(ipr)); 878257SBrad.Beckmann@amd.com } 888257SBrad.Beckmann@amd.com 898257SBrad.Beckmann@amd.com void serialize(EventManager *em, std::ostream &os); 908257SBrad.Beckmann@amd.com void unserialize(EventManager *em, Checkpoint *cp, 918257SBrad.Beckmann@amd.com const std::string §ion); 928257SBrad.Beckmann@amd.com 938257SBrad.Beckmann@amd.com int 948257SBrad.Beckmann@amd.com flattenIntIndex(int reg) 958257SBrad.Beckmann@amd.com { 968257SBrad.Beckmann@amd.com return reg; 97 } 98 99 int 100 flattenFloatIndex(int reg) 101 { 102 return reg; 103 } 104 105 ISA() 106 { 107 clear(); 108 initializeIprTable(); 109 } 110 }; 111} 112 113#endif 114