isa.hh revision 10698:829adc48e175
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_ALPHA_ISA_HH__ 32#define __ARCH_ALPHA_ISA_HH__ 33 34#include <cstring> 35#include <iostream> 36#include <string> 37 38#include "arch/alpha/registers.hh" 39#include "arch/alpha/types.hh" 40#include "base/types.hh" 41#include "sim/sim_object.hh" 42#include "sim/system.hh" 43 44struct AlphaISAParams; 45class BaseCPU; 46class Checkpoint; 47class EventManager; 48class ThreadContext; 49 50namespace AlphaISA 51{ 52 class ISA : public SimObject 53 { 54 public: 55 typedef uint64_t InternalProcReg; 56 typedef AlphaISAParams Params; 57 58 protected: 59 // Parent system 60 System *system; 61 62 uint64_t fpcr; // floating point condition codes 63 uint64_t uniq; // process-unique register 64 bool lock_flag; // lock flag for LL/SC 65 Addr lock_addr; // lock address for LL/SC 66 int intr_flag; 67 68 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 69 70 protected: 71 InternalProcReg readIpr(int idx, ThreadContext *tc); 72 void setIpr(int idx, InternalProcReg val, ThreadContext *tc); 73 74 public: 75 76 MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 77 MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 78 79 void setMiscRegNoEffect(int misc_reg, const MiscReg &val, 80 ThreadID tid = 0); 81 void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 82 ThreadID tid = 0); 83 84 void 85 clear() 86 { 87 fpcr = 0; 88 uniq = 0; 89 lock_flag = 0; 90 lock_addr = 0; 91 intr_flag = 0; 92 memset(ipr, 0, sizeof(ipr)); 93 } 94 95 void serialize(std::ostream &os); 96 void unserialize(Checkpoint *cp, const std::string §ion); 97 98 int 99 flattenIntIndex(int reg) const 100 { 101 return reg; 102 } 103 104 int 105 flattenFloatIndex(int reg) const 106 { 107 return reg; 108 } 109 110 // dummy 111 int 112 flattenCCIndex(int reg) const 113 { 114 return reg; 115 } 116 117 int 118 flattenMiscIndex(int reg) const 119 { 120 return reg; 121 } 122 123 const Params *params() const; 124 125 ISA(Params *p); 126 127 void startup(ThreadContext *tc) {} 128 129 /// Explicitly import the otherwise hidden startup 130 using SimObject::startup; 131 }; 132} 133 134#endif 135