isa.cc revision 7678
16313Sgblack@eecs.umich.edu/* 26313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 36313Sgblack@eecs.umich.edu * All rights reserved. 46313Sgblack@eecs.umich.edu * 56313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 66313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 76313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 86313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 96313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 106313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 116313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 126313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 136313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146313Sgblack@eecs.umich.edu * this software without specific prior written permission. 156313Sgblack@eecs.umich.edu * 166313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * Authors: Gabe Black 296313Sgblack@eecs.umich.edu */ 306313Sgblack@eecs.umich.edu 317678Sgblack@eecs.umich.edu#include <cassert> 327678Sgblack@eecs.umich.edu 336313Sgblack@eecs.umich.edu#include "arch/alpha/isa.hh" 346330Sgblack@eecs.umich.edu#include "base/misc.hh" 356313Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 366313Sgblack@eecs.umich.edu 376313Sgblack@eecs.umich.edunamespace AlphaISA 386313Sgblack@eecs.umich.edu{ 396313Sgblack@eecs.umich.edu 406313Sgblack@eecs.umich.eduvoid 416678Sgblack@eecs.umich.eduISA::serialize(EventManager *em, std::ostream &os) 426313Sgblack@eecs.umich.edu{ 436330Sgblack@eecs.umich.edu SERIALIZE_SCALAR(fpcr); 446330Sgblack@eecs.umich.edu SERIALIZE_SCALAR(uniq); 456330Sgblack@eecs.umich.edu SERIALIZE_SCALAR(lock_flag); 466330Sgblack@eecs.umich.edu SERIALIZE_SCALAR(lock_addr); 476330Sgblack@eecs.umich.edu SERIALIZE_ARRAY(ipr, NumInternalProcRegs); 486313Sgblack@eecs.umich.edu} 496313Sgblack@eecs.umich.edu 506313Sgblack@eecs.umich.eduvoid 516678Sgblack@eecs.umich.eduISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion) 526313Sgblack@eecs.umich.edu{ 536330Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(fpcr); 546330Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(uniq); 556330Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(lock_flag); 566330Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(lock_addr); 576330Sgblack@eecs.umich.edu UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); 586330Sgblack@eecs.umich.edu} 596330Sgblack@eecs.umich.edu 606330Sgblack@eecs.umich.edu 616330Sgblack@eecs.umich.eduMiscReg 626330Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) 636330Sgblack@eecs.umich.edu{ 646330Sgblack@eecs.umich.edu switch (misc_reg) { 656330Sgblack@eecs.umich.edu case MISCREG_FPCR: 666330Sgblack@eecs.umich.edu return fpcr; 676330Sgblack@eecs.umich.edu case MISCREG_UNIQ: 686330Sgblack@eecs.umich.edu return uniq; 696330Sgblack@eecs.umich.edu case MISCREG_LOCKFLAG: 706330Sgblack@eecs.umich.edu return lock_flag; 716330Sgblack@eecs.umich.edu case MISCREG_LOCKADDR: 726330Sgblack@eecs.umich.edu return lock_addr; 736330Sgblack@eecs.umich.edu case MISCREG_INTR: 746330Sgblack@eecs.umich.edu return intr_flag; 756330Sgblack@eecs.umich.edu default: 766330Sgblack@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 776330Sgblack@eecs.umich.edu return ipr[misc_reg]; 786330Sgblack@eecs.umich.edu } 796330Sgblack@eecs.umich.edu} 806330Sgblack@eecs.umich.edu 816330Sgblack@eecs.umich.eduMiscReg 826330Sgblack@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 836330Sgblack@eecs.umich.edu{ 846330Sgblack@eecs.umich.edu switch (misc_reg) { 856330Sgblack@eecs.umich.edu case MISCREG_FPCR: 866330Sgblack@eecs.umich.edu return fpcr; 876330Sgblack@eecs.umich.edu case MISCREG_UNIQ: 886330Sgblack@eecs.umich.edu return uniq; 896330Sgblack@eecs.umich.edu case MISCREG_LOCKFLAG: 906330Sgblack@eecs.umich.edu return lock_flag; 916330Sgblack@eecs.umich.edu case MISCREG_LOCKADDR: 926330Sgblack@eecs.umich.edu return lock_addr; 936330Sgblack@eecs.umich.edu case MISCREG_INTR: 946330Sgblack@eecs.umich.edu return intr_flag; 956330Sgblack@eecs.umich.edu default: 966330Sgblack@eecs.umich.edu return readIpr(misc_reg, tc); 976330Sgblack@eecs.umich.edu } 986330Sgblack@eecs.umich.edu} 996330Sgblack@eecs.umich.edu 1006330Sgblack@eecs.umich.eduvoid 1016330Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 1026330Sgblack@eecs.umich.edu{ 1036330Sgblack@eecs.umich.edu switch (misc_reg) { 1046330Sgblack@eecs.umich.edu case MISCREG_FPCR: 1056330Sgblack@eecs.umich.edu fpcr = val; 1066330Sgblack@eecs.umich.edu return; 1076330Sgblack@eecs.umich.edu case MISCREG_UNIQ: 1086330Sgblack@eecs.umich.edu uniq = val; 1096330Sgblack@eecs.umich.edu return; 1106330Sgblack@eecs.umich.edu case MISCREG_LOCKFLAG: 1116330Sgblack@eecs.umich.edu lock_flag = val; 1126330Sgblack@eecs.umich.edu return; 1136330Sgblack@eecs.umich.edu case MISCREG_LOCKADDR: 1146330Sgblack@eecs.umich.edu lock_addr = val; 1156330Sgblack@eecs.umich.edu return; 1166330Sgblack@eecs.umich.edu case MISCREG_INTR: 1176330Sgblack@eecs.umich.edu intr_flag = val; 1186330Sgblack@eecs.umich.edu return; 1196330Sgblack@eecs.umich.edu default: 1206330Sgblack@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 1216330Sgblack@eecs.umich.edu ipr[misc_reg] = val; 1226330Sgblack@eecs.umich.edu return; 1236330Sgblack@eecs.umich.edu } 1246330Sgblack@eecs.umich.edu} 1256330Sgblack@eecs.umich.edu 1266330Sgblack@eecs.umich.eduvoid 1276330Sgblack@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 1286330Sgblack@eecs.umich.edu ThreadID tid) 1296330Sgblack@eecs.umich.edu{ 1306330Sgblack@eecs.umich.edu switch (misc_reg) { 1316330Sgblack@eecs.umich.edu case MISCREG_FPCR: 1326330Sgblack@eecs.umich.edu fpcr = val; 1336330Sgblack@eecs.umich.edu return; 1346330Sgblack@eecs.umich.edu case MISCREG_UNIQ: 1356330Sgblack@eecs.umich.edu uniq = val; 1366330Sgblack@eecs.umich.edu return; 1376330Sgblack@eecs.umich.edu case MISCREG_LOCKFLAG: 1386330Sgblack@eecs.umich.edu lock_flag = val; 1396330Sgblack@eecs.umich.edu return; 1406330Sgblack@eecs.umich.edu case MISCREG_LOCKADDR: 1416330Sgblack@eecs.umich.edu lock_addr = val; 1426330Sgblack@eecs.umich.edu return; 1436330Sgblack@eecs.umich.edu case MISCREG_INTR: 1446330Sgblack@eecs.umich.edu intr_flag = val; 1456330Sgblack@eecs.umich.edu return; 1466330Sgblack@eecs.umich.edu default: 1476330Sgblack@eecs.umich.edu setIpr(misc_reg, val, tc); 1486330Sgblack@eecs.umich.edu return; 1496330Sgblack@eecs.umich.edu } 1506313Sgblack@eecs.umich.edu} 1516313Sgblack@eecs.umich.edu 1526313Sgblack@eecs.umich.edu} 153