isa.cc revision 11793
111988Sandreas.sandberg@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 38839Sandreas.hansson@arm.com * All rights reserved. 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68839Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78839Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98839Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118839Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128839Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 133101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 148579Ssteve.reinhardt@amd.com * this software without specific prior written permission. 153101Sstever@eecs.umich.edu * 163101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273101Sstever@eecs.umich.edu * 283101Sstever@eecs.umich.edu * Authors: Gabe Black 293101Sstever@eecs.umich.edu */ 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu#include "arch/alpha/isa.hh" 323101Sstever@eecs.umich.edu 333101Sstever@eecs.umich.edu#include <cassert> 343101Sstever@eecs.umich.edu 353101Sstever@eecs.umich.edu#include "base/misc.hh" 363101Sstever@eecs.umich.edu#include "cpu/thread_context.hh" 373101Sstever@eecs.umich.edu#include "params/AlphaISA.hh" 383101Sstever@eecs.umich.edu#include "sim/serialize.hh" 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.edunamespace AlphaISA 413101Sstever@eecs.umich.edu{ 427778Sgblack@eecs.umich.edu 438839Sandreas.hansson@arm.comISA::ISA(Params *p) 443101Sstever@eecs.umich.edu : SimObject(p), system(p->system) 453101Sstever@eecs.umich.edu{ 463101Sstever@eecs.umich.edu clear(); 473101Sstever@eecs.umich.edu initializeIprTable(); 483101Sstever@eecs.umich.edu} 493101Sstever@eecs.umich.edu 503101Sstever@eecs.umich.educonst AlphaISAParams * 513101Sstever@eecs.umich.eduISA::params() const 523101Sstever@eecs.umich.edu{ 533101Sstever@eecs.umich.edu return dynamic_cast<const Params *>(_params); 543101Sstever@eecs.umich.edu} 553101Sstever@eecs.umich.edu 563101Sstever@eecs.umich.eduvoid 573101Sstever@eecs.umich.eduISA::serialize(CheckpointOut &cp) const 583101Sstever@eecs.umich.edu{ 593101Sstever@eecs.umich.edu SERIALIZE_SCALAR(fpcr); 603101Sstever@eecs.umich.edu SERIALIZE_SCALAR(uniq); 613101Sstever@eecs.umich.edu SERIALIZE_SCALAR(lock_flag); 623885Sbinkertn@umich.edu SERIALIZE_SCALAR(lock_addr); 633885Sbinkertn@umich.edu SERIALIZE_ARRAY(ipr, NumInternalProcRegs); 644762Snate@binkert.org} 653885Sbinkertn@umich.edu 663885Sbinkertn@umich.eduvoid 677528Ssteve.reinhardt@amd.comISA::unserialize(CheckpointIn &cp) 683885Sbinkertn@umich.edu{ 694380Sbinkertn@umich.edu UNSERIALIZE_SCALAR(fpcr); 704167Sbinkertn@umich.edu UNSERIALIZE_SCALAR(uniq); 713102Sstever@eecs.umich.edu UNSERIALIZE_SCALAR(lock_flag); 723101Sstever@eecs.umich.edu UNSERIALIZE_SCALAR(lock_addr); 734762Snate@binkert.org UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); 744762Snate@binkert.org} 754762Snate@binkert.org 764762Snate@binkert.org 774762Snate@binkert.orgMiscReg 784762Snate@binkert.orgISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 794762Snate@binkert.org{ 804762Snate@binkert.org switch (misc_reg) { 814762Snate@binkert.org case MISCREG_FPCR: 825033Smilesck@eecs.umich.edu return fpcr; 835033Smilesck@eecs.umich.edu case MISCREG_UNIQ: 845033Smilesck@eecs.umich.edu return uniq; 855033Smilesck@eecs.umich.edu case MISCREG_LOCKFLAG: 865033Smilesck@eecs.umich.edu return lock_flag; 875033Smilesck@eecs.umich.edu case MISCREG_LOCKADDR: 885033Smilesck@eecs.umich.edu return lock_addr; 895033Smilesck@eecs.umich.edu case MISCREG_INTR: 905033Smilesck@eecs.umich.edu return intr_flag; 915033Smilesck@eecs.umich.edu default: 923101Sstever@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 933101Sstever@eecs.umich.edu return ipr[misc_reg]; 943101Sstever@eecs.umich.edu } 955033Smilesck@eecs.umich.edu} 9610267SGeoffrey.Blake@arm.com 978596Ssteve.reinhardt@amd.comMiscReg 988596Ssteve.reinhardt@amd.comISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 998596Ssteve.reinhardt@amd.com{ 1008596Ssteve.reinhardt@amd.com switch (misc_reg) { 1017673Snate@binkert.org case MISCREG_FPCR: 1027673Snate@binkert.org return fpcr; 1037673Snate@binkert.org case MISCREG_UNIQ: 1047673Snate@binkert.org return uniq; 10511988Sandreas.sandberg@arm.com case MISCREG_LOCKFLAG: 10611988Sandreas.sandberg@arm.com return lock_flag; 10711988Sandreas.sandberg@arm.com case MISCREG_LOCKADDR: 10811988Sandreas.sandberg@arm.com return lock_addr; 1093101Sstever@eecs.umich.edu case MISCREG_INTR: 1103101Sstever@eecs.umich.edu return intr_flag; 1113101Sstever@eecs.umich.edu default: 1123101Sstever@eecs.umich.edu return readIpr(misc_reg, tc); 1133101Sstever@eecs.umich.edu } 11410380SAndrew.Bardsley@arm.com} 11510380SAndrew.Bardsley@arm.com 11610380SAndrew.Bardsley@arm.comvoid 11710380SAndrew.Bardsley@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 11810380SAndrew.Bardsley@arm.com{ 11910380SAndrew.Bardsley@arm.com switch (misc_reg) { 12010458Sandreas.hansson@arm.com case MISCREG_FPCR: 12110458Sandreas.hansson@arm.com fpcr = val; 12210458Sandreas.hansson@arm.com return; 12310458Sandreas.hansson@arm.com case MISCREG_UNIQ: 12410458Sandreas.hansson@arm.com uniq = val; 12510458Sandreas.hansson@arm.com return; 12610458Sandreas.hansson@arm.com case MISCREG_LOCKFLAG: 12710458Sandreas.hansson@arm.com lock_flag = val; 12810458Sandreas.hansson@arm.com return; 12910458Sandreas.hansson@arm.com case MISCREG_LOCKADDR: 13010458Sandreas.hansson@arm.com lock_addr = val; 13110458Sandreas.hansson@arm.com return; 1323101Sstever@eecs.umich.edu case MISCREG_INTR: 1333101Sstever@eecs.umich.edu intr_flag = val; 1343101Sstever@eecs.umich.edu return; 1353101Sstever@eecs.umich.edu default: 1363101Sstever@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 13710267SGeoffrey.Blake@arm.com ipr[misc_reg] = val; 13810267SGeoffrey.Blake@arm.com return; 13910267SGeoffrey.Blake@arm.com } 14010267SGeoffrey.Blake@arm.com} 1413101Sstever@eecs.umich.edu 1423101Sstever@eecs.umich.eduvoid 1433101Sstever@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 1443101Sstever@eecs.umich.edu ThreadID tid) 1453101Sstever@eecs.umich.edu{ 1463101Sstever@eecs.umich.edu switch (misc_reg) { 1473101Sstever@eecs.umich.edu case MISCREG_FPCR: 1483101Sstever@eecs.umich.edu fpcr = val; 1493101Sstever@eecs.umich.edu return; 1503101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1513101Sstever@eecs.umich.edu uniq = val; 1523101Sstever@eecs.umich.edu return; 1533101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 1543101Sstever@eecs.umich.edu lock_flag = val; 1553101Sstever@eecs.umich.edu return; 1563101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 1573101Sstever@eecs.umich.edu lock_addr = val; 1583101Sstever@eecs.umich.edu return; 1593101Sstever@eecs.umich.edu case MISCREG_INTR: 1603101Sstever@eecs.umich.edu intr_flag = val; 1613101Sstever@eecs.umich.edu return; 1623101Sstever@eecs.umich.edu default: 1633101Sstever@eecs.umich.edu setIpr(misc_reg, val, tc); 1643101Sstever@eecs.umich.edu return; 1653101Sstever@eecs.umich.edu } 1663101Sstever@eecs.umich.edu} 1673101Sstever@eecs.umich.edu 1683101Sstever@eecs.umich.edu} 1693101Sstever@eecs.umich.edu 1703101Sstever@eecs.umich.eduAlphaISA::ISA * 1713101Sstever@eecs.umich.eduAlphaISAParams::create() 1723101Sstever@eecs.umich.edu{ 1733101Sstever@eecs.umich.edu return new AlphaISA::ISA(this); 1743101Sstever@eecs.umich.edu} 1753101Sstever@eecs.umich.edu