isa.cc revision 10698
113558Snikos.nikoleris@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 38839Sandreas.hansson@arm.com * All rights reserved. 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68839Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78839Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98839Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108839Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118839Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128839Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 133101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 148579Ssteve.reinhardt@amd.com * this software without specific prior written permission. 153101Sstever@eecs.umich.edu * 163101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273101Sstever@eecs.umich.edu * 283101Sstever@eecs.umich.edu * Authors: Gabe Black 293101Sstever@eecs.umich.edu */ 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu#include <cassert> 323101Sstever@eecs.umich.edu 333101Sstever@eecs.umich.edu#include "arch/alpha/isa.hh" 343101Sstever@eecs.umich.edu#include "base/misc.hh" 353101Sstever@eecs.umich.edu#include "cpu/thread_context.hh" 363101Sstever@eecs.umich.edu#include "params/AlphaISA.hh" 373101Sstever@eecs.umich.edu#include "sim/serialize.hh" 383101Sstever@eecs.umich.edu 393101Sstever@eecs.umich.edunamespace AlphaISA 403101Sstever@eecs.umich.edu{ 413101Sstever@eecs.umich.edu 427778Sgblack@eecs.umich.eduISA::ISA(Params *p) 438839Sandreas.hansson@arm.com : SimObject(p), system(p->system) 443101Sstever@eecs.umich.edu{ 453101Sstever@eecs.umich.edu clear(); 463101Sstever@eecs.umich.edu initializeIprTable(); 473101Sstever@eecs.umich.edu} 483101Sstever@eecs.umich.edu 493101Sstever@eecs.umich.educonst AlphaISAParams * 503101Sstever@eecs.umich.eduISA::params() const 513101Sstever@eecs.umich.edu{ 523101Sstever@eecs.umich.edu return dynamic_cast<const Params *>(_params); 533101Sstever@eecs.umich.edu} 543101Sstever@eecs.umich.edu 553101Sstever@eecs.umich.eduvoid 563101Sstever@eecs.umich.eduISA::serialize(std::ostream &os) 573101Sstever@eecs.umich.edu{ 583101Sstever@eecs.umich.edu SERIALIZE_SCALAR(fpcr); 593101Sstever@eecs.umich.edu SERIALIZE_SCALAR(uniq); 603101Sstever@eecs.umich.edu SERIALIZE_SCALAR(lock_flag); 613101Sstever@eecs.umich.edu SERIALIZE_SCALAR(lock_addr); 6212563Sgabeblack@google.com SERIALIZE_ARRAY(ipr, NumInternalProcRegs); 6313719Sandreas.sandberg@arm.com} 6413719Sandreas.sandberg@arm.com 6513719Sandreas.sandberg@arm.comvoid 6612563Sgabeblack@google.comISA::unserialize(Checkpoint *cp, const std::string §ion) 673885Sbinkertn@umich.edu{ 683885Sbinkertn@umich.edu UNSERIALIZE_SCALAR(fpcr); 694762Snate@binkert.org UNSERIALIZE_SCALAR(uniq); 703885Sbinkertn@umich.edu UNSERIALIZE_SCALAR(lock_flag); 713885Sbinkertn@umich.edu UNSERIALIZE_SCALAR(lock_addr); 727528Ssteve.reinhardt@amd.com UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); 733885Sbinkertn@umich.edu} 7413714Sandreas.sandberg@arm.com 7513714Sandreas.sandberg@arm.com 7613714Sandreas.sandberg@arm.comMiscReg 773101Sstever@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 784762Snate@binkert.org{ 7913716Sandreas.sandberg@arm.com switch (misc_reg) { 804762Snate@binkert.org case MISCREG_FPCR: 814762Snate@binkert.org return fpcr; 824762Snate@binkert.org case MISCREG_UNIQ: 8313716Sandreas.sandberg@arm.com return uniq; 844762Snate@binkert.org case MISCREG_LOCKFLAG: 854762Snate@binkert.org return lock_flag; 864762Snate@binkert.org case MISCREG_LOCKADDR: 8713716Sandreas.sandberg@arm.com return lock_addr; 884762Snate@binkert.org case MISCREG_INTR: 894762Snate@binkert.org return intr_flag; 905033Smilesck@eecs.umich.edu default: 915033Smilesck@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 925033Smilesck@eecs.umich.edu return ipr[misc_reg]; 935033Smilesck@eecs.umich.edu } 945033Smilesck@eecs.umich.edu} 955033Smilesck@eecs.umich.edu 965033Smilesck@eecs.umich.eduMiscReg 975033Smilesck@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 985033Smilesck@eecs.umich.edu{ 995033Smilesck@eecs.umich.edu switch (misc_reg) { 1003101Sstever@eecs.umich.edu case MISCREG_FPCR: 1013101Sstever@eecs.umich.edu return fpcr; 1023101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1035033Smilesck@eecs.umich.edu return uniq; 10410267SGeoffrey.Blake@arm.com case MISCREG_LOCKFLAG: 1058596Ssteve.reinhardt@amd.com return lock_flag; 1068596Ssteve.reinhardt@amd.com case MISCREG_LOCKADDR: 1078596Ssteve.reinhardt@amd.com return lock_addr; 1088596Ssteve.reinhardt@amd.com case MISCREG_INTR: 1097673Snate@binkert.org return intr_flag; 1107673Snate@binkert.org default: 1117673Snate@binkert.org return readIpr(misc_reg, tc); 1127673Snate@binkert.org } 11311988Sandreas.sandberg@arm.com} 11411988Sandreas.sandberg@arm.com 11511988Sandreas.sandberg@arm.comvoid 11611988Sandreas.sandberg@arm.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 1173101Sstever@eecs.umich.edu{ 1183101Sstever@eecs.umich.edu switch (misc_reg) { 1193101Sstever@eecs.umich.edu case MISCREG_FPCR: 1203101Sstever@eecs.umich.edu fpcr = val; 1213101Sstever@eecs.umich.edu return; 12210380SAndrew.Bardsley@arm.com case MISCREG_UNIQ: 12310380SAndrew.Bardsley@arm.com uniq = val; 12410380SAndrew.Bardsley@arm.com return; 12510380SAndrew.Bardsley@arm.com case MISCREG_LOCKFLAG: 12610380SAndrew.Bardsley@arm.com lock_flag = val; 12710380SAndrew.Bardsley@arm.com return; 12810458Sandreas.hansson@arm.com case MISCREG_LOCKADDR: 12910458Sandreas.hansson@arm.com lock_addr = val; 13010458Sandreas.hansson@arm.com return; 13110458Sandreas.hansson@arm.com case MISCREG_INTR: 13210458Sandreas.hansson@arm.com intr_flag = val; 13310458Sandreas.hansson@arm.com return; 13410458Sandreas.hansson@arm.com default: 13510458Sandreas.hansson@arm.com assert(misc_reg < NumInternalProcRegs); 13610458Sandreas.hansson@arm.com ipr[misc_reg] = val; 13710458Sandreas.hansson@arm.com return; 13810458Sandreas.hansson@arm.com } 13910458Sandreas.hansson@arm.com} 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.eduvoid 1423101Sstever@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 1433101Sstever@eecs.umich.edu ThreadID tid) 1443101Sstever@eecs.umich.edu{ 14510267SGeoffrey.Blake@arm.com switch (misc_reg) { 14610267SGeoffrey.Blake@arm.com case MISCREG_FPCR: 14710267SGeoffrey.Blake@arm.com fpcr = val; 14810267SGeoffrey.Blake@arm.com return; 1493101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1503101Sstever@eecs.umich.edu uniq = val; 1513101Sstever@eecs.umich.edu return; 1523101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 1533101Sstever@eecs.umich.edu lock_flag = val; 1543101Sstever@eecs.umich.edu return; 1553101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 1563101Sstever@eecs.umich.edu lock_addr = val; 1573101Sstever@eecs.umich.edu return; 1583101Sstever@eecs.umich.edu case MISCREG_INTR: 1593101Sstever@eecs.umich.edu intr_flag = val; 1603101Sstever@eecs.umich.edu return; 1613101Sstever@eecs.umich.edu default: 1623101Sstever@eecs.umich.edu setIpr(misc_reg, val, tc); 1633101Sstever@eecs.umich.edu return; 16413663Sandreas.sandberg@arm.com } 1653101Sstever@eecs.umich.edu} 16613675Sandreas.sandberg@arm.com 1673101Sstever@eecs.umich.edu} 1683101Sstever@eecs.umich.edu 1693101Sstever@eecs.umich.eduAlphaISA::ISA * 1703101Sstever@eecs.umich.eduAlphaISAParams::create() 17113675Sandreas.sandberg@arm.com{ 1723101Sstever@eecs.umich.edu return new AlphaISA::ISA(this); 1733101Sstever@eecs.umich.edu} 1743101Sstever@eecs.umich.edu