isa.cc revision 10033
13101Sstever@eecs.umich.edu/* 23101Sstever@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 33101Sstever@eecs.umich.edu * All rights reserved. 43101Sstever@eecs.umich.edu * 53101Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 73101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143101Sstever@eecs.umich.edu * this software without specific prior written permission. 153101Sstever@eecs.umich.edu * 163101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273101Sstever@eecs.umich.edu * 283101Sstever@eecs.umich.edu * Authors: Gabe Black 293101Sstever@eecs.umich.edu */ 303101Sstever@eecs.umich.edu 313101Sstever@eecs.umich.edu#include <cassert> 323101Sstever@eecs.umich.edu 333101Sstever@eecs.umich.edu#include "arch/alpha/isa.hh" 343101Sstever@eecs.umich.edu#include "base/misc.hh" 353101Sstever@eecs.umich.edu#include "cpu/thread_context.hh" 363101Sstever@eecs.umich.edu#include "params/AlphaISA.hh" 373101Sstever@eecs.umich.edu#include "sim/serialize.hh" 383101Sstever@eecs.umich.edu 393101Sstever@eecs.umich.edunamespace AlphaISA 403101Sstever@eecs.umich.edu{ 413101Sstever@eecs.umich.edu 423101Sstever@eecs.umich.eduISA::ISA(Params *p) 433101Sstever@eecs.umich.edu : SimObject(p), system(p->system) 443101Sstever@eecs.umich.edu{ 453101Sstever@eecs.umich.edu clear(); 463101Sstever@eecs.umich.edu initializeIprTable(); 473885Sbinkertn@umich.edu} 483885Sbinkertn@umich.edu 494762Snate@binkert.orgconst AlphaISAParams * 503885Sbinkertn@umich.eduISA::params() const 513885Sbinkertn@umich.edu{ 523885Sbinkertn@umich.edu return dynamic_cast<const Params *>(_params); 533101Sstever@eecs.umich.edu} 544380Sbinkertn@umich.edu 554167Sbinkertn@umich.eduvoid 563102Sstever@eecs.umich.eduISA::serialize(std::ostream &os) 573101Sstever@eecs.umich.edu{ 584762Snate@binkert.org SERIALIZE_SCALAR(fpcr); 594762Snate@binkert.org SERIALIZE_SCALAR(uniq); 604762Snate@binkert.org SERIALIZE_SCALAR(lock_flag); 614762Snate@binkert.org SERIALIZE_SCALAR(lock_addr); 624762Snate@binkert.org SERIALIZE_ARRAY(ipr, NumInternalProcRegs); 634762Snate@binkert.org} 644762Snate@binkert.org 654762Snate@binkert.orgvoid 664762Snate@binkert.orgISA::unserialize(Checkpoint *cp, const std::string §ion) 674762Snate@binkert.org{ 684762Snate@binkert.org UNSERIALIZE_SCALAR(fpcr); 695033Smilesck@eecs.umich.edu UNSERIALIZE_SCALAR(uniq); 705033Smilesck@eecs.umich.edu UNSERIALIZE_SCALAR(lock_flag); 715033Smilesck@eecs.umich.edu UNSERIALIZE_SCALAR(lock_addr); 725033Smilesck@eecs.umich.edu UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); 735033Smilesck@eecs.umich.edu} 745033Smilesck@eecs.umich.edu 755033Smilesck@eecs.umich.edu 765033Smilesck@eecs.umich.eduMiscReg 775033Smilesck@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) 785033Smilesck@eecs.umich.edu{ 793101Sstever@eecs.umich.edu switch (misc_reg) { 803101Sstever@eecs.umich.edu case MISCREG_FPCR: 813101Sstever@eecs.umich.edu return fpcr; 825033Smilesck@eecs.umich.edu case MISCREG_UNIQ: 833101Sstever@eecs.umich.edu return uniq; 843101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 853101Sstever@eecs.umich.edu return lock_flag; 863101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 873101Sstever@eecs.umich.edu return lock_addr; 883101Sstever@eecs.umich.edu case MISCREG_INTR: 893101Sstever@eecs.umich.edu return intr_flag; 903101Sstever@eecs.umich.edu default: 913101Sstever@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 923101Sstever@eecs.umich.edu return ipr[misc_reg]; 933101Sstever@eecs.umich.edu } 943101Sstever@eecs.umich.edu} 953101Sstever@eecs.umich.edu 963101Sstever@eecs.umich.eduMiscReg 973101Sstever@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 983101Sstever@eecs.umich.edu{ 993101Sstever@eecs.umich.edu switch (misc_reg) { 1003101Sstever@eecs.umich.edu case MISCREG_FPCR: 1013101Sstever@eecs.umich.edu return fpcr; 1023101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1033101Sstever@eecs.umich.edu return uniq; 1043101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 1053101Sstever@eecs.umich.edu return lock_flag; 1063101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 1073101Sstever@eecs.umich.edu return lock_addr; 1083101Sstever@eecs.umich.edu case MISCREG_INTR: 1093101Sstever@eecs.umich.edu return intr_flag; 1103101Sstever@eecs.umich.edu default: 1113101Sstever@eecs.umich.edu return readIpr(misc_reg, tc); 1123101Sstever@eecs.umich.edu } 1133101Sstever@eecs.umich.edu} 1143101Sstever@eecs.umich.edu 1153101Sstever@eecs.umich.eduvoid 1163101Sstever@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) 1173101Sstever@eecs.umich.edu{ 1183101Sstever@eecs.umich.edu switch (misc_reg) { 1193101Sstever@eecs.umich.edu case MISCREG_FPCR: 1203101Sstever@eecs.umich.edu fpcr = val; 1213101Sstever@eecs.umich.edu return; 1223101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1233101Sstever@eecs.umich.edu uniq = val; 1243101Sstever@eecs.umich.edu return; 1253101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 1263101Sstever@eecs.umich.edu lock_flag = val; 1273101Sstever@eecs.umich.edu return; 1283101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 1293101Sstever@eecs.umich.edu lock_addr = val; 1303101Sstever@eecs.umich.edu return; 1313101Sstever@eecs.umich.edu case MISCREG_INTR: 1325033Smilesck@eecs.umich.edu intr_flag = val; 1335033Smilesck@eecs.umich.edu return; 1345033Smilesck@eecs.umich.edu default: 1355033Smilesck@eecs.umich.edu assert(misc_reg < NumInternalProcRegs); 1365033Smilesck@eecs.umich.edu ipr[misc_reg] = val; 1373101Sstever@eecs.umich.edu return; 1383101Sstever@eecs.umich.edu } 1393101Sstever@eecs.umich.edu} 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.eduvoid 1423101Sstever@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, 1433101Sstever@eecs.umich.edu ThreadID tid) 1443101Sstever@eecs.umich.edu{ 1453101Sstever@eecs.umich.edu switch (misc_reg) { 1463101Sstever@eecs.umich.edu case MISCREG_FPCR: 1473101Sstever@eecs.umich.edu fpcr = val; 1483101Sstever@eecs.umich.edu return; 1493101Sstever@eecs.umich.edu case MISCREG_UNIQ: 1503102Sstever@eecs.umich.edu uniq = val; 1513101Sstever@eecs.umich.edu return; 1523101Sstever@eecs.umich.edu case MISCREG_LOCKFLAG: 1533101Sstever@eecs.umich.edu lock_flag = val; 1543101Sstever@eecs.umich.edu return; 1553101Sstever@eecs.umich.edu case MISCREG_LOCKADDR: 1563101Sstever@eecs.umich.edu lock_addr = val; 1573101Sstever@eecs.umich.edu return; 1583101Sstever@eecs.umich.edu case MISCREG_INTR: 1593101Sstever@eecs.umich.edu intr_flag = val; 1603101Sstever@eecs.umich.edu return; 1613101Sstever@eecs.umich.edu default: 1623101Sstever@eecs.umich.edu setIpr(misc_reg, val, tc); 1633101Sstever@eecs.umich.edu return; 1643101Sstever@eecs.umich.edu } 1653101Sstever@eecs.umich.edu} 1663101Sstever@eecs.umich.edu 1673101Sstever@eecs.umich.edu} 1685033Smilesck@eecs.umich.edu 1693101Sstever@eecs.umich.eduAlphaISA::ISA * 1703101Sstever@eecs.umich.eduAlphaISAParams::create() 1713101Sstever@eecs.umich.edu{ 1724762Snate@binkert.org return new AlphaISA::ISA(this); 1734762Snate@binkert.org} 1744762Snate@binkert.org