ipr.cc revision 3459:dd091092c8bb
19518SAndreas.Sandberg@ARM.com/* 29518SAndreas.Sandberg@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 39518SAndreas.Sandberg@ARM.com * All rights reserved. 49518SAndreas.Sandberg@ARM.com * 59518SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69518SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79518SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89518SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99518SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109518SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119518SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129518SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 135347Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147534Ssteve.reinhardt@amd.com * this software without specific prior written permission. 153395Shsul@eecs.umich.edu * 163395Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu * 283395Shsul@eecs.umich.edu * Authors: Gabe Black 293395Shsul@eecs.umich.edu */ 303395Shsul@eecs.umich.edu 313395Shsul@eecs.umich.edu#include <assert.h> 323395Shsul@eecs.umich.edu#include <string.h> 333395Shsul@eecs.umich.edu 343395Shsul@eecs.umich.edu#include "arch/alpha/ipr.hh" 353395Shsul@eecs.umich.edu 363395Shsul@eecs.umich.edunamespace AlphaISA 373395Shsul@eecs.umich.edu{ 383395Shsul@eecs.umich.edu md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = 393395Shsul@eecs.umich.edu { 403395Shsul@eecs.umich.edu //Write only 413395Shsul@eecs.umich.edu RAW_IPR_HWINT_CLR, // H/W interrupt clear register 429457Svilanova@ac.upc.edu RAW_IPR_SL_XMIT, // serial line transmit register 433395Shsul@eecs.umich.edu RAW_IPR_DC_FLUSH, 443509Shsul@eecs.umich.edu RAW_IPR_IC_FLUSH, // instruction cache flush control 456654Snate@binkert.org RAW_IPR_ALT_MODE, // alternate mode register 469520SAndreas.Sandberg@ARM.com RAW_IPR_DTB_IA, // DTLB invalidate all register 479520SAndreas.Sandberg@ARM.com RAW_IPR_DTB_IAP, // DTLB invalidate all process register 483395Shsul@eecs.umich.edu RAW_IPR_ITB_IA, // ITLB invalidate all register 496654Snate@binkert.org RAW_IPR_ITB_IAP, // ITLB invalidate all process register 503395Shsul@eecs.umich.edu 516654Snate@binkert.org //Read only 526654Snate@binkert.org RAW_IPR_INTID, // interrupt ID register 536654Snate@binkert.org RAW_IPR_SL_RCV, // serial line receive register 543395Shsul@eecs.umich.edu RAW_IPR_MM_STAT, // data MMU fault status register 559139Snilay@cs.wisc.edu RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register 569520SAndreas.Sandberg@ARM.com RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register 579520SAndreas.Sandberg@ARM.com 589520SAndreas.Sandberg@ARM.com RAW_IPR_ISR, // interrupt summary register 599139Snilay@cs.wisc.edu RAW_IPR_ITB_TAG, // ITLB tag register 603481Shsul@eecs.umich.edu RAW_IPR_ITB_PTE, // ITLB page table entry register 619139Snilay@cs.wisc.edu RAW_IPR_ITB_ASN, // ITLB address space register 623481Shsul@eecs.umich.edu RAW_IPR_ITB_IS, // ITLB invalidate select register 639139Snilay@cs.wisc.edu RAW_IPR_SIRR, // software interrupt request register 649139Snilay@cs.wisc.edu RAW_IPR_ASTRR, // asynchronous system trap request register 659139Snilay@cs.wisc.edu RAW_IPR_ASTER, // asynchronous system trap enable register 669139Snilay@cs.wisc.edu RAW_IPR_EXC_ADDR, // exception address register 679139Snilay@cs.wisc.edu RAW_IPR_EXC_SUM, // exception summary register 689139Snilay@cs.wisc.edu RAW_IPR_EXC_MASK, // exception mask register 699139Snilay@cs.wisc.edu RAW_IPR_PAL_BASE, // PAL base address register 709139Snilay@cs.wisc.edu RAW_IPR_ICM, // instruction current mode 713481Shsul@eecs.umich.edu RAW_IPR_IPLR, // interrupt priority level register 729518SAndreas.Sandberg@ARM.com RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register 739518SAndreas.Sandberg@ARM.com RAW_IPR_IVPTBR, // virtual page table base register 749518SAndreas.Sandberg@ARM.com RAW_IPR_ICSR, // instruction control and status register 753481Shsul@eecs.umich.edu RAW_IPR_IC_PERR_STAT, // inst cache parity error status register 769139Snilay@cs.wisc.edu RAW_IPR_PMCTR, // performance counter register 779139Snilay@cs.wisc.edu 783481Shsul@eecs.umich.edu // PAL temporary registers... 799139Snilay@cs.wisc.edu // register meanings gleaned from osfpal.s source code 809139Snilay@cs.wisc.edu RAW_IPR_PALtemp0, // local scratch 819139Snilay@cs.wisc.edu RAW_IPR_PALtemp1, // local scratch 829139Snilay@cs.wisc.edu RAW_IPR_PALtemp2, // entUna 839139Snilay@cs.wisc.edu RAW_IPR_PALtemp3, // CPU specific impure area pointer 843481Shsul@eecs.umich.edu RAW_IPR_PALtemp4, // memory management temp 853481Shsul@eecs.umich.edu RAW_IPR_PALtemp5, // memory management temp 863481Shsul@eecs.umich.edu RAW_IPR_PALtemp6, // memory management temp 878919Snilay@cs.wisc.edu RAW_IPR_PALtemp7, // entIF 888919Snilay@cs.wisc.edu RAW_IPR_PALtemp8, // intmask 898919Snilay@cs.wisc.edu RAW_IPR_PALtemp9, // entSys 908919Snilay@cs.wisc.edu RAW_IPR_PALtemp10, // ?? 918919Snilay@cs.wisc.edu RAW_IPR_PALtemp11, // entInt 928919Snilay@cs.wisc.edu RAW_IPR_PALtemp12, // entArith 938919Snilay@cs.wisc.edu RAW_IPR_PALtemp13, // reserved for platform specific PAL 948919Snilay@cs.wisc.edu RAW_IPR_PALtemp14, // reserved for platform specific PAL 958919Snilay@cs.wisc.edu RAW_IPR_PALtemp15, // reserved for platform specific PAL 968919Snilay@cs.wisc.edu RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> 978919Snilay@cs.wisc.edu RAW_IPR_PALtemp17, // sysval 988919Snilay@cs.wisc.edu RAW_IPR_PALtemp18, // usp 998919Snilay@cs.wisc.edu RAW_IPR_PALtemp19, // ksp 1008919Snilay@cs.wisc.edu RAW_IPR_PALtemp20, // PTBR 1018919Snilay@cs.wisc.edu RAW_IPR_PALtemp21, // entMM 1023481Shsul@eecs.umich.edu RAW_IPR_PALtemp22, // kgp 1039140Snilay@cs.wisc.edu RAW_IPR_PALtemp23, // PCBB 1049140Snilay@cs.wisc.edu 1059140Snilay@cs.wisc.edu RAW_IPR_DTB_ASN, // DTLB address space number register 1069140Snilay@cs.wisc.edu RAW_IPR_DTB_CM, // DTLB current mode register 1079140Snilay@cs.wisc.edu RAW_IPR_DTB_TAG, // DTLB tag register 1089140Snilay@cs.wisc.edu RAW_IPR_DTB_PTE, // DTLB page table entry register 1099140Snilay@cs.wisc.edu 1109140Snilay@cs.wisc.edu RAW_IPR_VA, // fault virtual address register 1119140Snilay@cs.wisc.edu RAW_IPR_VA_FORM, // formatted virtual address register 1129140Snilay@cs.wisc.edu RAW_IPR_MVPTBR, // MTU virtual page table base register 1139140Snilay@cs.wisc.edu RAW_IPR_DTB_IS, // DTLB invalidate single register 1149140Snilay@cs.wisc.edu RAW_IPR_CC, // cycle counter register 1159140Snilay@cs.wisc.edu RAW_IPR_CC_CTL, // cycle counter control register 1169140Snilay@cs.wisc.edu RAW_IPR_MCSR, // MTU control register 1179140Snilay@cs.wisc.edu 1189140Snilay@cs.wisc.edu RAW_IPR_DC_PERR_STAT, // Dcache parity error status register 1199140Snilay@cs.wisc.edu RAW_IPR_DC_TEST_CTL, // Dcache test tag control register 1209140Snilay@cs.wisc.edu RAW_IPR_DC_TEST_TAG, // Dcache test tag register 1219140Snilay@cs.wisc.edu RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register 1229140Snilay@cs.wisc.edu RAW_IPR_DC_MODE, // Dcache mode register 1239140Snilay@cs.wisc.edu RAW_IPR_MAF_MODE // miss address file mode register 1249140Snilay@cs.wisc.edu }; 1259140Snilay@cs.wisc.edu 1269140Snilay@cs.wisc.edu int IprToMiscRegIndex[MaxInternalProcRegs]; 1279140Snilay@cs.wisc.edu 1289140Snilay@cs.wisc.edu void initializeIprTable() 1299140Snilay@cs.wisc.edu { 1309140Snilay@cs.wisc.edu static bool initialized = false; 1319140Snilay@cs.wisc.edu if(initialized) 1329140Snilay@cs.wisc.edu return; 1339140Snilay@cs.wisc.edu 1349140Snilay@cs.wisc.edu memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); 1359140Snilay@cs.wisc.edu 1369140Snilay@cs.wisc.edu for(int x = 0; x < NumInternalProcRegs; x++) 1379140Snilay@cs.wisc.edu IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; 1389140Snilay@cs.wisc.edu } 1399140Snilay@cs.wisc.edu} 1409140Snilay@cs.wisc.edu 1419140Snilay@cs.wisc.edu