interrupts.hh revision 9550 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "base/compiler.hh"
38#include "base/trace.hh"
39#include "cpu/thread_context.hh"
40#include "debug/Flow.hh"
41#include "debug/Interrupt.hh"
42#include "params/AlphaInterrupts.hh"
43#include "sim/sim_object.hh"
44
45namespace AlphaISA {
46
47class Interrupts : public SimObject
48{
49  private:
50    bool newInfoSet;
51    int newIpl;
52    int newSummary;
53    BaseCPU * cpu;
54
55  protected:
56    uint64_t interrupts[NumInterruptLevels];
57    uint64_t intstatus;
58
59  public:
60    typedef AlphaInterruptsParams Params;
61
62    const Params *
63    params() const
64    {
65        return dynamic_cast<const Params *>(_params);
66    }
67
68    Interrupts(Params * p) : SimObject(p), cpu(NULL)
69    {
70        memset(interrupts, 0, sizeof(interrupts));
71        intstatus = 0;
72        newInfoSet = false;
73    }
74
75    void
76    setCPU(BaseCPU * _cpu)
77    {
78        cpu = _cpu;
79    }
80
81    void
82    post(int int_num, int index)
83    {
84        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
85
86        if (int_num < 0 || int_num >= NumInterruptLevels)
87            panic("int_num out of bounds\n");
88
89        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
90            panic("int_num out of bounds\n");
91
92        interrupts[int_num] |= 1 << index;
93        intstatus |= (ULL(1) << int_num);
94    }
95
96    void
97    clear(int int_num, int index)
98    {
99        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
100
101        if (int_num < 0 || int_num >= NumInterruptLevels)
102            panic("int_num out of bounds\n");
103
104        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
105            panic("int_num out of bounds\n");
106
107        interrupts[int_num] &= ~(1 << index);
108        if (interrupts[int_num] == 0)
109            intstatus &= ~(ULL(1) << int_num);
110    }
111
112    void
113    clearAll()
114    {
115        DPRINTF(Interrupt, "Interrupts all cleared\n");
116
117        memset(interrupts, 0, sizeof(interrupts));
118        intstatus = 0;
119    }
120
121    void
122    serialize(std::ostream &os)
123    {
124        SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
125        SERIALIZE_SCALAR(intstatus);
126    }
127
128    void
129    unserialize(Checkpoint *cp, const std::string &section)
130    {
131        UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
132        UNSERIALIZE_SCALAR(intstatus);
133    }
134
135    bool
136    checkInterrupts(ThreadContext *tc) const
137    {
138        return (intstatus != 0) && !(tc->pcState().pc() & 0x3);
139    }
140
141    Fault
142    getInterrupt(ThreadContext *tc)
143    {
144        uint64_t ipl = 0;
145        uint64_t summary = 0;
146
147        if (tc->readMiscRegNoEffect(IPR_ASTRR))
148            panic("asynchronous traps not implemented\n");
149
150        if (tc->readMiscRegNoEffect(IPR_SIRR)) {
151            for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
152                 i < INTLEVEL_SOFTWARE_MAX; i++) {
153                if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
154                    // See table 4-19 of 21164 hardware reference
155                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
156                    summary |= (ULL(1) << i);
157                }
158            }
159        }
160
161        if (intstatus) {
162            for (uint64_t i = INTLEVEL_EXTERNAL_MIN;
163                 i < INTLEVEL_EXTERNAL_MAX; i++) {
164                if (intstatus & (ULL(1) << i)) {
165                    // See table 4-19 of 21164 hardware reference
166                    ipl = i;
167                    summary |= (ULL(1) << i);
168                }
169            }
170        }
171
172        if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
173            newIpl = ipl;
174            newSummary = summary;
175            newInfoSet = true;
176            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
177                    tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
178
179            return new InterruptFault;
180        } else {
181            return NoFault;
182        }
183    }
184
185    void
186    updateIntrInfo(ThreadContext *tc)
187    {
188        assert(newInfoSet);
189        tc->setMiscRegNoEffect(IPR_ISR, newSummary);
190        tc->setMiscRegNoEffect(IPR_INTID, newIpl);
191        newInfoSet = false;
192    }
193};
194
195} // namespace AlphaISA
196
197#endif // __ARCH_ALPHA_INTERRUPT_HH__
198
199