interrupts.hh revision 4009
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Kevin Lim 30 */ 31 32#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 33#define __ARCH_ALPHA_INTERRUPT_HH__ 34 35#include "arch/alpha/faults.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "cpu/thread_context.hh" 38 39namespace AlphaISA 40{ 41 class Interrupts 42 { 43 protected: 44 uint64_t interrupts[NumInterruptLevels]; 45 uint64_t intstatus; 46 47 public: 48 Interrupts() 49 { 50 memset(interrupts, 0, sizeof(interrupts)); 51 intstatus = 0; 52 newInfoSet = false; 53 } 54 55 void post(int int_type) 56 { 57 // sparc only 58 } 59 60 void post(int int_num, int index) 61 { 62 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 63 64 if (int_num < 0 || int_num >= NumInterruptLevels) 65 panic("int_num out of bounds\n"); 66 67 if (index < 0 || index >= sizeof(uint64_t) * 8) 68 panic("int_num out of bounds\n"); 69 70 interrupts[int_num] |= 1 << index; 71 intstatus |= (ULL(1) << int_num); 72 } 73 74 void clear(int int_num, int index) 75 { 76 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 77 78 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 79 panic("int_num out of bounds\n"); 80 81 if (index < 0 || index >= sizeof(uint64_t) * 8) 82 panic("int_num out of bounds\n"); 83 84 interrupts[int_num] &= ~(1 << index); 85 if (interrupts[int_num] == 0) 86 intstatus &= ~(ULL(1) << int_num); 87 } 88 89 void clear_all() 90 { 91 DPRINTF(Interrupt, "Interrupts all cleared\n"); 92 93 memset(interrupts, 0, sizeof(interrupts)); 94 intstatus = 0; 95 } 96 97 void serialize(std::ostream &os) 98 { 99 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 100 SERIALIZE_SCALAR(intstatus); 101 } 102 103 void unserialize(Checkpoint *cp, const std::string §ion) 104 { 105 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 106 UNSERIALIZE_SCALAR(intstatus); 107 } 108 109 bool check_interrupts(ThreadContext * tc) const 110 { 111 return (intstatus != 0) && !(tc->readPC() & 0x3); 112 } 113 114 Fault getInterrupt(ThreadContext * tc) 115 { 116 int ipl = 0; 117 int summary = 0; 118 119 if (tc->readMiscReg(IPR_ASTRR)) 120 panic("asynchronous traps not implemented\n"); 121 122 if (tc->readMiscReg(IPR_SIRR)) { 123 for (int i = INTLEVEL_SOFTWARE_MIN; 124 i < INTLEVEL_SOFTWARE_MAX; i++) { 125 if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 126 // See table 4-19 of 21164 hardware reference 127 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 128 summary |= (ULL(1) << i); 129 } 130 } 131 } 132 133 uint64_t interrupts = intstatus; 134 if (interrupts) { 135 for (int i = INTLEVEL_EXTERNAL_MIN; 136 i < INTLEVEL_EXTERNAL_MAX; i++) { 137 if (interrupts & (ULL(1) << i)) { 138 // See table 4-19 of 21164 hardware reference 139 ipl = i; 140 summary |= (ULL(1) << i); 141 } 142 } 143 } 144 145 if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { 146 newIpl = ipl; 147 newSummary = summary; 148 newInfoSet = true; 149 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 150 tc->readMiscReg(IPR_IPLR), ipl, summary); 151 152 return new InterruptFault; 153 } else { 154 return NoFault; 155 } 156 } 157 158 void updateIntrInfo(ThreadContext *tc) 159 { 160 assert(newInfoSet); 161 tc->setMiscReg(IPR_ISR, newSummary); 162 tc->setMiscReg(IPR_INTID, newIpl); 163 newInfoSet = false; 164 } 165 166 private: 167 bool newInfoSet; 168 int newIpl; 169 int newSummary; 170 }; 171} 172 173#endif 174 175