interrupts.hh revision 3894 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "cpu/thread_context.hh"
38
39namespace AlphaISA
40{
41    class Interrupts
42    {
43      protected:
44        uint64_t interrupts[NumInterruptLevels];
45        uint64_t intstatus;
46
47      public:
48        Interrupts()
49        {
50            memset(interrupts, 0, sizeof(interrupts));
51            intstatus = 0;
52            newInfoSet = false;
53        }
54
55        void post(int int_num, int index)
56        {
57            DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
58
59            if (int_num < 0 || int_num >= NumInterruptLevels)
60                panic("int_num out of bounds\n");
61
62            if (index < 0 || index >= sizeof(uint64_t) * 8)
63                panic("int_num out of bounds\n");
64
65            interrupts[int_num] |= 1 << index;
66            intstatus |= (ULL(1) << int_num);
67        }
68
69        void clear(int int_num, int index)
70        {
71            DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
72
73            if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
74                panic("int_num out of bounds\n");
75
76            if (index < 0 || index >= sizeof(uint64_t) * 8)
77                panic("int_num out of bounds\n");
78
79            interrupts[int_num] &= ~(1 << index);
80            if (interrupts[int_num] == 0)
81                intstatus &= ~(ULL(1) << int_num);
82        }
83
84        void clear_all()
85        {
86            DPRINTF(Interrupt, "Interrupts all cleared\n");
87
88            memset(interrupts, 0, sizeof(interrupts));
89            intstatus = 0;
90        }
91
92        void serialize(std::ostream &os)
93        {
94            SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
95            SERIALIZE_SCALAR(intstatus);
96        }
97
98        void unserialize(Checkpoint *cp, const std::string &section)
99        {
100            UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
101            UNSERIALIZE_SCALAR(intstatus);
102        }
103
104        bool check_interrupts(ThreadContext * tc) const
105        {
106            return (intstatus != 0) && !(tc->readPC() & 0x3);
107        }
108
109        Fault getInterrupt(ThreadContext * tc)
110        {
111            int ipl = 0;
112            int summary = 0;
113
114            if (tc->readMiscReg(IPR_ASTRR))
115                panic("asynchronous traps not implemented\n");
116
117            if (tc->readMiscReg(IPR_SIRR)) {
118                for (int i = INTLEVEL_SOFTWARE_MIN;
119                     i < INTLEVEL_SOFTWARE_MAX; i++) {
120                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
121                        // See table 4-19 of 21164 hardware reference
122                        ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
123                        summary |= (ULL(1) << i);
124                    }
125                }
126            }
127
128            uint64_t interrupts = intstatus;
129            if (interrupts) {
130                for (int i = INTLEVEL_EXTERNAL_MIN;
131                    i < INTLEVEL_EXTERNAL_MAX; i++) {
132                    if (interrupts & (ULL(1) << i)) {
133                        // See table 4-19 of 21164 hardware reference
134                        ipl = i;
135                        summary |= (ULL(1) << i);
136                    }
137                }
138            }
139
140            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
141                newIpl = ipl;
142                newSummary = summary;
143                newInfoSet = true;
144                DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
145                        tc->readMiscReg(IPR_IPLR), ipl, summary);
146
147                return new InterruptFault;
148            } else {
149                return NoFault;
150            }
151        }
152
153        void updateIntrInfo(ThreadContext *tc)
154        {
155            assert(newInfoSet);
156            tc->setMiscReg(IPR_ISR, newSummary);
157            tc->setMiscReg(IPR_INTID, newIpl);
158            newInfoSet = false;
159        }
160
161      private:
162        bool newInfoSet;
163        int newIpl;
164        int newSummary;
165    };
166}
167
168#endif
169
170