interrupts.hh revision 3520
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Kevin Lim 30 */ 31 32#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 33#define __ARCH_ALPHA_INTERRUPT_HH__ 34 35#include "arch/alpha/faults.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "cpu/thread_context.hh" 38 39namespace AlphaISA 40{ 41 class Interrupts 42 { 43 protected: 44 uint64_t interrupts[NumInterruptLevels]; 45 uint64_t intstatus; 46 47 public: 48 Interrupts() 49 { 50 memset(interrupts, 0, sizeof(interrupts)); 51 intstatus = 0; 52 } 53 54 void post(int int_num, int index) 55 { 56 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 57 58 if (int_num < 0 || int_num >= NumInterruptLevels) 59 panic("int_num out of bounds\n"); 60 61 if (index < 0 || index >= sizeof(uint64_t) * 8) 62 panic("int_num out of bounds\n"); 63 64 interrupts[int_num] |= 1 << index; 65 intstatus |= (ULL(1) << int_num); 66 } 67 68 void clear(int int_num, int index) 69 { 70 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 71 72 if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) 73 panic("int_num out of bounds\n"); 74 75 if (index < 0 || index >= sizeof(uint64_t) * 8) 76 panic("int_num out of bounds\n"); 77 78 interrupts[int_num] &= ~(1 << index); 79 if (interrupts[int_num] == 0) 80 intstatus &= ~(ULL(1) << int_num); 81 } 82 83 void clear_all() 84 { 85 DPRINTF(Interrupt, "Interrupts all cleared\n"); 86 87 memset(interrupts, 0, sizeof(interrupts)); 88 intstatus = 0; 89 } 90 91 bool check_interrupt(int int_num) const { 92 if (int_num > NumInterruptLevels) 93 panic("int_num out of bounds\n"); 94 95 return interrupts[int_num] != 0; 96 } 97 98 bool check_interrupts() const { return intstatus != 0; } 99 100 void serialize(std::ostream &os) 101 { 102 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 103 SERIALIZE_SCALAR(intstatus); 104 } 105 106 void unserialize(Checkpoint *cp, const std::string §ion) 107 { 108 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 109 UNSERIALIZE_SCALAR(intstatus); 110 } 111 112 Fault getInterrupt(ThreadContext * tc) 113 { 114 int ipl = 0; 115 int summary = 0; 116 117 if (tc->readMiscReg(IPR_ASTRR)) 118 panic("asynchronous traps not implemented\n"); 119 120 if (tc->readMiscReg(IPR_SIRR)) { 121 for (int i = INTLEVEL_SOFTWARE_MIN; 122 i < INTLEVEL_SOFTWARE_MAX; i++) { 123 if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 124 // See table 4-19 of 21164 hardware reference 125 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 126 summary |= (ULL(1) << i); 127 } 128 } 129 } 130 131 uint64_t interrupts = intstatus; 132 if (interrupts) { 133 for (int i = INTLEVEL_EXTERNAL_MIN; 134 i < INTLEVEL_EXTERNAL_MAX; i++) { 135 if (interrupts & (ULL(1) << i)) { 136 // See table 4-19 of 21164 hardware reference 137 ipl = i; 138 summary |= (ULL(1) << i); 139 } 140 } 141 } 142 143 if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) { 144 tc->setMiscReg(IPR_ISR, summary); 145 tc->setMiscReg(IPR_INTID, ipl); 146 147 /* The following needs to be added back in somehow */ 148 // Checker needs to know these two registers were updated. 149/*#if USE_CHECKER 150 if (this->checker) { 151 this->checker->threadBase()->setMiscReg(IPR_ISR, summary); 152 this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); 153 } 154#endif*/ 155 156 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 157 tc->readMiscReg(IPR_IPLR), ipl, summary); 158 159 return new InterruptFault; 160 } else { 161 return NoFault; 162 } 163 } 164 165 private: 166 uint64_t intr_status() const { return intstatus; } 167 }; 168} 169 170#endif 171 172