interrupts.hh revision 11566 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include <memory>
36
37#include "arch/alpha/faults.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "base/compiler.hh"
40#include "base/trace.hh"
41#include "cpu/thread_context.hh"
42#include "debug/Flow.hh"
43#include "debug/Interrupt.hh"
44#include "params/AlphaInterrupts.hh"
45#include "sim/sim_object.hh"
46
47namespace AlphaISA {
48
49class Interrupts : public SimObject
50{
51  private:
52    bool newInfoSet;
53    int newIpl;
54    int newSummary;
55    BaseCPU * cpu;
56
57  protected:
58    uint64_t interrupts[NumInterruptLevels];
59    uint64_t intstatus;
60
61  public:
62    typedef AlphaInterruptsParams Params;
63
64    const Params *
65    params() const
66    {
67        return dynamic_cast<const Params *>(_params);
68    }
69
70    Interrupts(Params * p) : SimObject(p), cpu(NULL)
71    {
72        memset(interrupts, 0, sizeof(interrupts));
73        intstatus = 0;
74        newInfoSet = false;
75    }
76
77    void
78    setCPU(BaseCPU * _cpu)
79    {
80        cpu = _cpu;
81    }
82
83    void
84    post(int int_num, int index)
85    {
86        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
87
88        if (int_num < 0 || int_num >= NumInterruptLevels)
89            panic("int_num out of bounds\n");
90
91        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
92            panic("int_num out of bounds\n");
93
94        interrupts[int_num] |= 1 << index;
95        intstatus |= (ULL(1) << int_num);
96    }
97
98    void
99    clear(int int_num, int index)
100    {
101        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
102
103        if (int_num < 0 || int_num >= NumInterruptLevels)
104            panic("int_num out of bounds\n");
105
106        if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
107            panic("int_num out of bounds\n");
108
109        interrupts[int_num] &= ~(1 << index);
110        if (interrupts[int_num] == 0)
111            intstatus &= ~(ULL(1) << int_num);
112    }
113
114    void
115    clearAll()
116    {
117        DPRINTF(Interrupt, "Interrupts all cleared\n");
118
119        memset(interrupts, 0, sizeof(interrupts));
120        intstatus = 0;
121    }
122
123    void
124    serialize(CheckpointOut &cp) const
125    {
126        SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
127        SERIALIZE_SCALAR(intstatus);
128    }
129
130    void
131    unserialize(CheckpointIn &cp)
132    {
133        UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
134        UNSERIALIZE_SCALAR(intstatus);
135    }
136
137    bool
138    checkInterrupts(ThreadContext *tc) const
139    {
140        if (intstatus == 0)
141            return false;
142
143        if (tc->pcState().pc() & 0x3)
144            return false;
145
146        if (tc->readMiscRegNoEffect(IPR_ASTRR))
147            panic("asynchronous traps not implemented\n");
148
149        uint64_t ipl = 0;
150        uint64_t summary = 0;
151
152        if (tc->readMiscRegNoEffect(IPR_SIRR)) {
153            for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
154                 i < INTLEVEL_SOFTWARE_MAX; i++) {
155                if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
156                    // See table 4-19 of 21164 hardware reference
157                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
158                    summary |= (ULL(1) << i);
159                }
160            }
161        }
162
163        for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
164             i++) {
165            if (intstatus & (ULL(1) << i)) {
166                // See table 4-19 of 21164 hardware reference
167                ipl = i;
168                summary |= (ULL(1) << i);
169            }
170        }
171
172        return ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR);
173    }
174
175    Fault
176    getInterrupt(ThreadContext *tc)
177    {
178        assert(checkInterrupts(tc));
179
180        uint64_t ipl = 0;
181        uint64_t summary = 0;
182        if (tc->readMiscRegNoEffect(IPR_SIRR)) {
183            for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
184                 i < INTLEVEL_SOFTWARE_MAX; i++) {
185                if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
186                    // See table 4-19 of 21164 hardware reference
187                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
188                    summary |= (ULL(1) << i);
189                }
190            }
191        }
192
193        for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
194             i++) {
195            if (intstatus & (ULL(1) << i)) {
196                // See table 4-19 of 21164 hardware reference
197                ipl = i;
198                summary |= (ULL(1) << i);
199            }
200        }
201
202        newIpl = ipl;
203        newSummary = summary;
204        newInfoSet = true;
205        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
206                tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
207
208        return std::make_shared<InterruptFault>();
209    }
210
211    void
212    updateIntrInfo(ThreadContext *tc)
213    {
214        assert(newInfoSet);
215        tc->setMiscRegNoEffect(IPR_ISR, newSummary);
216        tc->setMiscRegNoEffect(IPR_INTID, newIpl);
217        newInfoSet = false;
218    }
219};
220
221} // namespace AlphaISA
222
223#endif // __ARCH_ALPHA_INTERRUPT_HH__
224
225