interrupts.hh revision 5704
13520Sgblack@eecs.umich.edu/* 23520Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33520Sgblack@eecs.umich.edu * All rights reserved. 43520Sgblack@eecs.umich.edu * 53520Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63520Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73520Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83520Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93520Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103520Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113520Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123520Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133520Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143520Sgblack@eecs.umich.edu * this software without specific prior written permission. 153520Sgblack@eecs.umich.edu * 163520Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173520Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183520Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193520Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203520Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213520Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223520Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233520Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243520Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253520Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263520Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273520Sgblack@eecs.umich.edu * 283520Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 293520Sgblack@eecs.umich.edu * Kevin Lim 303520Sgblack@eecs.umich.edu */ 313520Sgblack@eecs.umich.edu 323520Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 333520Sgblack@eecs.umich.edu#define __ARCH_ALPHA_INTERRUPT_HH__ 343520Sgblack@eecs.umich.edu 353520Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 363520Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 374103Ssaidi@eecs.umich.edu#include "base/compiler.hh" 385647Sgblack@eecs.umich.edu#include "base/trace.hh" 393520Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 405647Sgblack@eecs.umich.edu#include "params/AlphaInterrupts.hh" 415647Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 423520Sgblack@eecs.umich.edu 435565Snate@binkert.orgnamespace AlphaISA { 445565Snate@binkert.org 455647Sgblack@eecs.umich.educlass Interrupts : public SimObject 463520Sgblack@eecs.umich.edu{ 475565Snate@binkert.org private: 485565Snate@binkert.org bool newInfoSet; 495565Snate@binkert.org int newIpl; 505565Snate@binkert.org int newSummary; 515565Snate@binkert.org 525565Snate@binkert.org protected: 535565Snate@binkert.org uint64_t interrupts[NumInterruptLevels]; 545565Snate@binkert.org uint64_t intstatus; 555565Snate@binkert.org 565565Snate@binkert.org public: 575647Sgblack@eecs.umich.edu typedef AlphaInterruptsParams Params; 585647Sgblack@eecs.umich.edu 595647Sgblack@eecs.umich.edu const Params * 605647Sgblack@eecs.umich.edu params() const 615647Sgblack@eecs.umich.edu { 625647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 635647Sgblack@eecs.umich.edu } 645647Sgblack@eecs.umich.edu 655647Sgblack@eecs.umich.edu Interrupts(Params * p) : SimObject(p) 663520Sgblack@eecs.umich.edu { 675565Snate@binkert.org memset(interrupts, 0, sizeof(interrupts)); 685565Snate@binkert.org intstatus = 0; 695565Snate@binkert.org newInfoSet = false; 705565Snate@binkert.org } 713520Sgblack@eecs.umich.edu 725565Snate@binkert.org void 735565Snate@binkert.org post(int int_num, int index) 745565Snate@binkert.org { 755565Snate@binkert.org DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 763520Sgblack@eecs.umich.edu 775565Snate@binkert.org if (int_num < 0 || int_num >= NumInterruptLevels) 785565Snate@binkert.org panic("int_num out of bounds\n"); 793520Sgblack@eecs.umich.edu 805565Snate@binkert.org if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 815565Snate@binkert.org panic("int_num out of bounds\n"); 823520Sgblack@eecs.umich.edu 835565Snate@binkert.org interrupts[int_num] |= 1 << index; 845565Snate@binkert.org intstatus |= (ULL(1) << int_num); 855565Snate@binkert.org } 863520Sgblack@eecs.umich.edu 875565Snate@binkert.org void 885565Snate@binkert.org clear(int int_num, int index) 895565Snate@binkert.org { 905565Snate@binkert.org DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 913520Sgblack@eecs.umich.edu 925568Snate@binkert.org if (int_num < 0 || int_num >= NumInterruptLevels) 935565Snate@binkert.org panic("int_num out of bounds\n"); 943520Sgblack@eecs.umich.edu 955565Snate@binkert.org if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 965565Snate@binkert.org panic("int_num out of bounds\n"); 973520Sgblack@eecs.umich.edu 985565Snate@binkert.org interrupts[int_num] &= ~(1 << index); 995565Snate@binkert.org if (interrupts[int_num] == 0) 1005565Snate@binkert.org intstatus &= ~(ULL(1) << int_num); 1015565Snate@binkert.org } 1023520Sgblack@eecs.umich.edu 1035565Snate@binkert.org void 1045704Snate@binkert.org clearAll() 1055565Snate@binkert.org { 1065565Snate@binkert.org DPRINTF(Interrupt, "Interrupts all cleared\n"); 1073520Sgblack@eecs.umich.edu 1085565Snate@binkert.org memset(interrupts, 0, sizeof(interrupts)); 1095565Snate@binkert.org intstatus = 0; 1105565Snate@binkert.org } 1113520Sgblack@eecs.umich.edu 1125565Snate@binkert.org void 1135565Snate@binkert.org serialize(std::ostream &os) 1145565Snate@binkert.org { 1155565Snate@binkert.org SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1165565Snate@binkert.org SERIALIZE_SCALAR(intstatus); 1175565Snate@binkert.org } 1183520Sgblack@eecs.umich.edu 1195565Snate@binkert.org void 1205565Snate@binkert.org unserialize(Checkpoint *cp, const std::string §ion) 1215565Snate@binkert.org { 1225565Snate@binkert.org UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1235565Snate@binkert.org UNSERIALIZE_SCALAR(intstatus); 1245565Snate@binkert.org } 1253520Sgblack@eecs.umich.edu 1265565Snate@binkert.org bool 1275704Snate@binkert.org checkInterrupts(ThreadContext *tc) const 1285565Snate@binkert.org { 1295565Snate@binkert.org return (intstatus != 0) && !(tc->readPC() & 0x3); 1305565Snate@binkert.org } 1313520Sgblack@eecs.umich.edu 1325565Snate@binkert.org Fault 1335565Snate@binkert.org getInterrupt(ThreadContext *tc) 1345565Snate@binkert.org { 1355565Snate@binkert.org int ipl = 0; 1365565Snate@binkert.org int summary = 0; 1373521Sgblack@eecs.umich.edu 1385565Snate@binkert.org if (tc->readMiscRegNoEffect(IPR_ASTRR)) 1395565Snate@binkert.org panic("asynchronous traps not implemented\n"); 1403520Sgblack@eecs.umich.edu 1415565Snate@binkert.org if (tc->readMiscRegNoEffect(IPR_SIRR)) { 1425565Snate@binkert.org for (int i = INTLEVEL_SOFTWARE_MIN; 1435565Snate@binkert.org i < INTLEVEL_SOFTWARE_MAX; i++) { 1445565Snate@binkert.org if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 1455565Snate@binkert.org // See table 4-19 of 21164 hardware reference 1465565Snate@binkert.org ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 1475565Snate@binkert.org summary |= (ULL(1) << i); 1483520Sgblack@eecs.umich.edu } 1493520Sgblack@eecs.umich.edu } 1503520Sgblack@eecs.umich.edu } 1513520Sgblack@eecs.umich.edu 1525565Snate@binkert.org uint64_t interrupts = intstatus; 1535565Snate@binkert.org if (interrupts) { 1545565Snate@binkert.org for (int i = INTLEVEL_EXTERNAL_MIN; 1555565Snate@binkert.org i < INTLEVEL_EXTERNAL_MAX; i++) { 1565565Snate@binkert.org if (interrupts & (ULL(1) << i)) { 1575565Snate@binkert.org // See table 4-19 of 21164 hardware reference 1585565Snate@binkert.org ipl = i; 1595565Snate@binkert.org summary |= (ULL(1) << i); 1605565Snate@binkert.org } 1615565Snate@binkert.org } 1623633Sktlim@umich.edu } 1633633Sktlim@umich.edu 1645565Snate@binkert.org if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { 1655565Snate@binkert.org newIpl = ipl; 1665565Snate@binkert.org newSummary = summary; 1675565Snate@binkert.org newInfoSet = true; 1685565Snate@binkert.org DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 1695565Snate@binkert.org tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); 1705565Snate@binkert.org 1715565Snate@binkert.org return new InterruptFault; 1725565Snate@binkert.org } else { 1735565Snate@binkert.org return NoFault; 1744103Ssaidi@eecs.umich.edu } 1755565Snate@binkert.org } 1764103Ssaidi@eecs.umich.edu 1775565Snate@binkert.org void 1785565Snate@binkert.org updateIntrInfo(ThreadContext *tc) 1795565Snate@binkert.org { 1805565Snate@binkert.org assert(newInfoSet); 1815565Snate@binkert.org tc->setMiscRegNoEffect(IPR_ISR, newSummary); 1825565Snate@binkert.org tc->setMiscRegNoEffect(IPR_INTID, newIpl); 1835565Snate@binkert.org newInfoSet = false; 1845565Snate@binkert.org } 1855565Snate@binkert.org}; 1863520Sgblack@eecs.umich.edu 1875565Snate@binkert.org} // namespace AlphaISA 1885565Snate@binkert.org 1895565Snate@binkert.org#endif // __ARCH_ALPHA_INTERRUPT_HH__ 1905565Snate@binkert.org 191