interrupts.hh revision 5568
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Kevin Lim 30 */ 31 32#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 33#define __ARCH_ALPHA_INTERRUPT_HH__ 34 35#include "arch/alpha/faults.hh" 36#include "arch/alpha/isa_traits.hh" 37#include "base/compiler.hh" 38#include "cpu/thread_context.hh" 39 40namespace AlphaISA { 41 42class Interrupts 43{ 44 private: 45 bool newInfoSet; 46 int newIpl; 47 int newSummary; 48 49 protected: 50 uint64_t interrupts[NumInterruptLevels]; 51 uint64_t intstatus; 52 53 public: 54 Interrupts() 55 { 56 memset(interrupts, 0, sizeof(interrupts)); 57 intstatus = 0; 58 newInfoSet = false; 59 } 60 61 void 62 post(int int_num, int index) 63 { 64 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 65 66 if (int_num < 0 || int_num >= NumInterruptLevels) 67 panic("int_num out of bounds\n"); 68 69 if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 70 panic("int_num out of bounds\n"); 71 72 interrupts[int_num] |= 1 << index; 73 intstatus |= (ULL(1) << int_num); 74 } 75 76 void 77 clear(int int_num, int index) 78 { 79 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 80 81 if (int_num < 0 || int_num >= NumInterruptLevels) 82 panic("int_num out of bounds\n"); 83 84 if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 85 panic("int_num out of bounds\n"); 86 87 interrupts[int_num] &= ~(1 << index); 88 if (interrupts[int_num] == 0) 89 intstatus &= ~(ULL(1) << int_num); 90 } 91 92 void 93 clear_all() 94 { 95 DPRINTF(Interrupt, "Interrupts all cleared\n"); 96 97 memset(interrupts, 0, sizeof(interrupts)); 98 intstatus = 0; 99 } 100 101 void 102 serialize(std::ostream &os) 103 { 104 SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 105 SERIALIZE_SCALAR(intstatus); 106 } 107 108 void 109 unserialize(Checkpoint *cp, const std::string §ion) 110 { 111 UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 112 UNSERIALIZE_SCALAR(intstatus); 113 } 114 115 bool 116 check_interrupts(ThreadContext *tc) const 117 { 118 return (intstatus != 0) && !(tc->readPC() & 0x3); 119 } 120 121 Fault 122 getInterrupt(ThreadContext *tc) 123 { 124 int ipl = 0; 125 int summary = 0; 126 127 if (tc->readMiscRegNoEffect(IPR_ASTRR)) 128 panic("asynchronous traps not implemented\n"); 129 130 if (tc->readMiscRegNoEffect(IPR_SIRR)) { 131 for (int i = INTLEVEL_SOFTWARE_MIN; 132 i < INTLEVEL_SOFTWARE_MAX; i++) { 133 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 134 // See table 4-19 of 21164 hardware reference 135 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 136 summary |= (ULL(1) << i); 137 } 138 } 139 } 140 141 uint64_t interrupts = intstatus; 142 if (interrupts) { 143 for (int i = INTLEVEL_EXTERNAL_MIN; 144 i < INTLEVEL_EXTERNAL_MAX; i++) { 145 if (interrupts & (ULL(1) << i)) { 146 // See table 4-19 of 21164 hardware reference 147 ipl = i; 148 summary |= (ULL(1) << i); 149 } 150 } 151 } 152 153 if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { 154 newIpl = ipl; 155 newSummary = summary; 156 newInfoSet = true; 157 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 158 tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); 159 160 return new InterruptFault; 161 } else { 162 return NoFault; 163 } 164 } 165 166 void 167 updateIntrInfo(ThreadContext *tc) 168 { 169 assert(newInfoSet); 170 tc->setMiscRegNoEffect(IPR_ISR, newSummary); 171 tc->setMiscRegNoEffect(IPR_INTID, newIpl); 172 newInfoSet = false; 173 } 174 175 uint64_t 176 get_vec(int int_num) 177 { 178 panic("Shouldn't be called for Alpha\n"); 179 M5_DUMMY_RETURN; 180 } 181}; 182 183} // namespace AlphaISA 184 185#endif // __ARCH_ALPHA_INTERRUPT_HH__ 186 187