faults.cc revision 10664 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "base/trace.hh"
36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38#include "mem/page_table.hh"
39#include "sim/process.hh"
40#include "sim/full_system.hh"
41
42namespace AlphaISA {
43
44FaultName MachineCheckFault::_name = "mchk";
45FaultVect MachineCheckFault::_vect = 0x0401;
46FaultStat MachineCheckFault::_count;
47
48FaultName AlignmentFault::_name = "unalign";
49FaultVect AlignmentFault::_vect = 0x0301;
50FaultStat AlignmentFault::_count;
51
52FaultName ResetFault::_name = "reset";
53FaultVect ResetFault::_vect = 0x0001;
54FaultStat ResetFault::_count;
55
56FaultName ArithmeticFault::_name = "arith";
57FaultVect ArithmeticFault::_vect = 0x0501;
58FaultStat ArithmeticFault::_count;
59
60FaultName InterruptFault::_name = "interrupt";
61FaultVect InterruptFault::_vect = 0x0101;
62FaultStat InterruptFault::_count;
63
64FaultName NDtbMissFault::_name = "dtb_miss_single";
65FaultVect NDtbMissFault::_vect = 0x0201;
66FaultStat NDtbMissFault::_count;
67
68FaultName PDtbMissFault::_name = "dtb_miss_double";
69FaultVect PDtbMissFault::_vect = 0x0281;
70FaultStat PDtbMissFault::_count;
71
72FaultName DtbPageFault::_name = "dtb_page_fault";
73FaultVect DtbPageFault::_vect = 0x0381;
74FaultStat DtbPageFault::_count;
75
76FaultName DtbAcvFault::_name = "dtb_acv_fault";
77FaultVect DtbAcvFault::_vect = 0x0381;
78FaultStat DtbAcvFault::_count;
79
80FaultName DtbAlignmentFault::_name = "unalign";
81FaultVect DtbAlignmentFault::_vect = 0x0301;
82FaultStat DtbAlignmentFault::_count;
83
84FaultName ItbPageFault::_name = "itbmiss";
85FaultVect ItbPageFault::_vect = 0x0181;
86FaultStat ItbPageFault::_count;
87
88FaultName ItbAcvFault::_name = "iaccvio";
89FaultVect ItbAcvFault::_vect = 0x0081;
90FaultStat ItbAcvFault::_count;
91
92FaultName UnimplementedOpcodeFault::_name = "opdec";
93FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
94FaultStat UnimplementedOpcodeFault::_count;
95
96FaultName FloatEnableFault::_name = "fen";
97FaultVect FloatEnableFault::_vect = 0x0581;
98FaultStat FloatEnableFault::_count;
99
100FaultName PalFault::_name = "pal";
101FaultVect PalFault::_vect = 0x2001;
102FaultStat PalFault::_count;
103
104FaultName IntegerOverflowFault::_name = "intover";
105FaultVect IntegerOverflowFault::_vect = 0x0501;
106FaultStat IntegerOverflowFault::_count;
107
108void
109AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
110{
111    FaultBase::invoke(tc);
112    if (!FullSystem)
113        return;
114    countStat()++;
115
116    PCState pc = tc->pcState();
117
118    // exception restart address
119    if (setRestartAddress() || !(pc.pc() & 0x3))
120        tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
121
122    if (skipFaultingInstruction()) {
123        // traps...  skip faulting instruction.
124        tc->setMiscRegNoEffect(IPR_EXC_ADDR,
125                   tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126    }
127
128    pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129    tc->pcState(pc);
130}
131
132void
133ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
134{
135    FaultBase::invoke(tc);
136    if (!FullSystem)
137        return;
138    panic("Arithmetic traps are unimplemented!");
139}
140
141void
142DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
143{
144    if (FullSystem) {
145        // Set fault address and flags.  Even though we're modeling an
146        // EV5, we use the EV6 technique of not latching fault registers
147        // on VPTE loads (instead of locking the registers until IPR_VA is
148        // read, like the EV5).  The EV6 approach is cleaner and seems to
149        // work with EV5 PAL code, but not the other way around.
150        if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
151            // set VA register with faulting address
152            tc->setMiscRegNoEffect(IPR_VA, vaddr);
153
154            // set MM_STAT register flags
155            MachInst machInst = inst->machInst;
156            tc->setMiscRegNoEffect(IPR_MM_STAT,
157                (((Opcode(machInst) & 0x3f) << 11) |
158                 ((Ra(machInst) & 0x1f) << 6) |
159                 (flags & 0x3f)));
160
161            // set VA_FORM register with faulting formatted address
162            tc->setMiscRegNoEffect(IPR_VA_FORM,
163                tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
164        }
165    }
166
167    AlphaFault::invoke(tc);
168}
169
170void
171ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
172{
173    if (FullSystem) {
174        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
175        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
176            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
177    }
178
179    AlphaFault::invoke(tc);
180}
181
182void
183ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
184{
185    if (FullSystem) {
186        ItbFault::invoke(tc);
187        return;
188    }
189
190    Process *p = tc->getProcessPtr();
191    TlbEntry entry;
192    bool success = p->pTable->lookup(pc, entry);
193    if (!success) {
194        panic("Tried to execute unmapped address %#x.\n", pc);
195    } else {
196        VAddr vaddr(pc);
197        tc->getITBPtr()->insert(vaddr.page(), entry);
198    }
199}
200
201void
202NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
203{
204    if (FullSystem) {
205        DtbFault::invoke(tc, inst);
206        return;
207    }
208
209    Process *p = tc->getProcessPtr();
210    TlbEntry entry;
211    bool success = p->pTable->lookup(vaddr, entry);
212    if (!success) {
213        if (p->fixupStackFault(vaddr))
214            success = p->pTable->lookup(vaddr, entry);
215    }
216    if (!success) {
217        panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
218    } else {
219        tc->getDTBPtr()->insert(vaddr.page(), entry);
220    }
221}
222
223} // namespace AlphaISA
224
225