faults.cc revision 10664
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302SN/A */ 312SN/A 324997Sgblack@eecs.umich.edu#include "arch/alpha/ev5.hh" 331110SN/A#include "arch/alpha/faults.hh" 344997Sgblack@eecs.umich.edu#include "arch/alpha/tlb.hh" 358229Snate@binkert.org#include "base/trace.hh" 368229Snate@binkert.org#include "cpu/base.hh" 372680Sktlim@umich.edu#include "cpu/thread_context.hh" 388229Snate@binkert.org#include "mem/page_table.hh" 392800Ssaidi@eecs.umich.edu#include "sim/process.hh" 408780Sgblack@eecs.umich.edu#include "sim/full_system.hh" 412SN/A 425569Snate@binkert.orgnamespace AlphaISA { 432167SN/A 442203SN/AFaultName MachineCheckFault::_name = "mchk"; 452203SN/AFaultVect MachineCheckFault::_vect = 0x0401; 462222SN/AFaultStat MachineCheckFault::_count; 472166SN/A 482203SN/AFaultName AlignmentFault::_name = "unalign"; 492203SN/AFaultVect AlignmentFault::_vect = 0x0301; 502222SN/AFaultStat AlignmentFault::_count; 512166SN/A 522147SN/AFaultName ResetFault::_name = "reset"; 532147SN/AFaultVect ResetFault::_vect = 0x0001; 542222SN/AFaultStat ResetFault::_count; 552147SN/A 562147SN/AFaultName ArithmeticFault::_name = "arith"; 572147SN/AFaultVect ArithmeticFault::_vect = 0x0501; 582222SN/AFaultStat ArithmeticFault::_count; 592147SN/A 602147SN/AFaultName InterruptFault::_name = "interrupt"; 612147SN/AFaultVect InterruptFault::_vect = 0x0101; 622222SN/AFaultStat InterruptFault::_count; 632147SN/A 642147SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 652147SN/AFaultVect NDtbMissFault::_vect = 0x0201; 662222SN/AFaultStat NDtbMissFault::_count; 672147SN/A 682147SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 692147SN/AFaultVect PDtbMissFault::_vect = 0x0281; 702222SN/AFaultStat PDtbMissFault::_count; 712147SN/A 728405Sksewell@umich.eduFaultName DtbPageFault::_name = "dtb_page_fault"; 732147SN/AFaultVect DtbPageFault::_vect = 0x0381; 742222SN/AFaultStat DtbPageFault::_count; 752147SN/A 768405Sksewell@umich.eduFaultName DtbAcvFault::_name = "dtb_acv_fault"; 772147SN/AFaultVect DtbAcvFault::_vect = 0x0381; 782222SN/AFaultStat DtbAcvFault::_count; 792147SN/A 802289SN/AFaultName DtbAlignmentFault::_name = "unalign"; 812289SN/AFaultVect DtbAlignmentFault::_vect = 0x0301; 822289SN/AFaultStat DtbAlignmentFault::_count; 832289SN/A 842147SN/AFaultName ItbPageFault::_name = "itbmiss"; 852147SN/AFaultVect ItbPageFault::_vect = 0x0181; 862222SN/AFaultStat ItbPageFault::_count; 872147SN/A 882147SN/AFaultName ItbAcvFault::_name = "iaccvio"; 892147SN/AFaultVect ItbAcvFault::_vect = 0x0081; 902222SN/AFaultStat ItbAcvFault::_count; 912147SN/A 922147SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 932147SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 942222SN/AFaultStat UnimplementedOpcodeFault::_count; 952147SN/A 962147SN/AFaultName FloatEnableFault::_name = "fen"; 972147SN/AFaultVect FloatEnableFault::_vect = 0x0581; 982222SN/AFaultStat FloatEnableFault::_count; 992147SN/A 1002147SN/AFaultName PalFault::_name = "pal"; 1012147SN/AFaultVect PalFault::_vect = 0x2001; 1022222SN/AFaultStat PalFault::_count; 1032147SN/A 1042147SN/AFaultName IntegerOverflowFault::_name = "intover"; 1052147SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1062222SN/AFaultStat IntegerOverflowFault::_count; 1072147SN/A 1085569Snate@binkert.orgvoid 10910417Sandreas.hansson@arm.comAlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1102174SN/A{ 1112680Sktlim@umich.edu FaultBase::invoke(tc); 1128780Sgblack@eecs.umich.edu if (!FullSystem) 1138780Sgblack@eecs.umich.edu return; 1142222SN/A countStat()++; 1152174SN/A 1167720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1177720Sgblack@eecs.umich.edu 1182196SN/A // exception restart address 1197720Sgblack@eecs.umich.edu if (setRestartAddress() || !(pc.pc() & 0x3)) 1207720Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc()); 1212196SN/A 1222201SN/A if (skipFaultingInstruction()) { 1232196SN/A // traps... skip faulting instruction. 1245568Snate@binkert.org tc->setMiscRegNoEffect(IPR_EXC_ADDR, 1255568Snate@binkert.org tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4); 1262196SN/A } 1272196SN/A 1287720Sgblack@eecs.umich.edu pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect()); 1297720Sgblack@eecs.umich.edu tc->pcState(pc); 1302174SN/A} 1312174SN/A 1325569Snate@binkert.orgvoid 13310417Sandreas.hansson@arm.comArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1342201SN/A{ 1352680Sktlim@umich.edu FaultBase::invoke(tc); 1368780Sgblack@eecs.umich.edu if (!FullSystem) 1378780Sgblack@eecs.umich.edu return; 1382201SN/A panic("Arithmetic traps are unimplemented!"); 1392201SN/A} 1402201SN/A 1415569Snate@binkert.orgvoid 14210417Sandreas.hansson@arm.comDtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1432289SN/A{ 1448780Sgblack@eecs.umich.edu if (FullSystem) { 1458780Sgblack@eecs.umich.edu // Set fault address and flags. Even though we're modeling an 1468780Sgblack@eecs.umich.edu // EV5, we use the EV6 technique of not latching fault registers 1478780Sgblack@eecs.umich.edu // on VPTE loads (instead of locking the registers until IPR_VA is 1488780Sgblack@eecs.umich.edu // read, like the EV5). The EV6 approach is cleaner and seems to 1498780Sgblack@eecs.umich.edu // work with EV5 PAL code, but not the other way around. 15010664SAli.Saidi@ARM.com if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) { 1518780Sgblack@eecs.umich.edu // set VA register with faulting address 1528780Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_VA, vaddr); 1532289SN/A 1548780Sgblack@eecs.umich.edu // set MM_STAT register flags 1558780Sgblack@eecs.umich.edu MachInst machInst = inst->machInst; 1568780Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MM_STAT, 1578780Sgblack@eecs.umich.edu (((Opcode(machInst) & 0x3f) << 11) | 1588780Sgblack@eecs.umich.edu ((Ra(machInst) & 0x1f) << 6) | 1598780Sgblack@eecs.umich.edu (flags & 0x3f))); 1602289SN/A 1618780Sgblack@eecs.umich.edu // set VA_FORM register with faulting formatted address 1628780Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_VA_FORM, 1638780Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3)); 1648780Sgblack@eecs.umich.edu } 1652289SN/A } 1662289SN/A 1672680Sktlim@umich.edu AlphaFault::invoke(tc); 1682289SN/A} 1692289SN/A 1705569Snate@binkert.orgvoid 17110417Sandreas.hansson@arm.comItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1722289SN/A{ 1738780Sgblack@eecs.umich.edu if (FullSystem) { 17410664SAli.Saidi@ARM.com tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); 17510664SAli.Saidi@ARM.com tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, 17610664SAli.Saidi@ARM.com tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3)); 1772289SN/A } 1782289SN/A 1792680Sktlim@umich.edu AlphaFault::invoke(tc); 1802289SN/A} 1812289SN/A 1825569Snate@binkert.orgvoid 18310417Sandreas.hansson@arm.comItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1844997Sgblack@eecs.umich.edu{ 1858780Sgblack@eecs.umich.edu if (FullSystem) { 1868780Sgblack@eecs.umich.edu ItbFault::invoke(tc); 1878806Sgblack@eecs.umich.edu return; 1888806Sgblack@eecs.umich.edu } 1898806Sgblack@eecs.umich.edu 1908806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 1918806Sgblack@eecs.umich.edu TlbEntry entry; 1928806Sgblack@eecs.umich.edu bool success = p->pTable->lookup(pc, entry); 1938806Sgblack@eecs.umich.edu if (!success) { 1948806Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", pc); 1954997Sgblack@eecs.umich.edu } else { 1968806Sgblack@eecs.umich.edu VAddr vaddr(pc); 1978806Sgblack@eecs.umich.edu tc->getITBPtr()->insert(vaddr.page(), entry); 1984997Sgblack@eecs.umich.edu } 1994997Sgblack@eecs.umich.edu} 2004997Sgblack@eecs.umich.edu 2015569Snate@binkert.orgvoid 20210417Sandreas.hansson@arm.comNDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 2034997Sgblack@eecs.umich.edu{ 2048780Sgblack@eecs.umich.edu if (FullSystem) { 2058780Sgblack@eecs.umich.edu DtbFault::invoke(tc, inst); 2068806Sgblack@eecs.umich.edu return; 2078806Sgblack@eecs.umich.edu } 2088806Sgblack@eecs.umich.edu 2098806Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 2108806Sgblack@eecs.umich.edu TlbEntry entry; 2118806Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 2128806Sgblack@eecs.umich.edu if (!success) { 2138806Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) 2148806Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, entry); 2158806Sgblack@eecs.umich.edu } 2168806Sgblack@eecs.umich.edu if (!success) { 2178806Sgblack@eecs.umich.edu panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); 2184997Sgblack@eecs.umich.edu } else { 2198806Sgblack@eecs.umich.edu tc->getDTBPtr()->insert(vaddr.page(), entry); 2204997Sgblack@eecs.umich.edu } 2214997Sgblack@eecs.umich.edu} 2224997Sgblack@eecs.umich.edu 2232167SN/A} // namespace AlphaISA 2242167SN/A 225