ev5.cc revision 8780:89e0822462a1 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "base/cp_annotate.hh"
38#include "base/debug.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "sim/sim_exit.hh"
44
45namespace AlphaISA {
46
47////////////////////////////////////////////////////////////////////////
48//
49//  Machine dependent functions
50//
51void
52initCPU(ThreadContext *tc, int cpuId)
53{
54    initIPRs(tc, cpuId);
55
56    tc->setIntReg(16, cpuId);
57    tc->setIntReg(0, cpuId);
58
59    AlphaFault *reset = new ResetFault;
60
61    tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
62
63    delete reset;
64}
65
66template <class CPU>
67void
68zeroRegisters(CPU *cpu)
69{
70    // Insure ISA semantics
71    // (no longer very clean due to the change in setIntReg() in the
72    // cpu model.  Consider changing later.)
73    cpu->thread->setIntReg(ZeroReg, 0);
74    cpu->thread->setFloatReg(ZeroReg, 0.0);
75}
76
77////////////////////////////////////////////////////////////////////////
78//
79//
80//
81void
82initIPRs(ThreadContext *tc, int cpuId)
83{
84    for (int i = 0; i < NumInternalProcRegs; ++i) {
85        tc->setMiscRegNoEffect(i, 0);
86    }
87
88    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
89    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
90    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
91}
92
93MiscReg
94ISA::readIpr(int idx, ThreadContext *tc)
95{
96    uint64_t retval = 0;        // return value, default 0
97
98    switch (idx) {
99      case IPR_PALtemp0:
100      case IPR_PALtemp1:
101      case IPR_PALtemp2:
102      case IPR_PALtemp3:
103      case IPR_PALtemp4:
104      case IPR_PALtemp5:
105      case IPR_PALtemp6:
106      case IPR_PALtemp7:
107      case IPR_PALtemp8:
108      case IPR_PALtemp9:
109      case IPR_PALtemp10:
110      case IPR_PALtemp11:
111      case IPR_PALtemp12:
112      case IPR_PALtemp13:
113      case IPR_PALtemp14:
114      case IPR_PALtemp15:
115      case IPR_PALtemp16:
116      case IPR_PALtemp17:
117      case IPR_PALtemp18:
118      case IPR_PALtemp19:
119      case IPR_PALtemp20:
120      case IPR_PALtemp21:
121      case IPR_PALtemp22:
122      case IPR_PALtemp23:
123      case IPR_PAL_BASE:
124
125      case IPR_IVPTBR:
126      case IPR_DC_MODE:
127      case IPR_MAF_MODE:
128      case IPR_ISR:
129      case IPR_EXC_ADDR:
130      case IPR_IC_PERR_STAT:
131      case IPR_DC_PERR_STAT:
132      case IPR_MCSR:
133      case IPR_ASTRR:
134      case IPR_ASTER:
135      case IPR_SIRR:
136      case IPR_ICSR:
137      case IPR_ICM:
138      case IPR_DTB_CM:
139      case IPR_IPLR:
140      case IPR_INTID:
141      case IPR_PMCTR:
142        // no side-effect
143        retval = ipr[idx];
144        break;
145
146      case IPR_CC:
147        retval |= ipr[idx] & ULL(0xffffffff00000000);
148        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
149        break;
150
151      case IPR_VA:
152        retval = ipr[idx];
153        break;
154
155      case IPR_VA_FORM:
156      case IPR_MM_STAT:
157      case IPR_IFAULT_VA_FORM:
158      case IPR_EXC_MASK:
159      case IPR_EXC_SUM:
160        retval = ipr[idx];
161        break;
162
163      case IPR_DTB_PTE:
164        {
165            TlbEntry &entry
166                = tc->getDTBPtr()->index(!tc->misspeculating());
167
168            retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
169            retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
170            retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
171            retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
172            retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
173            retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
174            retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
175        }
176        break;
177
178        // write only registers
179      case IPR_HWINT_CLR:
180      case IPR_SL_XMIT:
181      case IPR_DC_FLUSH:
182      case IPR_IC_FLUSH:
183      case IPR_ALT_MODE:
184      case IPR_DTB_IA:
185      case IPR_DTB_IAP:
186      case IPR_ITB_IA:
187      case IPR_ITB_IAP:
188        panic("Tried to read write only register %d\n", idx);
189        break;
190
191      default:
192        // invalid IPR
193        panic("Tried to read from invalid ipr %d\n", idx);
194        break;
195    }
196
197    return retval;
198}
199
200// Cause the simulator to break when changing to the following IPL
201int break_ipl = -1;
202
203void
204ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
205{
206    uint64_t old;
207
208    if (tc->misspeculating())
209        return;
210
211    switch (idx) {
212      case IPR_PALtemp0:
213      case IPR_PALtemp1:
214      case IPR_PALtemp2:
215      case IPR_PALtemp3:
216      case IPR_PALtemp4:
217      case IPR_PALtemp5:
218      case IPR_PALtemp6:
219      case IPR_PALtemp7:
220      case IPR_PALtemp8:
221      case IPR_PALtemp9:
222      case IPR_PALtemp10:
223      case IPR_PALtemp11:
224      case IPR_PALtemp12:
225      case IPR_PALtemp13:
226      case IPR_PALtemp14:
227      case IPR_PALtemp15:
228      case IPR_PALtemp16:
229      case IPR_PALtemp17:
230      case IPR_PALtemp18:
231      case IPR_PALtemp19:
232      case IPR_PALtemp20:
233      case IPR_PALtemp21:
234      case IPR_PALtemp22:
235      case IPR_PAL_BASE:
236      case IPR_IC_PERR_STAT:
237      case IPR_DC_PERR_STAT:
238      case IPR_PMCTR:
239        // write entire quad w/ no side-effect
240        ipr[idx] = val;
241        break;
242
243      case IPR_CC_CTL:
244        // This IPR resets the cycle counter.  We assume this only
245        // happens once... let's verify that.
246        assert(ipr[idx] == 0);
247        ipr[idx] = 1;
248        break;
249
250      case IPR_CC:
251        // This IPR only writes the upper 64 bits.  It's ok to write
252        // all 64 here since we mask out the lower 32 in rpcc (see
253        // isa_desc).
254        ipr[idx] = val;
255        break;
256
257      case IPR_PALtemp23:
258        // write entire quad w/ no side-effect
259        old = ipr[idx];
260        ipr[idx] = val;
261        if (tc->getKernelStats())
262            tc->getKernelStats()->context(old, val, tc);
263        break;
264
265      case IPR_DTB_PTE:
266        // write entire quad w/ no side-effect, tag is forthcoming
267        ipr[idx] = val;
268        break;
269
270      case IPR_EXC_ADDR:
271        // second least significant bit in PC is always zero
272        ipr[idx] = val & ~2;
273        break;
274
275      case IPR_ASTRR:
276      case IPR_ASTER:
277        // only write least significant four bits - privilege mask
278        ipr[idx] = val & 0xf;
279        break;
280
281      case IPR_IPLR:
282#ifdef DEBUG
283        if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
284            Debug::breakpoint();
285#endif
286
287        // only write least significant five bits - interrupt level
288        ipr[idx] = val & 0x1f;
289        if (tc->getKernelStats())
290            tc->getKernelStats()->swpipl(ipr[idx]);
291        break;
292
293      case IPR_DTB_CM:
294        if (val & 0x18) {
295            if (tc->getKernelStats())
296                tc->getKernelStats()->mode(Kernel::user, tc);
297        } else {
298            if (tc->getKernelStats())
299                tc->getKernelStats()->mode(Kernel::kernel, tc);
300        }
301
302      case IPR_ICM:
303        // only write two mode bits - processor mode
304        ipr[idx] = val & 0x18;
305        break;
306
307      case IPR_ALT_MODE:
308        // only write two mode bits - processor mode
309        ipr[idx] = val & 0x18;
310        break;
311
312      case IPR_MCSR:
313        // more here after optimization...
314        ipr[idx] = val;
315        break;
316
317      case IPR_SIRR:
318        // only write software interrupt mask
319        ipr[idx] = val & 0x7fff0;
320        break;
321
322      case IPR_ICSR:
323        ipr[idx] = val & ULL(0xffffff0300);
324        break;
325
326      case IPR_IVPTBR:
327      case IPR_MVPTBR:
328        ipr[idx] = val & ULL(0xffffffffc0000000);
329        break;
330
331      case IPR_DC_TEST_CTL:
332        ipr[idx] = val & 0x1ffb;
333        break;
334
335      case IPR_DC_MODE:
336      case IPR_MAF_MODE:
337        ipr[idx] = val & 0x3f;
338        break;
339
340      case IPR_ITB_ASN:
341        ipr[idx] = val & 0x7f0;
342        break;
343
344      case IPR_DTB_ASN:
345        ipr[idx] = val & ULL(0xfe00000000000000);
346        break;
347
348      case IPR_EXC_SUM:
349      case IPR_EXC_MASK:
350        // any write to this register clears it
351        ipr[idx] = 0;
352        break;
353
354      case IPR_INTID:
355      case IPR_SL_RCV:
356      case IPR_MM_STAT:
357      case IPR_ITB_PTE_TEMP:
358      case IPR_DTB_PTE_TEMP:
359        // read-only registers
360        panic("Tried to write read only ipr %d\n", idx);
361
362      case IPR_HWINT_CLR:
363      case IPR_SL_XMIT:
364      case IPR_DC_FLUSH:
365      case IPR_IC_FLUSH:
366        // the following are write only
367        ipr[idx] = val;
368        break;
369
370      case IPR_DTB_IA:
371        // really a control write
372        ipr[idx] = 0;
373
374        tc->getDTBPtr()->flushAll();
375        break;
376
377      case IPR_DTB_IAP:
378        // really a control write
379        ipr[idx] = 0;
380
381        tc->getDTBPtr()->flushProcesses();
382        break;
383
384      case IPR_DTB_IS:
385        // really a control write
386        ipr[idx] = val;
387
388        tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
389        break;
390
391      case IPR_DTB_TAG: {
392          struct TlbEntry entry;
393
394          // FIXME: granularity hints NYI...
395          if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
396              panic("PTE GH field != 0");
397
398          // write entire quad
399          ipr[idx] = val;
400
401          // construct PTE for new entry
402          entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
403          entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
404          entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
405          entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
406          entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
407          entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
408          entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
409
410          // insert new TAG/PTE value into data TLB
411          tc->getDTBPtr()->insert(val, entry);
412      }
413        break;
414
415      case IPR_ITB_PTE: {
416          struct TlbEntry entry;
417
418          // FIXME: granularity hints NYI...
419          if (ITB_PTE_GH(val) != 0)
420              panic("PTE GH field != 0");
421
422          // write entire quad
423          ipr[idx] = val;
424
425          // construct PTE for new entry
426          entry.ppn = ITB_PTE_PPN(val);
427          entry.xre = ITB_PTE_XRE(val);
428          entry.xwe = 0;
429          entry.fonr = ITB_PTE_FONR(val);
430          entry.fonw = ITB_PTE_FONW(val);
431          entry.asma = ITB_PTE_ASMA(val);
432          entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
433
434          // insert new TAG/PTE value into data TLB
435          tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
436      }
437        break;
438
439      case IPR_ITB_IA:
440        // really a control write
441        ipr[idx] = 0;
442
443        tc->getITBPtr()->flushAll();
444        break;
445
446      case IPR_ITB_IAP:
447        // really a control write
448        ipr[idx] = 0;
449
450        tc->getITBPtr()->flushProcesses();
451        break;
452
453      case IPR_ITB_IS:
454        // really a control write
455        ipr[idx] = val;
456
457        tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
458        break;
459
460      default:
461        // invalid IPR
462        panic("Tried to write to invalid ipr %d\n", idx);
463    }
464
465    // no error...
466}
467
468void
469copyIprs(ThreadContext *src, ThreadContext *dest)
470{
471    for (int i = 0; i < NumInternalProcRegs; ++i)
472        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
473}
474
475} // namespace AlphaISA
476
477using namespace AlphaISA;
478
479Fault
480SimpleThread::hwrei()
481{
482    PCState pc = pcState();
483    if (!(pc.pc() & 0x3))
484        return new UnimplementedOpcodeFault;
485
486    pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
487    pcState(pc);
488
489    CPA::cpa()->swAutoBegin(tc, pc.npc());
490
491    if (!misspeculating()) {
492        if (kernelStats)
493            kernelStats->hwrei();
494    }
495
496    // FIXME: XXX check for interrupts? XXX
497    return NoFault;
498}
499
500/**
501 * Check for special simulator handling of specific PAL calls.
502 * If return value is false, actual PAL call will be suppressed.
503 */
504bool
505SimpleThread::simPalCheck(int palFunc)
506{
507    if (kernelStats)
508        kernelStats->callpal(palFunc, tc);
509
510    switch (palFunc) {
511      case PAL::halt:
512        halt();
513        if (--System::numSystemsRunning == 0)
514            exitSimLoop("all cpus halted");
515        break;
516
517      case PAL::bpt:
518      case PAL::bugchk:
519        if (system->breakpoint())
520            return false;
521        break;
522    }
523
524    return true;
525}
526