ev5.cc revision 8607
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/kernel_stats.hh" 35#include "arch/alpha/osfpal.hh" 36#include "arch/alpha/tlb.hh" 37#include "base/cp_annotate.hh" 38#include "base/debug.hh" 39#include "config/full_system.hh" 40#include "cpu/base.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/thread_context.hh" 43#include "sim/sim_exit.hh" 44 45namespace AlphaISA { 46 47#if FULL_SYSTEM 48 49//////////////////////////////////////////////////////////////////////// 50// 51// Machine dependent functions 52// 53void 54initCPU(ThreadContext *tc, int cpuId) 55{ 56 initIPRs(tc, cpuId); 57 58 tc->setIntReg(16, cpuId); 59 tc->setIntReg(0, cpuId); 60 61 AlphaFault *reset = new ResetFault; 62 63 tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 64 65 delete reset; 66} 67 68template <class CPU> 69void 70zeroRegisters(CPU *cpu) 71{ 72 // Insure ISA semantics 73 // (no longer very clean due to the change in setIntReg() in the 74 // cpu model. Consider changing later.) 75 cpu->thread->setIntReg(ZeroReg, 0); 76 cpu->thread->setFloatReg(ZeroReg, 0.0); 77} 78 79#endif 80 81//////////////////////////////////////////////////////////////////////// 82// 83// 84// 85void 86initIPRs(ThreadContext *tc, int cpuId) 87{ 88 for (int i = 0; i < NumInternalProcRegs; ++i) { 89 tc->setMiscRegNoEffect(i, 0); 90 } 91 92 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); 93 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 94 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 95} 96 97MiscReg 98ISA::readIpr(int idx, ThreadContext *tc) 99{ 100 uint64_t retval = 0; // return value, default 0 101 102 switch (idx) { 103 case IPR_PALtemp0: 104 case IPR_PALtemp1: 105 case IPR_PALtemp2: 106 case IPR_PALtemp3: 107 case IPR_PALtemp4: 108 case IPR_PALtemp5: 109 case IPR_PALtemp6: 110 case IPR_PALtemp7: 111 case IPR_PALtemp8: 112 case IPR_PALtemp9: 113 case IPR_PALtemp10: 114 case IPR_PALtemp11: 115 case IPR_PALtemp12: 116 case IPR_PALtemp13: 117 case IPR_PALtemp14: 118 case IPR_PALtemp15: 119 case IPR_PALtemp16: 120 case IPR_PALtemp17: 121 case IPR_PALtemp18: 122 case IPR_PALtemp19: 123 case IPR_PALtemp20: 124 case IPR_PALtemp21: 125 case IPR_PALtemp22: 126 case IPR_PALtemp23: 127 case IPR_PAL_BASE: 128 129 case IPR_IVPTBR: 130 case IPR_DC_MODE: 131 case IPR_MAF_MODE: 132 case IPR_ISR: 133 case IPR_EXC_ADDR: 134 case IPR_IC_PERR_STAT: 135 case IPR_DC_PERR_STAT: 136 case IPR_MCSR: 137 case IPR_ASTRR: 138 case IPR_ASTER: 139 case IPR_SIRR: 140 case IPR_ICSR: 141 case IPR_ICM: 142 case IPR_DTB_CM: 143 case IPR_IPLR: 144 case IPR_INTID: 145 case IPR_PMCTR: 146 // no side-effect 147 retval = ipr[idx]; 148 break; 149 150 case IPR_CC: 151 retval |= ipr[idx] & ULL(0xffffffff00000000); 152 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 153 break; 154 155 case IPR_VA: 156 retval = ipr[idx]; 157 break; 158 159 case IPR_VA_FORM: 160 case IPR_MM_STAT: 161 case IPR_IFAULT_VA_FORM: 162 case IPR_EXC_MASK: 163 case IPR_EXC_SUM: 164 retval = ipr[idx]; 165 break; 166 167 case IPR_DTB_PTE: 168 { 169 TlbEntry &entry 170 = tc->getDTBPtr()->index(!tc->misspeculating()); 171 172 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 173 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 174 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 175 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 176 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 177 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 178 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; 179 } 180 break; 181 182 // write only registers 183 case IPR_HWINT_CLR: 184 case IPR_SL_XMIT: 185 case IPR_DC_FLUSH: 186 case IPR_IC_FLUSH: 187 case IPR_ALT_MODE: 188 case IPR_DTB_IA: 189 case IPR_DTB_IAP: 190 case IPR_ITB_IA: 191 case IPR_ITB_IAP: 192 panic("Tried to read write only register %d\n", idx); 193 break; 194 195 default: 196 // invalid IPR 197 panic("Tried to read from invalid ipr %d\n", idx); 198 break; 199 } 200 201 return retval; 202} 203 204#ifdef DEBUG 205// Cause the simulator to break when changing to the following IPL 206int break_ipl = -1; 207#endif 208 209void 210ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) 211{ 212 if (tc->misspeculating()) 213 return; 214 215 switch (idx) { 216 case IPR_PALtemp0: 217 case IPR_PALtemp1: 218 case IPR_PALtemp2: 219 case IPR_PALtemp3: 220 case IPR_PALtemp4: 221 case IPR_PALtemp5: 222 case IPR_PALtemp6: 223 case IPR_PALtemp7: 224 case IPR_PALtemp8: 225 case IPR_PALtemp9: 226 case IPR_PALtemp10: 227 case IPR_PALtemp11: 228 case IPR_PALtemp12: 229 case IPR_PALtemp13: 230 case IPR_PALtemp14: 231 case IPR_PALtemp15: 232 case IPR_PALtemp16: 233 case IPR_PALtemp17: 234 case IPR_PALtemp18: 235 case IPR_PALtemp19: 236 case IPR_PALtemp20: 237 case IPR_PALtemp21: 238 case IPR_PALtemp22: 239 case IPR_PAL_BASE: 240 case IPR_IC_PERR_STAT: 241 case IPR_DC_PERR_STAT: 242 case IPR_PMCTR: 243 // write entire quad w/ no side-effect 244 ipr[idx] = val; 245 break; 246 247 case IPR_CC_CTL: 248 // This IPR resets the cycle counter. We assume this only 249 // happens once... let's verify that. 250 assert(ipr[idx] == 0); 251 ipr[idx] = 1; 252 break; 253 254 case IPR_CC: 255 // This IPR only writes the upper 64 bits. It's ok to write 256 // all 64 here since we mask out the lower 32 in rpcc (see 257 // isa_desc). 258 ipr[idx] = val; 259 break; 260 261 case IPR_PALtemp23: 262 // write entire quad w/ no side-effect 263#if FULL_SYSTEM 264 if (tc->getKernelStats()) 265 tc->getKernelStats()->context(ipr[idx], val, tc); 266#endif 267 ipr[idx] = val; 268 break; 269 270 case IPR_DTB_PTE: 271 // write entire quad w/ no side-effect, tag is forthcoming 272 ipr[idx] = val; 273 break; 274 275 case IPR_EXC_ADDR: 276 // second least significant bit in PC is always zero 277 ipr[idx] = val & ~2; 278 break; 279 280 case IPR_ASTRR: 281 case IPR_ASTER: 282 // only write least significant four bits - privilege mask 283 ipr[idx] = val & 0xf; 284 break; 285 286 case IPR_IPLR: 287#ifdef DEBUG 288 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f)) 289 Debug::breakpoint(); 290#endif 291 292 // only write least significant five bits - interrupt level 293 ipr[idx] = val & 0x1f; 294#if FULL_SYSTEM 295 if (tc->getKernelStats()) 296 tc->getKernelStats()->swpipl(ipr[idx]); 297#endif 298 break; 299 300 case IPR_DTB_CM: 301#if FULL_SYSTEM 302 if (val & 0x18) { 303 if (tc->getKernelStats()) 304 tc->getKernelStats()->mode(Kernel::user, tc); 305 } else { 306 if (tc->getKernelStats()) 307 tc->getKernelStats()->mode(Kernel::kernel, tc); 308 } 309#endif 310 311 case IPR_ICM: 312 // only write two mode bits - processor mode 313 ipr[idx] = val & 0x18; 314 break; 315 316 case IPR_ALT_MODE: 317 // only write two mode bits - processor mode 318 ipr[idx] = val & 0x18; 319 break; 320 321 case IPR_MCSR: 322 // more here after optimization... 323 ipr[idx] = val; 324 break; 325 326 case IPR_SIRR: 327 // only write software interrupt mask 328 ipr[idx] = val & 0x7fff0; 329 break; 330 331 case IPR_ICSR: 332 ipr[idx] = val & ULL(0xffffff0300); 333 break; 334 335 case IPR_IVPTBR: 336 case IPR_MVPTBR: 337 ipr[idx] = val & ULL(0xffffffffc0000000); 338 break; 339 340 case IPR_DC_TEST_CTL: 341 ipr[idx] = val & 0x1ffb; 342 break; 343 344 case IPR_DC_MODE: 345 case IPR_MAF_MODE: 346 ipr[idx] = val & 0x3f; 347 break; 348 349 case IPR_ITB_ASN: 350 ipr[idx] = val & 0x7f0; 351 break; 352 353 case IPR_DTB_ASN: 354 ipr[idx] = val & ULL(0xfe00000000000000); 355 break; 356 357 case IPR_EXC_SUM: 358 case IPR_EXC_MASK: 359 // any write to this register clears it 360 ipr[idx] = 0; 361 break; 362 363 case IPR_INTID: 364 case IPR_SL_RCV: 365 case IPR_MM_STAT: 366 case IPR_ITB_PTE_TEMP: 367 case IPR_DTB_PTE_TEMP: 368 // read-only registers 369 panic("Tried to write read only ipr %d\n", idx); 370 371 case IPR_HWINT_CLR: 372 case IPR_SL_XMIT: 373 case IPR_DC_FLUSH: 374 case IPR_IC_FLUSH: 375 // the following are write only 376 ipr[idx] = val; 377 break; 378 379 case IPR_DTB_IA: 380 // really a control write 381 ipr[idx] = 0; 382 383 tc->getDTBPtr()->flushAll(); 384 break; 385 386 case IPR_DTB_IAP: 387 // really a control write 388 ipr[idx] = 0; 389 390 tc->getDTBPtr()->flushProcesses(); 391 break; 392 393 case IPR_DTB_IS: 394 // really a control write 395 ipr[idx] = val; 396 397 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); 398 break; 399 400 case IPR_DTB_TAG: { 401 struct TlbEntry entry; 402 403 // FIXME: granularity hints NYI... 404 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) 405 panic("PTE GH field != 0"); 406 407 // write entire quad 408 ipr[idx] = val; 409 410 // construct PTE for new entry 411 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]); 412 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 413 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 414 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 415 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 416 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 417 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 418 419 // insert new TAG/PTE value into data TLB 420 tc->getDTBPtr()->insert(val, entry); 421 } 422 break; 423 424 case IPR_ITB_PTE: { 425 struct TlbEntry entry; 426 427 // FIXME: granularity hints NYI... 428 if (ITB_PTE_GH(val) != 0) 429 panic("PTE GH field != 0"); 430 431 // write entire quad 432 ipr[idx] = val; 433 434 // construct PTE for new entry 435 entry.ppn = ITB_PTE_PPN(val); 436 entry.xre = ITB_PTE_XRE(val); 437 entry.xwe = 0; 438 entry.fonr = ITB_PTE_FONR(val); 439 entry.fonw = ITB_PTE_FONW(val); 440 entry.asma = ITB_PTE_ASMA(val); 441 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 442 443 // insert new TAG/PTE value into data TLB 444 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry); 445 } 446 break; 447 448 case IPR_ITB_IA: 449 // really a control write 450 ipr[idx] = 0; 451 452 tc->getITBPtr()->flushAll(); 453 break; 454 455 case IPR_ITB_IAP: 456 // really a control write 457 ipr[idx] = 0; 458 459 tc->getITBPtr()->flushProcesses(); 460 break; 461 462 case IPR_ITB_IS: 463 // really a control write 464 ipr[idx] = val; 465 466 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); 467 break; 468 469 default: 470 // invalid IPR 471 panic("Tried to write to invalid ipr %d\n", idx); 472 } 473 474 // no error... 475} 476 477void 478copyIprs(ThreadContext *src, ThreadContext *dest) 479{ 480 for (int i = 0; i < NumInternalProcRegs; ++i) 481 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 482} 483 484} // namespace AlphaISA 485 486#if FULL_SYSTEM 487 488using namespace AlphaISA; 489 490Fault 491SimpleThread::hwrei() 492{ 493 PCState pc = pcState(); 494 if (!(pc.pc() & 0x3)) 495 return new UnimplementedOpcodeFault; 496 497 pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR)); 498 pcState(pc); 499 500 CPA::cpa()->swAutoBegin(tc, pc.npc()); 501 502 if (!misspeculating()) { 503 if (kernelStats) 504 kernelStats->hwrei(); 505 } 506 507 // FIXME: XXX check for interrupts? XXX 508 return NoFault; 509} 510 511/** 512 * Check for special simulator handling of specific PAL calls. 513 * If return value is false, actual PAL call will be suppressed. 514 */ 515bool 516SimpleThread::simPalCheck(int palFunc) 517{ 518 if (kernelStats) 519 kernelStats->callpal(palFunc, tc); 520 521 switch (palFunc) { 522 case PAL::halt: 523 halt(); 524 if (--System::numSystemsRunning == 0) 525 exitSimLoop("all cpus halted"); 526 break; 527 528 case PAL::bpt: 529 case PAL::bugchk: 530 if (system->breakpoint()) 531 return false; 532 break; 533 } 534 535 return true; 536} 537 538#endif // FULL_SYSTEM 539