ev5.cc revision 7720
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/kernel_stats.hh" 35#include "arch/alpha/osfpal.hh" 36#include "arch/alpha/tlb.hh" 37#include "base/cp_annotate.hh" 38#include "base/debug.hh" 39#include "config/full_system.hh" 40#include "cpu/base.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/thread_context.hh" 43#include "sim/sim_exit.hh" 44 45namespace AlphaISA { 46 47#if FULL_SYSTEM 48 49//////////////////////////////////////////////////////////////////////// 50// 51// Machine dependent functions 52// 53void 54initCPU(ThreadContext *tc, int cpuId) 55{ 56 initIPRs(tc, cpuId); 57 58 tc->setIntReg(16, cpuId); 59 tc->setIntReg(0, cpuId); 60 61 AlphaFault *reset = new ResetFault; 62 63 tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 64 65 delete reset; 66} 67 68template <class CPU> 69void 70zeroRegisters(CPU *cpu) 71{ 72 // Insure ISA semantics 73 // (no longer very clean due to the change in setIntReg() in the 74 // cpu model. Consider changing later.) 75 cpu->thread->setIntReg(ZeroReg, 0); 76 cpu->thread->setFloatReg(ZeroReg, 0.0); 77} 78 79#endif 80 81//////////////////////////////////////////////////////////////////////// 82// 83// 84// 85void 86initIPRs(ThreadContext *tc, int cpuId) 87{ 88 for (int i = 0; i < NumInternalProcRegs; ++i) { 89 tc->setMiscRegNoEffect(i, 0); 90 } 91 92 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); 93 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 94 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 95} 96 97MiscReg 98ISA::readIpr(int idx, ThreadContext *tc) 99{ 100 uint64_t retval = 0; // return value, default 0 101 102 switch (idx) { 103 case IPR_PALtemp0: 104 case IPR_PALtemp1: 105 case IPR_PALtemp2: 106 case IPR_PALtemp3: 107 case IPR_PALtemp4: 108 case IPR_PALtemp5: 109 case IPR_PALtemp6: 110 case IPR_PALtemp7: 111 case IPR_PALtemp8: 112 case IPR_PALtemp9: 113 case IPR_PALtemp10: 114 case IPR_PALtemp11: 115 case IPR_PALtemp12: 116 case IPR_PALtemp13: 117 case IPR_PALtemp14: 118 case IPR_PALtemp15: 119 case IPR_PALtemp16: 120 case IPR_PALtemp17: 121 case IPR_PALtemp18: 122 case IPR_PALtemp19: 123 case IPR_PALtemp20: 124 case IPR_PALtemp21: 125 case IPR_PALtemp22: 126 case IPR_PALtemp23: 127 case IPR_PAL_BASE: 128 129 case IPR_IVPTBR: 130 case IPR_DC_MODE: 131 case IPR_MAF_MODE: 132 case IPR_ISR: 133 case IPR_EXC_ADDR: 134 case IPR_IC_PERR_STAT: 135 case IPR_DC_PERR_STAT: 136 case IPR_MCSR: 137 case IPR_ASTRR: 138 case IPR_ASTER: 139 case IPR_SIRR: 140 case IPR_ICSR: 141 case IPR_ICM: 142 case IPR_DTB_CM: 143 case IPR_IPLR: 144 case IPR_INTID: 145 case IPR_PMCTR: 146 // no side-effect 147 retval = ipr[idx]; 148 break; 149 150 case IPR_CC: 151 retval |= ipr[idx] & ULL(0xffffffff00000000); 152 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 153 break; 154 155 case IPR_VA: 156 retval = ipr[idx]; 157 break; 158 159 case IPR_VA_FORM: 160 case IPR_MM_STAT: 161 case IPR_IFAULT_VA_FORM: 162 case IPR_EXC_MASK: 163 case IPR_EXC_SUM: 164 retval = ipr[idx]; 165 break; 166 167 case IPR_DTB_PTE: 168 { 169 TlbEntry &entry 170 = tc->getDTBPtr()->index(!tc->misspeculating()); 171 172 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 173 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 174 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 175 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 176 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 177 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 178 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; 179 } 180 break; 181 182 // write only registers 183 case IPR_HWINT_CLR: 184 case IPR_SL_XMIT: 185 case IPR_DC_FLUSH: 186 case IPR_IC_FLUSH: 187 case IPR_ALT_MODE: 188 case IPR_DTB_IA: 189 case IPR_DTB_IAP: 190 case IPR_ITB_IA: 191 case IPR_ITB_IAP: 192 panic("Tried to read write only register %d\n", idx); 193 break; 194 195 default: 196 // invalid IPR 197 panic("Tried to read from invalid ipr %d\n", idx); 198 break; 199 } 200 201 return retval; 202} 203 204#ifdef DEBUG 205// Cause the simulator to break when changing to the following IPL 206int break_ipl = -1; 207#endif 208 209void 210ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) 211{ 212 uint64_t old; 213 214 if (tc->misspeculating()) 215 return; 216 217 switch (idx) { 218 case IPR_PALtemp0: 219 case IPR_PALtemp1: 220 case IPR_PALtemp2: 221 case IPR_PALtemp3: 222 case IPR_PALtemp4: 223 case IPR_PALtemp5: 224 case IPR_PALtemp6: 225 case IPR_PALtemp7: 226 case IPR_PALtemp8: 227 case IPR_PALtemp9: 228 case IPR_PALtemp10: 229 case IPR_PALtemp11: 230 case IPR_PALtemp12: 231 case IPR_PALtemp13: 232 case IPR_PALtemp14: 233 case IPR_PALtemp15: 234 case IPR_PALtemp16: 235 case IPR_PALtemp17: 236 case IPR_PALtemp18: 237 case IPR_PALtemp19: 238 case IPR_PALtemp20: 239 case IPR_PALtemp21: 240 case IPR_PALtemp22: 241 case IPR_PAL_BASE: 242 case IPR_IC_PERR_STAT: 243 case IPR_DC_PERR_STAT: 244 case IPR_PMCTR: 245 // write entire quad w/ no side-effect 246 ipr[idx] = val; 247 break; 248 249 case IPR_CC_CTL: 250 // This IPR resets the cycle counter. We assume this only 251 // happens once... let's verify that. 252 assert(ipr[idx] == 0); 253 ipr[idx] = 1; 254 break; 255 256 case IPR_CC: 257 // This IPR only writes the upper 64 bits. It's ok to write 258 // all 64 here since we mask out the lower 32 in rpcc (see 259 // isa_desc). 260 ipr[idx] = val; 261 break; 262 263 case IPR_PALtemp23: 264 // write entire quad w/ no side-effect 265 old = ipr[idx]; 266 ipr[idx] = val; 267#if FULL_SYSTEM 268 if (tc->getKernelStats()) 269 tc->getKernelStats()->context(old, val, tc); 270#endif 271 break; 272 273 case IPR_DTB_PTE: 274 // write entire quad w/ no side-effect, tag is forthcoming 275 ipr[idx] = val; 276 break; 277 278 case IPR_EXC_ADDR: 279 // second least significant bit in PC is always zero 280 ipr[idx] = val & ~2; 281 break; 282 283 case IPR_ASTRR: 284 case IPR_ASTER: 285 // only write least significant four bits - privilege mask 286 ipr[idx] = val & 0xf; 287 break; 288 289 case IPR_IPLR: 290#ifdef DEBUG 291 if (break_ipl != -1 && break_ipl == (int)(val & 0x1f)) 292 debug_break(); 293#endif 294 295 // only write least significant five bits - interrupt level 296 ipr[idx] = val & 0x1f; 297#if FULL_SYSTEM 298 if (tc->getKernelStats()) 299 tc->getKernelStats()->swpipl(ipr[idx]); 300#endif 301 break; 302 303 case IPR_DTB_CM: 304#if FULL_SYSTEM 305 if (val & 0x18) { 306 if (tc->getKernelStats()) 307 tc->getKernelStats()->mode(Kernel::user, tc); 308 } else { 309 if (tc->getKernelStats()) 310 tc->getKernelStats()->mode(Kernel::kernel, tc); 311 } 312#endif 313 314 case IPR_ICM: 315 // only write two mode bits - processor mode 316 ipr[idx] = val & 0x18; 317 break; 318 319 case IPR_ALT_MODE: 320 // only write two mode bits - processor mode 321 ipr[idx] = val & 0x18; 322 break; 323 324 case IPR_MCSR: 325 // more here after optimization... 326 ipr[idx] = val; 327 break; 328 329 case IPR_SIRR: 330 // only write software interrupt mask 331 ipr[idx] = val & 0x7fff0; 332 break; 333 334 case IPR_ICSR: 335 ipr[idx] = val & ULL(0xffffff0300); 336 break; 337 338 case IPR_IVPTBR: 339 case IPR_MVPTBR: 340 ipr[idx] = val & ULL(0xffffffffc0000000); 341 break; 342 343 case IPR_DC_TEST_CTL: 344 ipr[idx] = val & 0x1ffb; 345 break; 346 347 case IPR_DC_MODE: 348 case IPR_MAF_MODE: 349 ipr[idx] = val & 0x3f; 350 break; 351 352 case IPR_ITB_ASN: 353 ipr[idx] = val & 0x7f0; 354 break; 355 356 case IPR_DTB_ASN: 357 ipr[idx] = val & ULL(0xfe00000000000000); 358 break; 359 360 case IPR_EXC_SUM: 361 case IPR_EXC_MASK: 362 // any write to this register clears it 363 ipr[idx] = 0; 364 break; 365 366 case IPR_INTID: 367 case IPR_SL_RCV: 368 case IPR_MM_STAT: 369 case IPR_ITB_PTE_TEMP: 370 case IPR_DTB_PTE_TEMP: 371 // read-only registers 372 panic("Tried to write read only ipr %d\n", idx); 373 374 case IPR_HWINT_CLR: 375 case IPR_SL_XMIT: 376 case IPR_DC_FLUSH: 377 case IPR_IC_FLUSH: 378 // the following are write only 379 ipr[idx] = val; 380 break; 381 382 case IPR_DTB_IA: 383 // really a control write 384 ipr[idx] = 0; 385 386 tc->getDTBPtr()->flushAll(); 387 break; 388 389 case IPR_DTB_IAP: 390 // really a control write 391 ipr[idx] = 0; 392 393 tc->getDTBPtr()->flushProcesses(); 394 break; 395 396 case IPR_DTB_IS: 397 // really a control write 398 ipr[idx] = val; 399 400 tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); 401 break; 402 403 case IPR_DTB_TAG: { 404 struct TlbEntry entry; 405 406 // FIXME: granularity hints NYI... 407 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) 408 panic("PTE GH field != 0"); 409 410 // write entire quad 411 ipr[idx] = val; 412 413 // construct PTE for new entry 414 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]); 415 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 416 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 417 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 418 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 419 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 420 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 421 422 // insert new TAG/PTE value into data TLB 423 tc->getDTBPtr()->insert(val, entry); 424 } 425 break; 426 427 case IPR_ITB_PTE: { 428 struct TlbEntry entry; 429 430 // FIXME: granularity hints NYI... 431 if (ITB_PTE_GH(val) != 0) 432 panic("PTE GH field != 0"); 433 434 // write entire quad 435 ipr[idx] = val; 436 437 // construct PTE for new entry 438 entry.ppn = ITB_PTE_PPN(val); 439 entry.xre = ITB_PTE_XRE(val); 440 entry.xwe = 0; 441 entry.fonr = ITB_PTE_FONR(val); 442 entry.fonw = ITB_PTE_FONW(val); 443 entry.asma = ITB_PTE_ASMA(val); 444 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 445 446 // insert new TAG/PTE value into data TLB 447 tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry); 448 } 449 break; 450 451 case IPR_ITB_IA: 452 // really a control write 453 ipr[idx] = 0; 454 455 tc->getITBPtr()->flushAll(); 456 break; 457 458 case IPR_ITB_IAP: 459 // really a control write 460 ipr[idx] = 0; 461 462 tc->getITBPtr()->flushProcesses(); 463 break; 464 465 case IPR_ITB_IS: 466 // really a control write 467 ipr[idx] = val; 468 469 tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); 470 break; 471 472 default: 473 // invalid IPR 474 panic("Tried to write to invalid ipr %d\n", idx); 475 } 476 477 // no error... 478} 479 480void 481copyIprs(ThreadContext *src, ThreadContext *dest) 482{ 483 for (int i = 0; i < NumInternalProcRegs; ++i) 484 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 485} 486 487} // namespace AlphaISA 488 489#if FULL_SYSTEM 490 491using namespace AlphaISA; 492 493Fault 494SimpleThread::hwrei() 495{ 496 PCState pc = pcState(); 497 if (!(pc.pc() & 0x3)) 498 return new UnimplementedOpcodeFault; 499 500 pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR)); 501 pcState(pc); 502 503 CPA::cpa()->swAutoBegin(tc, pc.npc()); 504 505 if (!misspeculating()) { 506 if (kernelStats) 507 kernelStats->hwrei(); 508 } 509 510 // FIXME: XXX check for interrupts? XXX 511 return NoFault; 512} 513 514/** 515 * Check for special simulator handling of specific PAL calls. 516 * If return value is false, actual PAL call will be suppressed. 517 */ 518bool 519SimpleThread::simPalCheck(int palFunc) 520{ 521 if (kernelStats) 522 kernelStats->callpal(palFunc, tc); 523 524 switch (palFunc) { 525 case PAL::halt: 526 halt(); 527 if (--System::numSystemsRunning == 0) 528 exitSimLoop("all cpus halted"); 529 break; 530 531 case PAL::bpt: 532 case PAL::bugchk: 533 if (system->breakpoint()) 534 return false; 535 break; 536 } 537 538 return true; 539} 540 541#endif // FULL_SYSTEM 542