ev5.cc revision 6331:d947798df4a1 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "arch/alpha/kgdb.h"
38#include "base/cp_annotate.hh"
39#include "base/debug.hh"
40#include "base/remote_gdb.hh"
41#include "base/stats/events.hh"
42#include "config/full_system.hh"
43#include "cpu/base.hh"
44#include "cpu/simple_thread.hh"
45#include "cpu/thread_context.hh"
46#include "sim/sim_exit.hh"
47
48namespace AlphaISA {
49
50#if FULL_SYSTEM
51
52////////////////////////////////////////////////////////////////////////
53//
54//  Machine dependent functions
55//
56void
57initCPU(ThreadContext *tc, int cpuId)
58{
59    initIPRs(tc, cpuId);
60
61    tc->setIntReg(16, cpuId);
62    tc->setIntReg(0, cpuId);
63
64    AlphaFault *reset = new ResetFault;
65
66    tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
67    tc->setNextPC(tc->readPC() + sizeof(MachInst));
68
69    delete reset;
70}
71
72
73template <class CPU>
74void
75processInterrupts(CPU *cpu)
76{
77    //Check if there are any outstanding interrupts
78    //Handle the interrupts
79    int ipl = 0;
80    int summary = 0;
81
82    if (cpu->readMiscRegNoEffect(IPR_ASTRR))
83        panic("asynchronous traps not implemented\n");
84
85    if (cpu->readMiscRegNoEffect(IPR_SIRR)) {
86        for (int i = INTLEVEL_SOFTWARE_MIN;
87             i < INTLEVEL_SOFTWARE_MAX; i++) {
88            if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
89                // See table 4-19 of the 21164 hardware reference
90                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
91                summary |= (ULL(1) << i);
92            }
93        }
94    }
95
96    uint64_t interrupts = cpu->intr_status();
97
98    if (interrupts) {
99        for (int i = INTLEVEL_EXTERNAL_MIN;
100             i < INTLEVEL_EXTERNAL_MAX; i++) {
101            if (interrupts & (ULL(1) << i)) {
102                // See table 4-19 of the 21164 hardware reference
103                ipl = i;
104                summary |= (ULL(1) << i);
105            }
106        }
107    }
108
109    if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) {
110        cpu->setMiscRegNoEffect(IPR_ISR, summary);
111        cpu->setMiscRegNoEffect(IPR_INTID, ipl);
112        cpu->trap(new InterruptFault);
113        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
114                cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
115    }
116
117}
118
119template <class CPU>
120void
121zeroRegisters(CPU *cpu)
122{
123    // Insure ISA semantics
124    // (no longer very clean due to the change in setIntReg() in the
125    // cpu model.  Consider changing later.)
126    cpu->thread->setIntReg(ZeroReg, 0);
127    cpu->thread->setFloatReg(ZeroReg, 0.0);
128}
129
130#endif
131
132////////////////////////////////////////////////////////////////////////
133//
134//
135//
136void
137initIPRs(ThreadContext *tc, int cpuId)
138{
139    for (int i = 0; i < NumInternalProcRegs; ++i) {
140        tc->setMiscRegNoEffect(i, 0);
141    }
142
143    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
144    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
145    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
146}
147
148MiscReg
149ISA::readIpr(int idx, ThreadContext *tc)
150{
151    uint64_t retval = 0;        // return value, default 0
152
153    switch (idx) {
154      case IPR_PALtemp0:
155      case IPR_PALtemp1:
156      case IPR_PALtemp2:
157      case IPR_PALtemp3:
158      case IPR_PALtemp4:
159      case IPR_PALtemp5:
160      case IPR_PALtemp6:
161      case IPR_PALtemp7:
162      case IPR_PALtemp8:
163      case IPR_PALtemp9:
164      case IPR_PALtemp10:
165      case IPR_PALtemp11:
166      case IPR_PALtemp12:
167      case IPR_PALtemp13:
168      case IPR_PALtemp14:
169      case IPR_PALtemp15:
170      case IPR_PALtemp16:
171      case IPR_PALtemp17:
172      case IPR_PALtemp18:
173      case IPR_PALtemp19:
174      case IPR_PALtemp20:
175      case IPR_PALtemp21:
176      case IPR_PALtemp22:
177      case IPR_PALtemp23:
178      case IPR_PAL_BASE:
179
180      case IPR_IVPTBR:
181      case IPR_DC_MODE:
182      case IPR_MAF_MODE:
183      case IPR_ISR:
184      case IPR_EXC_ADDR:
185      case IPR_IC_PERR_STAT:
186      case IPR_DC_PERR_STAT:
187      case IPR_MCSR:
188      case IPR_ASTRR:
189      case IPR_ASTER:
190      case IPR_SIRR:
191      case IPR_ICSR:
192      case IPR_ICM:
193      case IPR_DTB_CM:
194      case IPR_IPLR:
195      case IPR_INTID:
196      case IPR_PMCTR:
197        // no side-effect
198        retval = ipr[idx];
199        break;
200
201      case IPR_CC:
202        retval |= ipr[idx] & ULL(0xffffffff00000000);
203        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
204        break;
205
206      case IPR_VA:
207        retval = ipr[idx];
208        break;
209
210      case IPR_VA_FORM:
211      case IPR_MM_STAT:
212      case IPR_IFAULT_VA_FORM:
213      case IPR_EXC_MASK:
214      case IPR_EXC_SUM:
215        retval = ipr[idx];
216        break;
217
218      case IPR_DTB_PTE:
219        {
220            TlbEntry &entry
221                = tc->getDTBPtr()->index(!tc->misspeculating());
222
223            retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
224            retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
225            retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
226            retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
227            retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
228            retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
229            retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
230        }
231        break;
232
233        // write only registers
234      case IPR_HWINT_CLR:
235      case IPR_SL_XMIT:
236      case IPR_DC_FLUSH:
237      case IPR_IC_FLUSH:
238      case IPR_ALT_MODE:
239      case IPR_DTB_IA:
240      case IPR_DTB_IAP:
241      case IPR_ITB_IA:
242      case IPR_ITB_IAP:
243        panic("Tried to read write only register %d\n", idx);
244        break;
245
246      default:
247        // invalid IPR
248        panic("Tried to read from invalid ipr %d\n", idx);
249        break;
250    }
251
252    return retval;
253}
254
255#ifdef DEBUG
256// Cause the simulator to break when changing to the following IPL
257int break_ipl = -1;
258#endif
259
260void
261ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
262{
263    uint64_t old;
264
265    if (tc->misspeculating())
266        return;
267
268    switch (idx) {
269      case IPR_PALtemp0:
270      case IPR_PALtemp1:
271      case IPR_PALtemp2:
272      case IPR_PALtemp3:
273      case IPR_PALtemp4:
274      case IPR_PALtemp5:
275      case IPR_PALtemp6:
276      case IPR_PALtemp7:
277      case IPR_PALtemp8:
278      case IPR_PALtemp9:
279      case IPR_PALtemp10:
280      case IPR_PALtemp11:
281      case IPR_PALtemp12:
282      case IPR_PALtemp13:
283      case IPR_PALtemp14:
284      case IPR_PALtemp15:
285      case IPR_PALtemp16:
286      case IPR_PALtemp17:
287      case IPR_PALtemp18:
288      case IPR_PALtemp19:
289      case IPR_PALtemp20:
290      case IPR_PALtemp21:
291      case IPR_PALtemp22:
292      case IPR_PAL_BASE:
293      case IPR_IC_PERR_STAT:
294      case IPR_DC_PERR_STAT:
295      case IPR_PMCTR:
296        // write entire quad w/ no side-effect
297        ipr[idx] = val;
298        break;
299
300      case IPR_CC_CTL:
301        // This IPR resets the cycle counter.  We assume this only
302        // happens once... let's verify that.
303        assert(ipr[idx] == 0);
304        ipr[idx] = 1;
305        break;
306
307      case IPR_CC:
308        // This IPR only writes the upper 64 bits.  It's ok to write
309        // all 64 here since we mask out the lower 32 in rpcc (see
310        // isa_desc).
311        ipr[idx] = val;
312        break;
313
314      case IPR_PALtemp23:
315        // write entire quad w/ no side-effect
316        old = ipr[idx];
317        ipr[idx] = val;
318#if FULL_SYSTEM
319        if (tc->getKernelStats())
320            tc->getKernelStats()->context(old, val, tc);
321#endif
322        break;
323
324      case IPR_DTB_PTE:
325        // write entire quad w/ no side-effect, tag is forthcoming
326        ipr[idx] = val;
327        break;
328
329      case IPR_EXC_ADDR:
330        // second least significant bit in PC is always zero
331        ipr[idx] = val & ~2;
332        break;
333
334      case IPR_ASTRR:
335      case IPR_ASTER:
336        // only write least significant four bits - privilege mask
337        ipr[idx] = val & 0xf;
338        break;
339
340      case IPR_IPLR:
341#ifdef DEBUG
342        if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
343            debug_break();
344#endif
345
346        // only write least significant five bits - interrupt level
347        ipr[idx] = val & 0x1f;
348#if FULL_SYSTEM
349        if (tc->getKernelStats())
350            tc->getKernelStats()->swpipl(ipr[idx]);
351#endif
352        break;
353
354      case IPR_DTB_CM:
355#if FULL_SYSTEM
356        if (val & 0x18) {
357            if (tc->getKernelStats())
358                tc->getKernelStats()->mode(Kernel::user, tc);
359        } else {
360            if (tc->getKernelStats())
361                tc->getKernelStats()->mode(Kernel::kernel, tc);
362        }
363#endif
364
365      case IPR_ICM:
366        // only write two mode bits - processor mode
367        ipr[idx] = val & 0x18;
368        break;
369
370      case IPR_ALT_MODE:
371        // only write two mode bits - processor mode
372        ipr[idx] = val & 0x18;
373        break;
374
375      case IPR_MCSR:
376        // more here after optimization...
377        ipr[idx] = val;
378        break;
379
380      case IPR_SIRR:
381        // only write software interrupt mask
382        ipr[idx] = val & 0x7fff0;
383        break;
384
385      case IPR_ICSR:
386        ipr[idx] = val & ULL(0xffffff0300);
387        break;
388
389      case IPR_IVPTBR:
390      case IPR_MVPTBR:
391        ipr[idx] = val & ULL(0xffffffffc0000000);
392        break;
393
394      case IPR_DC_TEST_CTL:
395        ipr[idx] = val & 0x1ffb;
396        break;
397
398      case IPR_DC_MODE:
399      case IPR_MAF_MODE:
400        ipr[idx] = val & 0x3f;
401        break;
402
403      case IPR_ITB_ASN:
404        ipr[idx] = val & 0x7f0;
405        break;
406
407      case IPR_DTB_ASN:
408        ipr[idx] = val & ULL(0xfe00000000000000);
409        break;
410
411      case IPR_EXC_SUM:
412      case IPR_EXC_MASK:
413        // any write to this register clears it
414        ipr[idx] = 0;
415        break;
416
417      case IPR_INTID:
418      case IPR_SL_RCV:
419      case IPR_MM_STAT:
420      case IPR_ITB_PTE_TEMP:
421      case IPR_DTB_PTE_TEMP:
422        // read-only registers
423        panic("Tried to write read only ipr %d\n", idx);
424
425      case IPR_HWINT_CLR:
426      case IPR_SL_XMIT:
427      case IPR_DC_FLUSH:
428      case IPR_IC_FLUSH:
429        // the following are write only
430        ipr[idx] = val;
431        break;
432
433      case IPR_DTB_IA:
434        // really a control write
435        ipr[idx] = 0;
436
437        tc->getDTBPtr()->flushAll();
438        break;
439
440      case IPR_DTB_IAP:
441        // really a control write
442        ipr[idx] = 0;
443
444        tc->getDTBPtr()->flushProcesses();
445        break;
446
447      case IPR_DTB_IS:
448        // really a control write
449        ipr[idx] = val;
450
451        tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
452        break;
453
454      case IPR_DTB_TAG: {
455          struct TlbEntry entry;
456
457          // FIXME: granularity hints NYI...
458          if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
459              panic("PTE GH field != 0");
460
461          // write entire quad
462          ipr[idx] = val;
463
464          // construct PTE for new entry
465          entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
466          entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
467          entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
468          entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
469          entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
470          entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
471          entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
472
473          // insert new TAG/PTE value into data TLB
474          tc->getDTBPtr()->insert(val, entry);
475      }
476        break;
477
478      case IPR_ITB_PTE: {
479          struct TlbEntry entry;
480
481          // FIXME: granularity hints NYI...
482          if (ITB_PTE_GH(val) != 0)
483              panic("PTE GH field != 0");
484
485          // write entire quad
486          ipr[idx] = val;
487
488          // construct PTE for new entry
489          entry.ppn = ITB_PTE_PPN(val);
490          entry.xre = ITB_PTE_XRE(val);
491          entry.xwe = 0;
492          entry.fonr = ITB_PTE_FONR(val);
493          entry.fonw = ITB_PTE_FONW(val);
494          entry.asma = ITB_PTE_ASMA(val);
495          entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
496
497          // insert new TAG/PTE value into data TLB
498          tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
499      }
500        break;
501
502      case IPR_ITB_IA:
503        // really a control write
504        ipr[idx] = 0;
505
506        tc->getITBPtr()->flushAll();
507        break;
508
509      case IPR_ITB_IAP:
510        // really a control write
511        ipr[idx] = 0;
512
513        tc->getITBPtr()->flushProcesses();
514        break;
515
516      case IPR_ITB_IS:
517        // really a control write
518        ipr[idx] = val;
519
520        tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
521        break;
522
523      default:
524        // invalid IPR
525        panic("Tried to write to invalid ipr %d\n", idx);
526    }
527
528    // no error...
529}
530
531void
532copyIprs(ThreadContext *src, ThreadContext *dest)
533{
534    for (int i = 0; i < NumInternalProcRegs; ++i)
535        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
536}
537
538} // namespace AlphaISA
539
540#if FULL_SYSTEM
541
542using namespace AlphaISA;
543
544Fault
545SimpleThread::hwrei()
546{
547    if (!(readPC() & 0x3))
548        return new UnimplementedOpcodeFault;
549
550    setNextPC(readMiscRegNoEffect(IPR_EXC_ADDR));
551
552    CPA::cpa()->swAutoBegin(tc, readNextPC());
553
554    if (!misspeculating()) {
555        if (kernelStats)
556            kernelStats->hwrei();
557    }
558
559    // FIXME: XXX check for interrupts? XXX
560    return NoFault;
561}
562
563/**
564 * Check for special simulator handling of specific PAL calls.
565 * If return value is false, actual PAL call will be suppressed.
566 */
567bool
568SimpleThread::simPalCheck(int palFunc)
569{
570    if (kernelStats)
571        kernelStats->callpal(palFunc, tc);
572
573    switch (palFunc) {
574      case PAL::halt:
575        halt();
576        if (--System::numSystemsRunning == 0)
577            exitSimLoop("all cpus halted");
578        break;
579
580      case PAL::bpt:
581      case PAL::bugchk:
582        if (system->breakpoint())
583            return false;
584        break;
585    }
586
587    return true;
588}
589
590#endif // FULL_SYSTEM
591