ev5.cc revision 596
1/* $Id$ */ 2 3#include "targetarch/alpha_memory.hh" 4#include "sim/annotation.hh" 5#ifdef DEBUG 6#include "sim/debug.hh" 7#endif 8#include "cpu/exec_context.hh" 9#include "sim/sim_events.hh" 10#include "targetarch/isa_traits.hh" 11#include "base/remote_gdb.hh" 12#include "base/kgdb.h" // for ALPHA_KENTRY_IF 13#include "targetarch/osfpal.hh" 14 15#ifdef FULL_SYSTEM 16 17#ifndef SYSTEM_EV5 18#error This code is only valid for EV5 systems 19#endif 20 21//////////////////////////////////////////////////////////////////////// 22// 23// 24// 25void 26AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) 27{ 28 if (regs->pal_shadow == use_shadow) 29 panic("swap_palshadow: wrong PAL shadow state"); 30 31 regs->pal_shadow = use_shadow; 32 33 for (int i = 0; i < NumIntRegs; i++) { 34 if (reg_redir[i]) { 35 IntReg temp = regs->intRegFile[i]; 36 regs->intRegFile[i] = regs->palregs[i]; 37 regs->palregs[i] = temp; 38 } 39 } 40} 41 42//////////////////////////////////////////////////////////////////////// 43// 44// Machine dependent functions 45// 46void 47AlphaISA::initCPU(RegFile *regs) 48{ 49 initIPRs(regs); 50 // CPU comes up with PAL regs enabled 51 swap_palshadow(regs, true); 52 53 regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; 54 regs->npc = regs->pc + sizeof(MachInst); 55} 56 57//////////////////////////////////////////////////////////////////////// 58// 59// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE 60// 61Addr 62AlphaISA::fault_addr[Num_Faults] = { 63 0x0000, /* No_Fault */ 64 0x0001, /* Reset_Fault */ 65 0x0401, /* Machine_Check_Fault */ 66 0x0501, /* Arithmetic_Fault */ 67 0x0101, /* Interrupt_Fault */ 68 0x0201, /* Ndtb_Miss_Fault */ 69 0x0281, /* Pdtb_Miss_Fault */ 70 0x0301, /* Alignment_Fault */ 71 0x0381, /* Dtb_Fault_Fault */ 72 0x0381, /* Dtb_Acv_Fault */ 73 0x0181, /* Itb_Miss_Fault */ 74 0x0181, /* Itb_Fault_Fault */ 75 0x0081, /* Itb_Acv_Fault */ 76 0x0481, /* Unimplemented_Opcode_Fault */ 77 0x0581, /* Fen_Fault */ 78 0x2001, /* Pal_Fault */ 79 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */ 80}; 81 82const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { 83 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 84 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, 85 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 86 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 }; 87 88//////////////////////////////////////////////////////////////////////// 89// 90// 91// 92void 93AlphaISA::initIPRs(RegFile *regs) 94{ 95 uint64_t *ipr = regs->ipr; 96 97 bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); 98 ipr[IPR_PAL_BASE] = PAL_BASE; 99 ipr[IPR_MCSR] = 0x6; 100} 101 102 103void 104ExecContext::ev5_trap(Fault fault) 105{ 106 assert(!misspeculating()); 107 kernelStats.fault(fault); 108 109 if (fault == Arithmetic_Fault) 110 panic("Arithmetic traps are unimplemented!"); 111 112 AlphaISA::InternalProcReg *ipr = regs.ipr; 113 114 // exception restart address 115 if (fault != Interrupt_Fault || !PC_PAL(regs.pc)) 116 ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc; 117 118 if (fault == Pal_Fault || fault == Arithmetic_Fault /* || 119 fault == Interrupt_Fault && !PC_PAL(regs.pc) */) { 120 // traps... skip faulting instruction 121 ipr[AlphaISA::IPR_EXC_ADDR] += 4; 122 } 123 124 if (!PC_PAL(regs.pc)) 125 AlphaISA::swap_palshadow(®s, true); 126 127 regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault]; 128 regs.npc = regs.pc + sizeof(MachInst); 129 130 Annotate::Ev5Trap(this, fault); 131} 132 133 134void 135AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) 136{ 137 InternalProcReg *ipr = regs->ipr; 138 bool use_pc = (fault == No_Fault); 139 140 if (fault == Arithmetic_Fault) 141 panic("arithmetic faults NYI..."); 142 143 // compute exception restart address 144 if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) { 145 // traps... skip faulting instruction 146 ipr[IPR_EXC_ADDR] = regs->pc + 4; 147 } else { 148 // fault, post fault at excepting instruction 149 ipr[IPR_EXC_ADDR] = regs->pc; 150 } 151 152 // jump to expection address (PAL PC bit set here as well...) 153 if (!use_pc) 154 regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault]; 155 else 156 regs->npc = ipr[IPR_PAL_BASE] + pc; 157 158 // that's it! (orders of magnitude less painful than x86) 159} 160 161bool AlphaISA::check_interrupts = false; 162 163Fault 164ExecContext::hwrei() 165{ 166 uint64_t *ipr = regs.ipr; 167 168 if (!PC_PAL(regs.pc)) 169 return Unimplemented_Opcode_Fault; 170 171 setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); 172 173 if (!misspeculating()) { 174 kernelStats.hwrei(); 175 176 if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) 177 AlphaISA::swap_palshadow(®s, false); 178 179 AlphaISA::check_interrupts = true; 180 } 181 182 // FIXME: XXX check for interrupts? XXX 183 return No_Fault; 184} 185 186uint64_t 187ExecContext::readIpr(int idx, Fault &fault) 188{ 189 uint64_t *ipr = regs.ipr; 190 uint64_t retval = 0; // return value, default 0 191 192 switch (idx) { 193 case AlphaISA::IPR_PALtemp0: 194 case AlphaISA::IPR_PALtemp1: 195 case AlphaISA::IPR_PALtemp2: 196 case AlphaISA::IPR_PALtemp3: 197 case AlphaISA::IPR_PALtemp4: 198 case AlphaISA::IPR_PALtemp5: 199 case AlphaISA::IPR_PALtemp6: 200 case AlphaISA::IPR_PALtemp7: 201 case AlphaISA::IPR_PALtemp8: 202 case AlphaISA::IPR_PALtemp9: 203 case AlphaISA::IPR_PALtemp10: 204 case AlphaISA::IPR_PALtemp11: 205 case AlphaISA::IPR_PALtemp12: 206 case AlphaISA::IPR_PALtemp13: 207 case AlphaISA::IPR_PALtemp14: 208 case AlphaISA::IPR_PALtemp15: 209 case AlphaISA::IPR_PALtemp16: 210 case AlphaISA::IPR_PALtemp17: 211 case AlphaISA::IPR_PALtemp18: 212 case AlphaISA::IPR_PALtemp19: 213 case AlphaISA::IPR_PALtemp20: 214 case AlphaISA::IPR_PALtemp21: 215 case AlphaISA::IPR_PALtemp22: 216 case AlphaISA::IPR_PALtemp23: 217 case AlphaISA::IPR_PAL_BASE: 218 219 case AlphaISA::IPR_IVPTBR: 220 case AlphaISA::IPR_DC_MODE: 221 case AlphaISA::IPR_MAF_MODE: 222 case AlphaISA::IPR_ISR: 223 case AlphaISA::IPR_EXC_ADDR: 224 case AlphaISA::IPR_IC_PERR_STAT: 225 case AlphaISA::IPR_DC_PERR_STAT: 226 case AlphaISA::IPR_MCSR: 227 case AlphaISA::IPR_ASTRR: 228 case AlphaISA::IPR_ASTER: 229 case AlphaISA::IPR_SIRR: 230 case AlphaISA::IPR_ICSR: 231 case AlphaISA::IPR_ICM: 232 case AlphaISA::IPR_DTB_CM: 233 case AlphaISA::IPR_IPLR: 234 case AlphaISA::IPR_INTID: 235 case AlphaISA::IPR_PMCTR: 236 // no side-effect 237 retval = ipr[idx]; 238 break; 239 240 case AlphaISA::IPR_VA: 241 // SFX: unlocks interrupt status registers 242 retval = ipr[idx]; 243 244 if (!misspeculating()) 245 regs.intrlock = false; 246 break; 247 248 case AlphaISA::IPR_VA_FORM: 249 case AlphaISA::IPR_MM_STAT: 250 case AlphaISA::IPR_IFAULT_VA_FORM: 251 case AlphaISA::IPR_EXC_MASK: 252 case AlphaISA::IPR_EXC_SUM: 253 retval = ipr[idx]; 254 break; 255 256 case AlphaISA::IPR_DTB_PTE: 257 { 258 AlphaISA::PTE &pte = dtb->index(!misspeculating()); 259 260 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 261 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 262 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 263 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 264 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 265 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 266 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 267 } 268 break; 269 270 // write only registers 271 case AlphaISA::IPR_HWINT_CLR: 272 case AlphaISA::IPR_SL_XMIT: 273 case AlphaISA::IPR_DC_FLUSH: 274 case AlphaISA::IPR_IC_FLUSH: 275 case AlphaISA::IPR_ALT_MODE: 276 case AlphaISA::IPR_DTB_IA: 277 case AlphaISA::IPR_DTB_IAP: 278 case AlphaISA::IPR_ITB_IA: 279 case AlphaISA::IPR_ITB_IAP: 280 fault = Unimplemented_Opcode_Fault; 281 break; 282 283 default: 284 // invalid IPR 285 fault = Unimplemented_Opcode_Fault; 286 break; 287 } 288 289 return retval; 290} 291 292#ifdef DEBUG 293// Cause the simulator to break when changing to the following IPL 294int break_ipl = -1; 295#endif 296 297Fault 298ExecContext::setIpr(int idx, uint64_t val) 299{ 300 uint64_t *ipr = regs.ipr; 301 302 if (misspeculating()) 303 return No_Fault; 304 305 switch (idx) { 306 case AlphaISA::IPR_PALtemp0: 307 case AlphaISA::IPR_PALtemp1: 308 case AlphaISA::IPR_PALtemp2: 309 case AlphaISA::IPR_PALtemp3: 310 case AlphaISA::IPR_PALtemp4: 311 case AlphaISA::IPR_PALtemp5: 312 case AlphaISA::IPR_PALtemp6: 313 case AlphaISA::IPR_PALtemp7: 314 case AlphaISA::IPR_PALtemp8: 315 case AlphaISA::IPR_PALtemp9: 316 case AlphaISA::IPR_PALtemp10: 317 case AlphaISA::IPR_PALtemp11: 318 case AlphaISA::IPR_PALtemp12: 319 case AlphaISA::IPR_PALtemp13: 320 case AlphaISA::IPR_PALtemp14: 321 case AlphaISA::IPR_PALtemp15: 322 case AlphaISA::IPR_PALtemp16: 323 case AlphaISA::IPR_PALtemp17: 324 case AlphaISA::IPR_PALtemp18: 325 case AlphaISA::IPR_PALtemp19: 326 case AlphaISA::IPR_PALtemp20: 327 case AlphaISA::IPR_PALtemp21: 328 case AlphaISA::IPR_PALtemp22: 329 case AlphaISA::IPR_PAL_BASE: 330 case AlphaISA::IPR_IC_PERR_STAT: 331 case AlphaISA::IPR_DC_PERR_STAT: 332 case AlphaISA::IPR_PMCTR: 333 // write entire quad w/ no side-effect 334 ipr[idx] = val; 335 break; 336 337 case AlphaISA::IPR_CC_CTL: 338 // This IPR resets the cycle counter. We assume this only 339 // happens once... let's verify that. 340 assert(ipr[idx] == 0); 341 ipr[idx] = 1; 342 break; 343 344 case AlphaISA::IPR_CC: 345 // This IPR only writes the upper 64 bits. It's ok to write 346 // all 64 here since we mask out the lower 32 in rpcc (see 347 // isa_desc). 348 ipr[idx] = val; 349 break; 350 351 case AlphaISA::IPR_PALtemp23: 352 // write entire quad w/ no side-effect 353 ipr[idx] = val; 354 kernelStats.context(ipr[idx]); 355 Annotate::Context(this); 356 break; 357 358 case AlphaISA::IPR_DTB_PTE: 359 // write entire quad w/ no side-effect, tag is forthcoming 360 ipr[idx] = val; 361 break; 362 363 case AlphaISA::IPR_EXC_ADDR: 364 // second least significant bit in PC is always zero 365 ipr[idx] = val & ~2; 366 break; 367 368 case AlphaISA::IPR_ASTRR: 369 case AlphaISA::IPR_ASTER: 370 // only write least significant four bits - privilege mask 371 ipr[idx] = val & 0xf; 372 break; 373 374 case AlphaISA::IPR_IPLR: 375#ifdef DEBUG 376 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 377 debug_break(); 378#endif 379 380 // only write least significant five bits - interrupt level 381 ipr[idx] = val & 0x1f; 382 kernelStats.swpipl(ipr[idx]); 383 Annotate::IPL(this, val & 0x1f); 384 break; 385 386 case AlphaISA::IPR_DTB_CM: 387 Annotate::ChangeMode(this, (val & 0x18) != 0); 388 kernelStats.mode((val & 0x18) != 0); 389 390 case AlphaISA::IPR_ICM: 391 // only write two mode bits - processor mode 392 ipr[idx] = val & 0x18; 393 break; 394 395 case AlphaISA::IPR_ALT_MODE: 396 // only write two mode bits - processor mode 397 ipr[idx] = val & 0x18; 398 break; 399 400 case AlphaISA::IPR_MCSR: 401 // more here after optimization... 402 ipr[idx] = val; 403 break; 404 405 case AlphaISA::IPR_SIRR: 406 // only write software interrupt mask 407 ipr[idx] = val & 0x7fff0; 408 break; 409 410 case AlphaISA::IPR_ICSR: 411 ipr[idx] = val & ULL(0xffffff0300); 412 break; 413 414 case AlphaISA::IPR_IVPTBR: 415 case AlphaISA::IPR_MVPTBR: 416 ipr[idx] = val & ULL(0xffffffffc0000000); 417 break; 418 419 case AlphaISA::IPR_DC_TEST_CTL: 420 ipr[idx] = val & 0x1ffb; 421 break; 422 423 case AlphaISA::IPR_DC_MODE: 424 case AlphaISA::IPR_MAF_MODE: 425 ipr[idx] = val & 0x3f; 426 break; 427 428 case AlphaISA::IPR_ITB_ASN: 429 ipr[idx] = val & 0x7f0; 430 break; 431 432 case AlphaISA::IPR_DTB_ASN: 433 ipr[idx] = val & ULL(0xfe00000000000000); 434 break; 435 436 case AlphaISA::IPR_EXC_SUM: 437 case AlphaISA::IPR_EXC_MASK: 438 // any write to this register clears it 439 ipr[idx] = 0; 440 break; 441 442 case AlphaISA::IPR_INTID: 443 case AlphaISA::IPR_SL_RCV: 444 case AlphaISA::IPR_MM_STAT: 445 case AlphaISA::IPR_ITB_PTE_TEMP: 446 case AlphaISA::IPR_DTB_PTE_TEMP: 447 // read-only registers 448 return Unimplemented_Opcode_Fault; 449 450 case AlphaISA::IPR_HWINT_CLR: 451 case AlphaISA::IPR_SL_XMIT: 452 case AlphaISA::IPR_DC_FLUSH: 453 case AlphaISA::IPR_IC_FLUSH: 454 // the following are write only 455 ipr[idx] = val; 456 break; 457 458 case AlphaISA::IPR_DTB_IA: 459 // really a control write 460 ipr[idx] = 0; 461 462 dtb->flushAll(); 463 break; 464 465 case AlphaISA::IPR_DTB_IAP: 466 // really a control write 467 ipr[idx] = 0; 468 469 dtb->flushProcesses(); 470 break; 471 472 case AlphaISA::IPR_DTB_IS: 473 // really a control write 474 ipr[idx] = val; 475 476 dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 477 break; 478 479 case AlphaISA::IPR_DTB_TAG: { 480 struct AlphaISA::PTE pte; 481 482 // FIXME: granularity hints NYI... 483 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 484 panic("PTE GH field != 0"); 485 486 // write entire quad 487 ipr[idx] = val; 488 489 // construct PTE for new entry 490 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 491 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 492 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 493 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 494 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 495 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 496 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 497 498 // insert new TAG/PTE value into data TLB 499 dtb->insert(val, pte); 500 } 501 break; 502 503 case AlphaISA::IPR_ITB_PTE: { 504 struct AlphaISA::PTE pte; 505 506 // FIXME: granularity hints NYI... 507 if (ITB_PTE_GH(val) != 0) 508 panic("PTE GH field != 0"); 509 510 // write entire quad 511 ipr[idx] = val; 512 513 // construct PTE for new entry 514 pte.ppn = ITB_PTE_PPN(val); 515 pte.xre = ITB_PTE_XRE(val); 516 pte.xwe = 0; 517 pte.fonr = ITB_PTE_FONR(val); 518 pte.fonw = ITB_PTE_FONW(val); 519 pte.asma = ITB_PTE_ASMA(val); 520 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 521 522 // insert new TAG/PTE value into data TLB 523 itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 524 } 525 break; 526 527 case AlphaISA::IPR_ITB_IA: 528 // really a control write 529 ipr[idx] = 0; 530 531 itb->flushAll(); 532 break; 533 534 case AlphaISA::IPR_ITB_IAP: 535 // really a control write 536 ipr[idx] = 0; 537 538 itb->flushProcesses(); 539 break; 540 541 case AlphaISA::IPR_ITB_IS: 542 // really a control write 543 ipr[idx] = val; 544 545 itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 546 break; 547 548 default: 549 // invalid IPR 550 return Unimplemented_Opcode_Fault; 551 } 552 553 // no error... 554 return No_Fault; 555} 556 557/** 558 * Check for special simulator handling of specific PAL calls. 559 * If return value is false, actual PAL call will be suppressed. 560 */ 561bool 562ExecContext::simPalCheck(int palFunc) 563{ 564 kernelStats.callpal(palFunc); 565 566 switch (palFunc) { 567 case PAL::halt: 568 halt(); 569 if (--System::numSystemsRunning == 0) 570 new SimExitEvent("all cpus halted"); 571 break; 572 573 case PAL::bpt: 574 case PAL::bugchk: 575 if (system->breakpoint()) 576 return false; 577 break; 578 } 579 580 return true; 581} 582 583#endif // FULL_SYSTEM 584