ev5.cc revision 5566
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/kernel_stats.hh" 35#include "arch/alpha/osfpal.hh" 36#include "arch/alpha/tlb.hh" 37#include "arch/alpha/kgdb.h" 38#include "base/remote_gdb.hh" 39#include "base/stats/events.hh" 40#include "config/full_system.hh" 41#include "cpu/base.hh" 42#include "cpu/simple_thread.hh" 43#include "cpu/thread_context.hh" 44#include "sim/debug.hh" 45#include "sim/sim_exit.hh" 46 47using namespace AlphaISA; 48 49#if FULL_SYSTEM 50 51//////////////////////////////////////////////////////////////////////// 52// 53// Machine dependent functions 54// 55void 56AlphaISA::initCPU(ThreadContext *tc, int cpuId) 57{ 58 initIPRs(tc, cpuId); 59 60 tc->setIntReg(16, cpuId); 61 tc->setIntReg(0, cpuId); 62 63 AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; 64 65 tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 66 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 67 68 delete reset; 69} 70 71 72template <class CPU> 73void 74AlphaISA::processInterrupts(CPU *cpu) 75{ 76 //Check if there are any outstanding interrupts 77 //Handle the interrupts 78 int ipl = 0; 79 int summary = 0; 80 81 if (cpu->readMiscRegNoEffect(IPR_ASTRR)) 82 panic("asynchronous traps not implemented\n"); 83 84 if (cpu->readMiscRegNoEffect(IPR_SIRR)) { 85 for (int i = INTLEVEL_SOFTWARE_MIN; 86 i < INTLEVEL_SOFTWARE_MAX; i++) { 87 if (cpu->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 88 // See table 4-19 of the 21164 hardware reference 89 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 90 summary |= (ULL(1) << i); 91 } 92 } 93 } 94 95 uint64_t interrupts = cpu->intr_status(); 96 97 if (interrupts) { 98 for (int i = INTLEVEL_EXTERNAL_MIN; 99 i < INTLEVEL_EXTERNAL_MAX; i++) { 100 if (interrupts & (ULL(1) << i)) { 101 // See table 4-19 of the 21164 hardware reference 102 ipl = i; 103 summary |= (ULL(1) << i); 104 } 105 } 106 } 107 108 if (ipl && ipl > cpu->readMiscRegNoEffect(IPR_IPLR)) { 109 cpu->setMiscRegNoEffect(IPR_ISR, summary); 110 cpu->setMiscRegNoEffect(IPR_INTID, ipl); 111 cpu->trap(new InterruptFault); 112 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 113 cpu->readMiscRegNoEffect(IPR_IPLR), ipl, summary); 114 } 115 116} 117 118template <class CPU> 119void 120AlphaISA::zeroRegisters(CPU *cpu) 121{ 122 // Insure ISA semantics 123 // (no longer very clean due to the change in setIntReg() in the 124 // cpu model. Consider changing later.) 125 cpu->thread->setIntReg(ZeroReg, 0); 126 cpu->thread->setFloatReg(ZeroReg, 0.0); 127} 128 129Fault 130SimpleThread::hwrei() 131{ 132 if (!(readPC() & 0x3)) 133 return new UnimplementedOpcodeFault; 134 135 setNextPC(readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR)); 136 137 if (!misspeculating()) { 138 if (kernelStats) 139 kernelStats->hwrei(); 140 } 141 142 // FIXME: XXX check for interrupts? XXX 143 return NoFault; 144} 145 146int 147AlphaISA::MiscRegFile::getInstAsid() 148{ 149 return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 150} 151 152int 153AlphaISA::MiscRegFile::getDataAsid() 154{ 155 return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 156} 157 158#endif 159 160//////////////////////////////////////////////////////////////////////// 161// 162// 163// 164void 165AlphaISA::initIPRs(ThreadContext *tc, int cpuId) 166{ 167 for (int i = 0; i < NumInternalProcRegs; ++i) { 168 tc->setMiscRegNoEffect(i, 0); 169 } 170 171 tc->setMiscRegNoEffect(IPR_PAL_BASE, AlphaISA::PalBase); 172 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 173 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 174} 175 176AlphaISA::MiscReg 177AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) 178{ 179 uint64_t retval = 0; // return value, default 0 180 181 switch (idx) { 182 case AlphaISA::IPR_PALtemp0: 183 case AlphaISA::IPR_PALtemp1: 184 case AlphaISA::IPR_PALtemp2: 185 case AlphaISA::IPR_PALtemp3: 186 case AlphaISA::IPR_PALtemp4: 187 case AlphaISA::IPR_PALtemp5: 188 case AlphaISA::IPR_PALtemp6: 189 case AlphaISA::IPR_PALtemp7: 190 case AlphaISA::IPR_PALtemp8: 191 case AlphaISA::IPR_PALtemp9: 192 case AlphaISA::IPR_PALtemp10: 193 case AlphaISA::IPR_PALtemp11: 194 case AlphaISA::IPR_PALtemp12: 195 case AlphaISA::IPR_PALtemp13: 196 case AlphaISA::IPR_PALtemp14: 197 case AlphaISA::IPR_PALtemp15: 198 case AlphaISA::IPR_PALtemp16: 199 case AlphaISA::IPR_PALtemp17: 200 case AlphaISA::IPR_PALtemp18: 201 case AlphaISA::IPR_PALtemp19: 202 case AlphaISA::IPR_PALtemp20: 203 case AlphaISA::IPR_PALtemp21: 204 case AlphaISA::IPR_PALtemp22: 205 case AlphaISA::IPR_PALtemp23: 206 case AlphaISA::IPR_PAL_BASE: 207 208 case AlphaISA::IPR_IVPTBR: 209 case AlphaISA::IPR_DC_MODE: 210 case AlphaISA::IPR_MAF_MODE: 211 case AlphaISA::IPR_ISR: 212 case AlphaISA::IPR_EXC_ADDR: 213 case AlphaISA::IPR_IC_PERR_STAT: 214 case AlphaISA::IPR_DC_PERR_STAT: 215 case AlphaISA::IPR_MCSR: 216 case AlphaISA::IPR_ASTRR: 217 case AlphaISA::IPR_ASTER: 218 case AlphaISA::IPR_SIRR: 219 case AlphaISA::IPR_ICSR: 220 case AlphaISA::IPR_ICM: 221 case AlphaISA::IPR_DTB_CM: 222 case AlphaISA::IPR_IPLR: 223 case AlphaISA::IPR_INTID: 224 case AlphaISA::IPR_PMCTR: 225 // no side-effect 226 retval = ipr[idx]; 227 break; 228 229 case AlphaISA::IPR_CC: 230 retval |= ipr[idx] & ULL(0xffffffff00000000); 231 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 232 break; 233 234 case AlphaISA::IPR_VA: 235 retval = ipr[idx]; 236 break; 237 238 case AlphaISA::IPR_VA_FORM: 239 case AlphaISA::IPR_MM_STAT: 240 case AlphaISA::IPR_IFAULT_VA_FORM: 241 case AlphaISA::IPR_EXC_MASK: 242 case AlphaISA::IPR_EXC_SUM: 243 retval = ipr[idx]; 244 break; 245 246 case AlphaISA::IPR_DTB_PTE: 247 { 248 AlphaISA::TlbEntry &entry 249 = tc->getDTBPtr()->index(!tc->misspeculating()); 250 251 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 252 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 253 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 254 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 255 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 256 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 257 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; 258 } 259 break; 260 261 // write only registers 262 case AlphaISA::IPR_HWINT_CLR: 263 case AlphaISA::IPR_SL_XMIT: 264 case AlphaISA::IPR_DC_FLUSH: 265 case AlphaISA::IPR_IC_FLUSH: 266 case AlphaISA::IPR_ALT_MODE: 267 case AlphaISA::IPR_DTB_IA: 268 case AlphaISA::IPR_DTB_IAP: 269 case AlphaISA::IPR_ITB_IA: 270 case AlphaISA::IPR_ITB_IAP: 271 panic("Tried to read write only register %d\n", idx); 272 break; 273 274 default: 275 // invalid IPR 276 panic("Tried to read from invalid ipr %d\n", idx); 277 break; 278 } 279 280 return retval; 281} 282 283#ifdef DEBUG 284// Cause the simulator to break when changing to the following IPL 285int break_ipl = -1; 286#endif 287 288void 289AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) 290{ 291 uint64_t old; 292 293 if (tc->misspeculating()) 294 return; 295 296 switch (idx) { 297 case AlphaISA::IPR_PALtemp0: 298 case AlphaISA::IPR_PALtemp1: 299 case AlphaISA::IPR_PALtemp2: 300 case AlphaISA::IPR_PALtemp3: 301 case AlphaISA::IPR_PALtemp4: 302 case AlphaISA::IPR_PALtemp5: 303 case AlphaISA::IPR_PALtemp6: 304 case AlphaISA::IPR_PALtemp7: 305 case AlphaISA::IPR_PALtemp8: 306 case AlphaISA::IPR_PALtemp9: 307 case AlphaISA::IPR_PALtemp10: 308 case AlphaISA::IPR_PALtemp11: 309 case AlphaISA::IPR_PALtemp12: 310 case AlphaISA::IPR_PALtemp13: 311 case AlphaISA::IPR_PALtemp14: 312 case AlphaISA::IPR_PALtemp15: 313 case AlphaISA::IPR_PALtemp16: 314 case AlphaISA::IPR_PALtemp17: 315 case AlphaISA::IPR_PALtemp18: 316 case AlphaISA::IPR_PALtemp19: 317 case AlphaISA::IPR_PALtemp20: 318 case AlphaISA::IPR_PALtemp21: 319 case AlphaISA::IPR_PALtemp22: 320 case AlphaISA::IPR_PAL_BASE: 321 case AlphaISA::IPR_IC_PERR_STAT: 322 case AlphaISA::IPR_DC_PERR_STAT: 323 case AlphaISA::IPR_PMCTR: 324 // write entire quad w/ no side-effect 325 ipr[idx] = val; 326 break; 327 328 case AlphaISA::IPR_CC_CTL: 329 // This IPR resets the cycle counter. We assume this only 330 // happens once... let's verify that. 331 assert(ipr[idx] == 0); 332 ipr[idx] = 1; 333 break; 334 335 case AlphaISA::IPR_CC: 336 // This IPR only writes the upper 64 bits. It's ok to write 337 // all 64 here since we mask out the lower 32 in rpcc (see 338 // isa_desc). 339 ipr[idx] = val; 340 break; 341 342 case AlphaISA::IPR_PALtemp23: 343 // write entire quad w/ no side-effect 344 old = ipr[idx]; 345 ipr[idx] = val; 346#if FULL_SYSTEM 347 if (tc->getKernelStats()) 348 tc->getKernelStats()->context(old, val, tc); 349#endif 350 break; 351 352 case AlphaISA::IPR_DTB_PTE: 353 // write entire quad w/ no side-effect, tag is forthcoming 354 ipr[idx] = val; 355 break; 356 357 case AlphaISA::IPR_EXC_ADDR: 358 // second least significant bit in PC is always zero 359 ipr[idx] = val & ~2; 360 break; 361 362 case AlphaISA::IPR_ASTRR: 363 case AlphaISA::IPR_ASTER: 364 // only write least significant four bits - privilege mask 365 ipr[idx] = val & 0xf; 366 break; 367 368 case AlphaISA::IPR_IPLR: 369#ifdef DEBUG 370 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 371 debug_break(); 372#endif 373 374 // only write least significant five bits - interrupt level 375 ipr[idx] = val & 0x1f; 376#if FULL_SYSTEM 377 if (tc->getKernelStats()) 378 tc->getKernelStats()->swpipl(ipr[idx]); 379#endif 380 break; 381 382 case AlphaISA::IPR_DTB_CM: 383#if FULL_SYSTEM 384 if (val & 0x18) { 385 if (tc->getKernelStats()) 386 tc->getKernelStats()->mode(TheISA::Kernel::user, tc); 387 } else { 388 if (tc->getKernelStats()) 389 tc->getKernelStats()->mode(TheISA::Kernel::kernel, tc); 390 } 391#endif 392 393 case AlphaISA::IPR_ICM: 394 // only write two mode bits - processor mode 395 ipr[idx] = val & 0x18; 396 break; 397 398 case AlphaISA::IPR_ALT_MODE: 399 // only write two mode bits - processor mode 400 ipr[idx] = val & 0x18; 401 break; 402 403 case AlphaISA::IPR_MCSR: 404 // more here after optimization... 405 ipr[idx] = val; 406 break; 407 408 case AlphaISA::IPR_SIRR: 409 // only write software interrupt mask 410 ipr[idx] = val & 0x7fff0; 411 break; 412 413 case AlphaISA::IPR_ICSR: 414 ipr[idx] = val & ULL(0xffffff0300); 415 break; 416 417 case AlphaISA::IPR_IVPTBR: 418 case AlphaISA::IPR_MVPTBR: 419 ipr[idx] = val & ULL(0xffffffffc0000000); 420 break; 421 422 case AlphaISA::IPR_DC_TEST_CTL: 423 ipr[idx] = val & 0x1ffb; 424 break; 425 426 case AlphaISA::IPR_DC_MODE: 427 case AlphaISA::IPR_MAF_MODE: 428 ipr[idx] = val & 0x3f; 429 break; 430 431 case AlphaISA::IPR_ITB_ASN: 432 ipr[idx] = val & 0x7f0; 433 break; 434 435 case AlphaISA::IPR_DTB_ASN: 436 ipr[idx] = val & ULL(0xfe00000000000000); 437 break; 438 439 case AlphaISA::IPR_EXC_SUM: 440 case AlphaISA::IPR_EXC_MASK: 441 // any write to this register clears it 442 ipr[idx] = 0; 443 break; 444 445 case AlphaISA::IPR_INTID: 446 case AlphaISA::IPR_SL_RCV: 447 case AlphaISA::IPR_MM_STAT: 448 case AlphaISA::IPR_ITB_PTE_TEMP: 449 case AlphaISA::IPR_DTB_PTE_TEMP: 450 // read-only registers 451 panic("Tried to write read only ipr %d\n", idx); 452 453 case AlphaISA::IPR_HWINT_CLR: 454 case AlphaISA::IPR_SL_XMIT: 455 case AlphaISA::IPR_DC_FLUSH: 456 case AlphaISA::IPR_IC_FLUSH: 457 // the following are write only 458 ipr[idx] = val; 459 break; 460 461 case AlphaISA::IPR_DTB_IA: 462 // really a control write 463 ipr[idx] = 0; 464 465 tc->getDTBPtr()->flushAll(); 466 break; 467 468 case AlphaISA::IPR_DTB_IAP: 469 // really a control write 470 ipr[idx] = 0; 471 472 tc->getDTBPtr()->flushProcesses(); 473 break; 474 475 case AlphaISA::IPR_DTB_IS: 476 // really a control write 477 ipr[idx] = val; 478 479 tc->getDTBPtr()->flushAddr(val, 480 AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 481 break; 482 483 case AlphaISA::IPR_DTB_TAG: { 484 struct AlphaISA::TlbEntry entry; 485 486 // FIXME: granularity hints NYI... 487 if (AlphaISA::DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 488 panic("PTE GH field != 0"); 489 490 // write entire quad 491 ipr[idx] = val; 492 493 // construct PTE for new entry 494 entry.ppn = AlphaISA::DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 495 entry.xre = AlphaISA::DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 496 entry.xwe = AlphaISA::DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 497 entry.fonr = AlphaISA::DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 498 entry.fonw = AlphaISA::DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 499 entry.asma = AlphaISA::DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 500 entry.asn = AlphaISA::DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 501 502 // insert new TAG/PTE value into data TLB 503 tc->getDTBPtr()->insert(val, entry); 504 } 505 break; 506 507 case AlphaISA::IPR_ITB_PTE: { 508 struct AlphaISA::TlbEntry entry; 509 510 // FIXME: granularity hints NYI... 511 if (AlphaISA::ITB_PTE_GH(val) != 0) 512 panic("PTE GH field != 0"); 513 514 // write entire quad 515 ipr[idx] = val; 516 517 // construct PTE for new entry 518 entry.ppn = AlphaISA::ITB_PTE_PPN(val); 519 entry.xre = AlphaISA::ITB_PTE_XRE(val); 520 entry.xwe = 0; 521 entry.fonr = AlphaISA::ITB_PTE_FONR(val); 522 entry.fonw = AlphaISA::ITB_PTE_FONW(val); 523 entry.asma = AlphaISA::ITB_PTE_ASMA(val); 524 entry.asn = AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 525 526 // insert new TAG/PTE value into data TLB 527 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], entry); 528 } 529 break; 530 531 case AlphaISA::IPR_ITB_IA: 532 // really a control write 533 ipr[idx] = 0; 534 535 tc->getITBPtr()->flushAll(); 536 break; 537 538 case AlphaISA::IPR_ITB_IAP: 539 // really a control write 540 ipr[idx] = 0; 541 542 tc->getITBPtr()->flushProcesses(); 543 break; 544 545 case AlphaISA::IPR_ITB_IS: 546 // really a control write 547 ipr[idx] = val; 548 549 tc->getITBPtr()->flushAddr(val, 550 AlphaISA::ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 551 break; 552 553 default: 554 // invalid IPR 555 panic("Tried to write to invalid ipr %d\n", idx); 556 } 557 558 // no error... 559} 560 561 562void 563AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) 564{ 565 for (int i = 0; i < NumInternalProcRegs; ++i) { 566 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 567 } 568} 569 570#if FULL_SYSTEM 571 572/** 573 * Check for special simulator handling of specific PAL calls. 574 * If return value is false, actual PAL call will be suppressed. 575 */ 576bool 577SimpleThread::simPalCheck(int palFunc) 578{ 579 if (kernelStats) 580 kernelStats->callpal(palFunc, tc); 581 582 switch (palFunc) { 583 case PAL::halt: 584 halt(); 585 if (--System::numSystemsRunning == 0) 586 exitSimLoop("all cpus halted"); 587 break; 588 589 case PAL::bpt: 590 case PAL::bugchk: 591 if (system->breakpoint()) 592 return false; 593 break; 594 } 595 596 return true; 597} 598 599#endif // FULL_SYSTEM 600