ev5.cc revision 3536:89aa06409e4d
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292SN/A * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include "arch/alpha/faults.hh" 336214Snate@binkert.org#include "arch/alpha/isa_traits.hh" 342SN/A#include "arch/alpha/osfpal.hh" 352SN/A#include "arch/alpha/tlb.hh" 362SN/A#include "arch/alpha/kgdb.h" 376214Snate@binkert.org#include "base/remote_gdb.hh" 386214Snate@binkert.org#include "base/stats/events.hh" 392SN/A#include "config/full_system.hh" 402SN/A#include "cpu/base.hh" 412SN/A#include "cpu/simple_thread.hh" 429180Sandreas.hansson@arm.com#include "cpu/thread_context.hh" 4310474Sandreas.hansson@arm.com#include "kern/kernel_stats.hh" 449500Snilay@cs.wisc.edu#include "sim/debug.hh" 459180Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 4610276SAndreas.Sandberg@ARM.com 4710276SAndreas.Sandberg@ARM.com#if FULL_SYSTEM 482SN/A 495543SN/Ausing namespace EV5; 502SN/A 515543SN/A//////////////////////////////////////////////////////////////////////// 522SN/A// 532SN/A// Machine dependent functions 542SN/A// 552SN/Avoid 562SN/AAlphaISA::initCPU(ThreadContext *tc, int cpuId) 572SN/A{ 582SN/A initIPRs(tc, cpuId); 592SN/A 609158Sandreas.hansson@arm.com tc->setIntReg(16, cpuId); 612SN/A tc->setIntReg(0, cpuId); 629158Sandreas.hansson@arm.com 632SN/A AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault; 649158Sandreas.hansson@arm.com 652667SN/A tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect()); 662130SN/A tc->setNextPC(tc->readPC() + sizeof(MachInst)); 679180Sandreas.hansson@arm.com 689180Sandreas.hansson@arm.com delete reset; 699180Sandreas.hansson@arm.com} 709180Sandreas.hansson@arm.com 719180Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////////// 729180Sandreas.hansson@arm.com// 739180Sandreas.hansson@arm.com// 749180Sandreas.hansson@arm.com// 759180Sandreas.hansson@arm.comvoid 769180Sandreas.hansson@arm.comAlphaISA::initIPRs(ThreadContext *tc, int cpuId) 779180Sandreas.hansson@arm.com{ 789180Sandreas.hansson@arm.com for (int i = 0; i < NumInternalProcRegs; ++i) { 799180Sandreas.hansson@arm.com tc->setMiscReg(i, 0); 809180Sandreas.hansson@arm.com } 819180Sandreas.hansson@arm.com 829180Sandreas.hansson@arm.com tc->setMiscReg(IPR_PAL_BASE, PalBase); 839180Sandreas.hansson@arm.com tc->setMiscReg(IPR_MCSR, 0x6); 849180Sandreas.hansson@arm.com tc->setMiscReg(IPR_PALtemp16, cpuId); 859180Sandreas.hansson@arm.com} 869180Sandreas.hansson@arm.com 879180Sandreas.hansson@arm.com 889180Sandreas.hansson@arm.comtemplate <class CPU> 899180Sandreas.hansson@arm.comvoid 909180Sandreas.hansson@arm.comAlphaISA::processInterrupts(CPU *cpu) 919180Sandreas.hansson@arm.com{ 929180Sandreas.hansson@arm.com //Check if there are any outstanding interrupts 939180Sandreas.hansson@arm.com //Handle the interrupts 949180Sandreas.hansson@arm.com int ipl = 0; 959180Sandreas.hansson@arm.com int summary = 0; 969184Sandreas.hansson@arm.com 979184Sandreas.hansson@arm.com cpu->checkInterrupts = false; 989184Sandreas.hansson@arm.com 999180Sandreas.hansson@arm.com if (cpu->readMiscReg(IPR_ASTRR)) 1009180Sandreas.hansson@arm.com panic("asynchronous traps not implemented\n"); 1019180Sandreas.hansson@arm.com 1029180Sandreas.hansson@arm.com if (cpu->readMiscReg(IPR_SIRR)) { 1039180Sandreas.hansson@arm.com for (int i = INTLEVEL_SOFTWARE_MIN; 1049180Sandreas.hansson@arm.com i < INTLEVEL_SOFTWARE_MAX; i++) { 1059180Sandreas.hansson@arm.com if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 1069180Sandreas.hansson@arm.com // See table 4-19 of the 21164 hardware reference 1079180Sandreas.hansson@arm.com ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 1089180Sandreas.hansson@arm.com summary |= (ULL(1) << i); 1099180Sandreas.hansson@arm.com } 1109180Sandreas.hansson@arm.com } 1119180Sandreas.hansson@arm.com } 1129180Sandreas.hansson@arm.com 1139180Sandreas.hansson@arm.com uint64_t interrupts = cpu->intr_status(); 1149180Sandreas.hansson@arm.com 1159180Sandreas.hansson@arm.com if (interrupts) { 1169180Sandreas.hansson@arm.com for (int i = INTLEVEL_EXTERNAL_MIN; 1179180Sandreas.hansson@arm.com i < INTLEVEL_EXTERNAL_MAX; i++) { 1189180Sandreas.hansson@arm.com if (interrupts & (ULL(1) << i)) { 1199180Sandreas.hansson@arm.com // See table 4-19 of the 21164 hardware reference 1209498Snilay@cs.wisc.edu ipl = i; 1219498Snilay@cs.wisc.edu summary |= (ULL(1) << i); 1229498Snilay@cs.wisc.edu } 1239498Snilay@cs.wisc.edu } 1249498Snilay@cs.wisc.edu } 1259498Snilay@cs.wisc.edu 1269498Snilay@cs.wisc.edu if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { 1279498Snilay@cs.wisc.edu cpu->setMiscReg(IPR_ISR, summary); 1289498Snilay@cs.wisc.edu cpu->setMiscReg(IPR_INTID, ipl); 1299498Snilay@cs.wisc.edu cpu->trap(new InterruptFault); 1309498Snilay@cs.wisc.edu DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 1319498Snilay@cs.wisc.edu cpu->readMiscReg(IPR_IPLR), ipl, summary); 1329500Snilay@cs.wisc.edu } 1339500Snilay@cs.wisc.edu 1349180Sandreas.hansson@arm.com} 1359180Sandreas.hansson@arm.com 1369180Sandreas.hansson@arm.comtemplate <class CPU> 1379180Sandreas.hansson@arm.comvoid 1389180Sandreas.hansson@arm.comAlphaISA::zeroRegisters(CPU *cpu) 1392130SN/A{ 1402130SN/A // Insure ISA semantics 1412130SN/A // (no longer very clean due to the change in setIntReg() in the 1422130SN/A // cpu model. Consider changing later.) 1432130SN/A cpu->thread->setIntReg(ZeroReg, 0); 1442130SN/A cpu->thread->setFloatReg(ZeroReg, 0.0); 1452130SN/A} 1467720Sgblack@eecs.umich.edu 1477720Sgblack@eecs.umich.eduFault 1487720Sgblack@eecs.umich.eduSimpleThread::hwrei() 1497720Sgblack@eecs.umich.edu{ 1507720Sgblack@eecs.umich.edu if (!(readPC() & 0x3)) 1517720Sgblack@eecs.umich.edu return new UnimplementedOpcodeFault; 1527720Sgblack@eecs.umich.edu 1537720Sgblack@eecs.umich.edu setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); 1547720Sgblack@eecs.umich.edu 1557720Sgblack@eecs.umich.edu if (!misspeculating()) { 1567720Sgblack@eecs.umich.edu if (kernelStats) 1577720Sgblack@eecs.umich.edu kernelStats->hwrei(); 1587720Sgblack@eecs.umich.edu 1597720Sgblack@eecs.umich.edu cpu->checkInterrupts = true; 1607720Sgblack@eecs.umich.edu } 1617720Sgblack@eecs.umich.edu 1627720Sgblack@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 1637720Sgblack@eecs.umich.edu return NoFault; 1647720Sgblack@eecs.umich.edu} 1657720Sgblack@eecs.umich.edu 1667720Sgblack@eecs.umich.eduint 1677720Sgblack@eecs.umich.eduAlphaISA::MiscRegFile::getInstAsid() 1682438SN/A{ 1692438SN/A return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 1706221Snate@binkert.org} 1716221Snate@binkert.org 1726221Snate@binkert.orgint 1736221Snate@binkert.orgAlphaISA::MiscRegFile::getDataAsid() 1746221Snate@binkert.org{ 1756221Snate@binkert.org return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 1769031Sandreas.hansson@arm.com} 1779031Sandreas.hansson@arm.com 1789031Sandreas.hansson@arm.comAlphaISA::MiscReg 1799031Sandreas.hansson@arm.comAlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc) 1809031Sandreas.hansson@arm.com{ 1819031Sandreas.hansson@arm.com uint64_t retval = 0; // return value, default 0 1827678Sgblack@eecs.umich.edu 18310474Sandreas.hansson@arm.com switch (idx) { 18410474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp0: 18510474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp1: 18610474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp2: 18710474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp3: 18810474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp4: 18910474Sandreas.hansson@arm.com case AlphaISA::IPR_PALtemp5: 1907678Sgblack@eecs.umich.edu case AlphaISA::IPR_PALtemp6: 19110839Sandreas.sandberg@arm.com case AlphaISA::IPR_PALtemp7: 19210839Sandreas.sandberg@arm.com case AlphaISA::IPR_PALtemp8: 19310839Sandreas.sandberg@arm.com case AlphaISA::IPR_PALtemp9: 19410839Sandreas.sandberg@arm.com case AlphaISA::IPR_PALtemp10: 19510839Sandreas.sandberg@arm.com case AlphaISA::IPR_PALtemp11: 1966214Snate@binkert.org case AlphaISA::IPR_PALtemp12: 197 case AlphaISA::IPR_PALtemp13: 198 case AlphaISA::IPR_PALtemp14: 199 case AlphaISA::IPR_PALtemp15: 200 case AlphaISA::IPR_PALtemp16: 201 case AlphaISA::IPR_PALtemp17: 202 case AlphaISA::IPR_PALtemp18: 203 case AlphaISA::IPR_PALtemp19: 204 case AlphaISA::IPR_PALtemp20: 205 case AlphaISA::IPR_PALtemp21: 206 case AlphaISA::IPR_PALtemp22: 207 case AlphaISA::IPR_PALtemp23: 208 case AlphaISA::IPR_PAL_BASE: 209 210 case AlphaISA::IPR_IVPTBR: 211 case AlphaISA::IPR_DC_MODE: 212 case AlphaISA::IPR_MAF_MODE: 213 case AlphaISA::IPR_ISR: 214 case AlphaISA::IPR_EXC_ADDR: 215 case AlphaISA::IPR_IC_PERR_STAT: 216 case AlphaISA::IPR_DC_PERR_STAT: 217 case AlphaISA::IPR_MCSR: 218 case AlphaISA::IPR_ASTRR: 219 case AlphaISA::IPR_ASTER: 220 case AlphaISA::IPR_SIRR: 221 case AlphaISA::IPR_ICSR: 222 case AlphaISA::IPR_ICM: 223 case AlphaISA::IPR_DTB_CM: 224 case AlphaISA::IPR_IPLR: 225 case AlphaISA::IPR_INTID: 226 case AlphaISA::IPR_PMCTR: 227 // no side-effect 228 retval = ipr[idx]; 229 break; 230 231 case AlphaISA::IPR_CC: 232 retval |= ipr[idx] & ULL(0xffffffff00000000); 233 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 234 break; 235 236 case AlphaISA::IPR_VA: 237 retval = ipr[idx]; 238 break; 239 240 case AlphaISA::IPR_VA_FORM: 241 case AlphaISA::IPR_MM_STAT: 242 case AlphaISA::IPR_IFAULT_VA_FORM: 243 case AlphaISA::IPR_EXC_MASK: 244 case AlphaISA::IPR_EXC_SUM: 245 retval = ipr[idx]; 246 break; 247 248 case AlphaISA::IPR_DTB_PTE: 249 { 250 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); 251 252 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 253 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 254 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 255 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 256 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 257 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 258 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 259 } 260 break; 261 262 // write only registers 263 case AlphaISA::IPR_HWINT_CLR: 264 case AlphaISA::IPR_SL_XMIT: 265 case AlphaISA::IPR_DC_FLUSH: 266 case AlphaISA::IPR_IC_FLUSH: 267 case AlphaISA::IPR_ALT_MODE: 268 case AlphaISA::IPR_DTB_IA: 269 case AlphaISA::IPR_DTB_IAP: 270 case AlphaISA::IPR_ITB_IA: 271 case AlphaISA::IPR_ITB_IAP: 272 panic("Tried to read write only register %d\n", idx); 273 break; 274 275 default: 276 // invalid IPR 277 panic("Tried to read from invalid ipr %d\n", idx); 278 break; 279 } 280 281 return retval; 282} 283 284#ifdef DEBUG 285// Cause the simulator to break when changing to the following IPL 286int break_ipl = -1; 287#endif 288 289void 290AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) 291{ 292 uint64_t old; 293 294 if (tc->misspeculating()) 295 return; 296 297 switch (idx) { 298 case AlphaISA::IPR_PALtemp0: 299 case AlphaISA::IPR_PALtemp1: 300 case AlphaISA::IPR_PALtemp2: 301 case AlphaISA::IPR_PALtemp3: 302 case AlphaISA::IPR_PALtemp4: 303 case AlphaISA::IPR_PALtemp5: 304 case AlphaISA::IPR_PALtemp6: 305 case AlphaISA::IPR_PALtemp7: 306 case AlphaISA::IPR_PALtemp8: 307 case AlphaISA::IPR_PALtemp9: 308 case AlphaISA::IPR_PALtemp10: 309 case AlphaISA::IPR_PALtemp11: 310 case AlphaISA::IPR_PALtemp12: 311 case AlphaISA::IPR_PALtemp13: 312 case AlphaISA::IPR_PALtemp14: 313 case AlphaISA::IPR_PALtemp15: 314 case AlphaISA::IPR_PALtemp16: 315 case AlphaISA::IPR_PALtemp17: 316 case AlphaISA::IPR_PALtemp18: 317 case AlphaISA::IPR_PALtemp19: 318 case AlphaISA::IPR_PALtemp20: 319 case AlphaISA::IPR_PALtemp21: 320 case AlphaISA::IPR_PALtemp22: 321 case AlphaISA::IPR_PAL_BASE: 322 case AlphaISA::IPR_IC_PERR_STAT: 323 case AlphaISA::IPR_DC_PERR_STAT: 324 case AlphaISA::IPR_PMCTR: 325 // write entire quad w/ no side-effect 326 ipr[idx] = val; 327 break; 328 329 case AlphaISA::IPR_CC_CTL: 330 // This IPR resets the cycle counter. We assume this only 331 // happens once... let's verify that. 332 assert(ipr[idx] == 0); 333 ipr[idx] = 1; 334 break; 335 336 case AlphaISA::IPR_CC: 337 // This IPR only writes the upper 64 bits. It's ok to write 338 // all 64 here since we mask out the lower 32 in rpcc (see 339 // isa_desc). 340 ipr[idx] = val; 341 break; 342 343 case AlphaISA::IPR_PALtemp23: 344 // write entire quad w/ no side-effect 345 old = ipr[idx]; 346 ipr[idx] = val; 347 if (tc->getKernelStats()) 348 tc->getKernelStats()->context(old, val, tc); 349 break; 350 351 case AlphaISA::IPR_DTB_PTE: 352 // write entire quad w/ no side-effect, tag is forthcoming 353 ipr[idx] = val; 354 break; 355 356 case AlphaISA::IPR_EXC_ADDR: 357 // second least significant bit in PC is always zero 358 ipr[idx] = val & ~2; 359 break; 360 361 case AlphaISA::IPR_ASTRR: 362 case AlphaISA::IPR_ASTER: 363 // only write least significant four bits - privilege mask 364 ipr[idx] = val & 0xf; 365 break; 366 367 case AlphaISA::IPR_IPLR: 368#ifdef DEBUG 369 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 370 debug_break(); 371#endif 372 373 // only write least significant five bits - interrupt level 374 ipr[idx] = val & 0x1f; 375 if (tc->getKernelStats()) 376 tc->getKernelStats()->swpipl(ipr[idx]); 377 break; 378 379 case AlphaISA::IPR_DTB_CM: 380 if (val & 0x18) { 381 if (tc->getKernelStats()) 382 tc->getKernelStats()->mode(Kernel::user, tc); 383 } else { 384 if (tc->getKernelStats()) 385 tc->getKernelStats()->mode(Kernel::kernel, tc); 386 } 387 388 case AlphaISA::IPR_ICM: 389 // only write two mode bits - processor mode 390 ipr[idx] = val & 0x18; 391 break; 392 393 case AlphaISA::IPR_ALT_MODE: 394 // only write two mode bits - processor mode 395 ipr[idx] = val & 0x18; 396 break; 397 398 case AlphaISA::IPR_MCSR: 399 // more here after optimization... 400 ipr[idx] = val; 401 break; 402 403 case AlphaISA::IPR_SIRR: 404 // only write software interrupt mask 405 ipr[idx] = val & 0x7fff0; 406 break; 407 408 case AlphaISA::IPR_ICSR: 409 ipr[idx] = val & ULL(0xffffff0300); 410 break; 411 412 case AlphaISA::IPR_IVPTBR: 413 case AlphaISA::IPR_MVPTBR: 414 ipr[idx] = val & ULL(0xffffffffc0000000); 415 break; 416 417 case AlphaISA::IPR_DC_TEST_CTL: 418 ipr[idx] = val & 0x1ffb; 419 break; 420 421 case AlphaISA::IPR_DC_MODE: 422 case AlphaISA::IPR_MAF_MODE: 423 ipr[idx] = val & 0x3f; 424 break; 425 426 case AlphaISA::IPR_ITB_ASN: 427 ipr[idx] = val & 0x7f0; 428 break; 429 430 case AlphaISA::IPR_DTB_ASN: 431 ipr[idx] = val & ULL(0xfe00000000000000); 432 break; 433 434 case AlphaISA::IPR_EXC_SUM: 435 case AlphaISA::IPR_EXC_MASK: 436 // any write to this register clears it 437 ipr[idx] = 0; 438 break; 439 440 case AlphaISA::IPR_INTID: 441 case AlphaISA::IPR_SL_RCV: 442 case AlphaISA::IPR_MM_STAT: 443 case AlphaISA::IPR_ITB_PTE_TEMP: 444 case AlphaISA::IPR_DTB_PTE_TEMP: 445 // read-only registers 446 panic("Tried to write read only ipr %d\n", idx); 447 448 case AlphaISA::IPR_HWINT_CLR: 449 case AlphaISA::IPR_SL_XMIT: 450 case AlphaISA::IPR_DC_FLUSH: 451 case AlphaISA::IPR_IC_FLUSH: 452 // the following are write only 453 ipr[idx] = val; 454 break; 455 456 case AlphaISA::IPR_DTB_IA: 457 // really a control write 458 ipr[idx] = 0; 459 460 tc->getDTBPtr()->flushAll(); 461 break; 462 463 case AlphaISA::IPR_DTB_IAP: 464 // really a control write 465 ipr[idx] = 0; 466 467 tc->getDTBPtr()->flushProcesses(); 468 break; 469 470 case AlphaISA::IPR_DTB_IS: 471 // really a control write 472 ipr[idx] = val; 473 474 tc->getDTBPtr()->flushAddr(val, 475 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 476 break; 477 478 case AlphaISA::IPR_DTB_TAG: { 479 struct AlphaISA::PTE pte; 480 481 // FIXME: granularity hints NYI... 482 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 483 panic("PTE GH field != 0"); 484 485 // write entire quad 486 ipr[idx] = val; 487 488 // construct PTE for new entry 489 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 490 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 491 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 492 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 493 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 494 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 495 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 496 497 // insert new TAG/PTE value into data TLB 498 tc->getDTBPtr()->insert(val, pte); 499 } 500 break; 501 502 case AlphaISA::IPR_ITB_PTE: { 503 struct AlphaISA::PTE pte; 504 505 // FIXME: granularity hints NYI... 506 if (ITB_PTE_GH(val) != 0) 507 panic("PTE GH field != 0"); 508 509 // write entire quad 510 ipr[idx] = val; 511 512 // construct PTE for new entry 513 pte.ppn = ITB_PTE_PPN(val); 514 pte.xre = ITB_PTE_XRE(val); 515 pte.xwe = 0; 516 pte.fonr = ITB_PTE_FONR(val); 517 pte.fonw = ITB_PTE_FONW(val); 518 pte.asma = ITB_PTE_ASMA(val); 519 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 520 521 // insert new TAG/PTE value into data TLB 522 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 523 } 524 break; 525 526 case AlphaISA::IPR_ITB_IA: 527 // really a control write 528 ipr[idx] = 0; 529 530 tc->getITBPtr()->flushAll(); 531 break; 532 533 case AlphaISA::IPR_ITB_IAP: 534 // really a control write 535 ipr[idx] = 0; 536 537 tc->getITBPtr()->flushProcesses(); 538 break; 539 540 case AlphaISA::IPR_ITB_IS: 541 // really a control write 542 ipr[idx] = val; 543 544 tc->getITBPtr()->flushAddr(val, 545 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 546 break; 547 548 default: 549 // invalid IPR 550 panic("Tried to write to invalid ipr %d\n", idx); 551 } 552 553 // no error... 554} 555 556 557void 558AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) 559{ 560 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { 561 dest->setMiscReg(i, src->readMiscReg(i)); 562 } 563} 564 565 566/** 567 * Check for special simulator handling of specific PAL calls. 568 * If return value is false, actual PAL call will be suppressed. 569 */ 570bool 571SimpleThread::simPalCheck(int palFunc) 572{ 573 if (kernelStats) 574 kernelStats->callpal(palFunc, tc); 575 576 switch (palFunc) { 577 case PAL::halt: 578 halt(); 579 if (--System::numSystemsRunning == 0) 580 exitSimLoop("all cpus halted"); 581 break; 582 583 case PAL::bpt: 584 case PAL::bugchk: 585 if (system->breakpoint()) 586 return false; 587 break; 588 } 589 590 return true; 591} 592 593#endif // FULL_SYSTEM 594