ev5.cc revision 3125:febd811bccc6 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/osfpal.hh"
35#include "arch/alpha/tlb.hh"
36#include "base/kgdb.h"
37#include "base/remote_gdb.hh"
38#include "base/stats/events.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/simple_thread.hh"
42#include "cpu/thread_context.hh"
43#include "kern/kernel_stats.hh"
44#include "sim/debug.hh"
45#include "sim/sim_exit.hh"
46
47#if FULL_SYSTEM
48
49using namespace EV5;
50
51////////////////////////////////////////////////////////////////////////
52//
53//  Machine dependent functions
54//
55void
56AlphaISA::initCPU(ThreadContext *tc, int cpuId)
57{
58    initIPRs(tc, cpuId);
59
60    tc->setIntReg(16, cpuId);
61    tc->setIntReg(0, cpuId);
62
63    AlphaFault *reset = new ResetFault;
64
65    tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
66    tc->setNextPC(tc->readPC() + sizeof(MachInst));
67
68    delete reset;
69}
70
71////////////////////////////////////////////////////////////////////////
72//
73//
74//
75void
76AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
77{
78    for (int i = 0; i < NumInternalProcRegs; ++i) {
79        tc->setMiscReg(i, 0);
80    }
81
82    tc->setMiscReg(IPR_PAL_BASE, PalBase);
83    tc->setMiscReg(IPR_MCSR, 0x6);
84    tc->setMiscReg(IPR_PALtemp16, cpuId);
85}
86
87
88template <class CPU>
89void
90AlphaISA::processInterrupts(CPU *cpu)
91{
92    //Check if there are any outstanding interrupts
93    //Handle the interrupts
94    int ipl = 0;
95    int summary = 0;
96
97    cpu->checkInterrupts = false;
98
99    if (cpu->readMiscReg(IPR_ASTRR))
100        panic("asynchronous traps not implemented\n");
101
102    if (cpu->readMiscReg(IPR_SIRR)) {
103        for (int i = INTLEVEL_SOFTWARE_MIN;
104             i < INTLEVEL_SOFTWARE_MAX; i++) {
105            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
106                // See table 4-19 of the 21164 hardware reference
107                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
108                summary |= (ULL(1) << i);
109            }
110        }
111    }
112
113    uint64_t interrupts = cpu->intr_status();
114
115    if (interrupts) {
116        for (int i = INTLEVEL_EXTERNAL_MIN;
117             i < INTLEVEL_EXTERNAL_MAX; i++) {
118            if (interrupts & (ULL(1) << i)) {
119                // See table 4-19 of the 21164 hardware reference
120                ipl = i;
121                summary |= (ULL(1) << i);
122            }
123        }
124    }
125
126    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
127        cpu->setMiscReg(IPR_ISR, summary);
128        cpu->setMiscReg(IPR_INTID, ipl);
129        cpu->trap(new InterruptFault);
130        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
131                cpu->readMiscReg(IPR_IPLR), ipl, summary);
132    }
133
134}
135
136template <class CPU>
137void
138AlphaISA::zeroRegisters(CPU *cpu)
139{
140    // Insure ISA semantics
141    // (no longer very clean due to the change in setIntReg() in the
142    // cpu model.  Consider changing later.)
143    cpu->thread->setIntReg(ZeroReg, 0);
144    cpu->thread->setFloatReg(ZeroReg, 0.0);
145}
146
147Fault
148SimpleThread::hwrei()
149{
150    if (!inPalMode())
151        return new UnimplementedOpcodeFault;
152
153    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
154
155    if (!misspeculating()) {
156        if (kernelStats)
157            kernelStats->hwrei();
158
159        cpu->checkInterrupts = true;
160    }
161
162    // FIXME: XXX check for interrupts? XXX
163    return NoFault;
164}
165
166int
167AlphaISA::MiscRegFile::getInstAsid()
168{
169    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
170}
171
172int
173AlphaISA::MiscRegFile::getDataAsid()
174{
175    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
176}
177
178AlphaISA::MiscReg
179AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
180{
181    uint64_t retval = 0;	// return value, default 0
182
183    switch (idx) {
184      case AlphaISA::IPR_PALtemp0:
185      case AlphaISA::IPR_PALtemp1:
186      case AlphaISA::IPR_PALtemp2:
187      case AlphaISA::IPR_PALtemp3:
188      case AlphaISA::IPR_PALtemp4:
189      case AlphaISA::IPR_PALtemp5:
190      case AlphaISA::IPR_PALtemp6:
191      case AlphaISA::IPR_PALtemp7:
192      case AlphaISA::IPR_PALtemp8:
193      case AlphaISA::IPR_PALtemp9:
194      case AlphaISA::IPR_PALtemp10:
195      case AlphaISA::IPR_PALtemp11:
196      case AlphaISA::IPR_PALtemp12:
197      case AlphaISA::IPR_PALtemp13:
198      case AlphaISA::IPR_PALtemp14:
199      case AlphaISA::IPR_PALtemp15:
200      case AlphaISA::IPR_PALtemp16:
201      case AlphaISA::IPR_PALtemp17:
202      case AlphaISA::IPR_PALtemp18:
203      case AlphaISA::IPR_PALtemp19:
204      case AlphaISA::IPR_PALtemp20:
205      case AlphaISA::IPR_PALtemp21:
206      case AlphaISA::IPR_PALtemp22:
207      case AlphaISA::IPR_PALtemp23:
208      case AlphaISA::IPR_PAL_BASE:
209
210      case AlphaISA::IPR_IVPTBR:
211      case AlphaISA::IPR_DC_MODE:
212      case AlphaISA::IPR_MAF_MODE:
213      case AlphaISA::IPR_ISR:
214      case AlphaISA::IPR_EXC_ADDR:
215      case AlphaISA::IPR_IC_PERR_STAT:
216      case AlphaISA::IPR_DC_PERR_STAT:
217      case AlphaISA::IPR_MCSR:
218      case AlphaISA::IPR_ASTRR:
219      case AlphaISA::IPR_ASTER:
220      case AlphaISA::IPR_SIRR:
221      case AlphaISA::IPR_ICSR:
222      case AlphaISA::IPR_ICM:
223      case AlphaISA::IPR_DTB_CM:
224      case AlphaISA::IPR_IPLR:
225      case AlphaISA::IPR_INTID:
226      case AlphaISA::IPR_PMCTR:
227        // no side-effect
228        retval = ipr[idx];
229        break;
230
231      case AlphaISA::IPR_CC:
232        retval |= ipr[idx] & ULL(0xffffffff00000000);
233        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
234        break;
235
236      case AlphaISA::IPR_VA:
237        retval = ipr[idx];
238        break;
239
240      case AlphaISA::IPR_VA_FORM:
241      case AlphaISA::IPR_MM_STAT:
242      case AlphaISA::IPR_IFAULT_VA_FORM:
243      case AlphaISA::IPR_EXC_MASK:
244      case AlphaISA::IPR_EXC_SUM:
245        retval = ipr[idx];
246        break;
247
248      case AlphaISA::IPR_DTB_PTE:
249        {
250            AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
251
252            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
253            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
254            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
255            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
256            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
257            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
258            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
259        }
260        break;
261
262        // write only registers
263      case AlphaISA::IPR_HWINT_CLR:
264      case AlphaISA::IPR_SL_XMIT:
265      case AlphaISA::IPR_DC_FLUSH:
266      case AlphaISA::IPR_IC_FLUSH:
267      case AlphaISA::IPR_ALT_MODE:
268      case AlphaISA::IPR_DTB_IA:
269      case AlphaISA::IPR_DTB_IAP:
270      case AlphaISA::IPR_ITB_IA:
271      case AlphaISA::IPR_ITB_IAP:
272        fault = new UnimplementedOpcodeFault;
273        break;
274
275      default:
276        // invalid IPR
277        fault = new UnimplementedOpcodeFault;
278        break;
279    }
280
281    return retval;
282}
283
284#ifdef DEBUG
285// Cause the simulator to break when changing to the following IPL
286int break_ipl = -1;
287#endif
288
289Fault
290AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
291{
292    uint64_t old;
293
294    if (tc->misspeculating())
295        return NoFault;
296
297    switch (idx) {
298      case AlphaISA::IPR_PALtemp0:
299      case AlphaISA::IPR_PALtemp1:
300      case AlphaISA::IPR_PALtemp2:
301      case AlphaISA::IPR_PALtemp3:
302      case AlphaISA::IPR_PALtemp4:
303      case AlphaISA::IPR_PALtemp5:
304      case AlphaISA::IPR_PALtemp6:
305      case AlphaISA::IPR_PALtemp7:
306      case AlphaISA::IPR_PALtemp8:
307      case AlphaISA::IPR_PALtemp9:
308      case AlphaISA::IPR_PALtemp10:
309      case AlphaISA::IPR_PALtemp11:
310      case AlphaISA::IPR_PALtemp12:
311      case AlphaISA::IPR_PALtemp13:
312      case AlphaISA::IPR_PALtemp14:
313      case AlphaISA::IPR_PALtemp15:
314      case AlphaISA::IPR_PALtemp16:
315      case AlphaISA::IPR_PALtemp17:
316      case AlphaISA::IPR_PALtemp18:
317      case AlphaISA::IPR_PALtemp19:
318      case AlphaISA::IPR_PALtemp20:
319      case AlphaISA::IPR_PALtemp21:
320      case AlphaISA::IPR_PALtemp22:
321      case AlphaISA::IPR_PAL_BASE:
322      case AlphaISA::IPR_IC_PERR_STAT:
323      case AlphaISA::IPR_DC_PERR_STAT:
324      case AlphaISA::IPR_PMCTR:
325        // write entire quad w/ no side-effect
326        ipr[idx] = val;
327        break;
328
329      case AlphaISA::IPR_CC_CTL:
330        // This IPR resets the cycle counter.  We assume this only
331        // happens once... let's verify that.
332        assert(ipr[idx] == 0);
333        ipr[idx] = 1;
334        break;
335
336      case AlphaISA::IPR_CC:
337        // This IPR only writes the upper 64 bits.  It's ok to write
338        // all 64 here since we mask out the lower 32 in rpcc (see
339        // isa_desc).
340        ipr[idx] = val;
341        break;
342
343      case AlphaISA::IPR_PALtemp23:
344        // write entire quad w/ no side-effect
345        old = ipr[idx];
346        ipr[idx] = val;
347        if (tc->getKernelStats())
348            tc->getKernelStats()->context(old, val, tc);
349        break;
350
351      case AlphaISA::IPR_DTB_PTE:
352        // write entire quad w/ no side-effect, tag is forthcoming
353        ipr[idx] = val;
354        break;
355
356      case AlphaISA::IPR_EXC_ADDR:
357        // second least significant bit in PC is always zero
358        ipr[idx] = val & ~2;
359        break;
360
361      case AlphaISA::IPR_ASTRR:
362      case AlphaISA::IPR_ASTER:
363        // only write least significant four bits - privilege mask
364        ipr[idx] = val & 0xf;
365        break;
366
367      case AlphaISA::IPR_IPLR:
368#ifdef DEBUG
369        if (break_ipl != -1 && break_ipl == (val & 0x1f))
370            debug_break();
371#endif
372
373        // only write least significant five bits - interrupt level
374        ipr[idx] = val & 0x1f;
375        if (tc->getKernelStats())
376            tc->getKernelStats()->swpipl(ipr[idx]);
377        break;
378
379      case AlphaISA::IPR_DTB_CM:
380        if (val & 0x18) {
381            if (tc->getKernelStats())
382                tc->getKernelStats()->mode(Kernel::user, tc);
383        } else {
384            if (tc->getKernelStats())
385                tc->getKernelStats()->mode(Kernel::kernel, tc);
386        }
387
388      case AlphaISA::IPR_ICM:
389        // only write two mode bits - processor mode
390        ipr[idx] = val & 0x18;
391        break;
392
393      case AlphaISA::IPR_ALT_MODE:
394        // only write two mode bits - processor mode
395        ipr[idx] = val & 0x18;
396        break;
397
398      case AlphaISA::IPR_MCSR:
399        // more here after optimization...
400        ipr[idx] = val;
401        break;
402
403      case AlphaISA::IPR_SIRR:
404        // only write software interrupt mask
405        ipr[idx] = val & 0x7fff0;
406        break;
407
408      case AlphaISA::IPR_ICSR:
409        ipr[idx] = val & ULL(0xffffff0300);
410        break;
411
412      case AlphaISA::IPR_IVPTBR:
413      case AlphaISA::IPR_MVPTBR:
414        ipr[idx] = val & ULL(0xffffffffc0000000);
415        break;
416
417      case AlphaISA::IPR_DC_TEST_CTL:
418        ipr[idx] = val & 0x1ffb;
419        break;
420
421      case AlphaISA::IPR_DC_MODE:
422      case AlphaISA::IPR_MAF_MODE:
423        ipr[idx] = val & 0x3f;
424        break;
425
426      case AlphaISA::IPR_ITB_ASN:
427        ipr[idx] = val & 0x7f0;
428        break;
429
430      case AlphaISA::IPR_DTB_ASN:
431        ipr[idx] = val & ULL(0xfe00000000000000);
432        break;
433
434      case AlphaISA::IPR_EXC_SUM:
435      case AlphaISA::IPR_EXC_MASK:
436        // any write to this register clears it
437        ipr[idx] = 0;
438        break;
439
440      case AlphaISA::IPR_INTID:
441      case AlphaISA::IPR_SL_RCV:
442      case AlphaISA::IPR_MM_STAT:
443      case AlphaISA::IPR_ITB_PTE_TEMP:
444      case AlphaISA::IPR_DTB_PTE_TEMP:
445        // read-only registers
446        return new UnimplementedOpcodeFault;
447
448      case AlphaISA::IPR_HWINT_CLR:
449      case AlphaISA::IPR_SL_XMIT:
450      case AlphaISA::IPR_DC_FLUSH:
451      case AlphaISA::IPR_IC_FLUSH:
452        // the following are write only
453        ipr[idx] = val;
454        break;
455
456      case AlphaISA::IPR_DTB_IA:
457        // really a control write
458        ipr[idx] = 0;
459
460        tc->getDTBPtr()->flushAll();
461        break;
462
463      case AlphaISA::IPR_DTB_IAP:
464        // really a control write
465        ipr[idx] = 0;
466
467        tc->getDTBPtr()->flushProcesses();
468        break;
469
470      case AlphaISA::IPR_DTB_IS:
471        // really a control write
472        ipr[idx] = val;
473
474        tc->getDTBPtr()->flushAddr(val,
475                                   DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
476        break;
477
478      case AlphaISA::IPR_DTB_TAG: {
479          struct AlphaISA::PTE pte;
480
481          // FIXME: granularity hints NYI...
482          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
483              panic("PTE GH field != 0");
484
485          // write entire quad
486          ipr[idx] = val;
487
488          // construct PTE for new entry
489          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
490          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
491          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
492          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
493          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
494          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
495          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
496
497          // insert new TAG/PTE value into data TLB
498          tc->getDTBPtr()->insert(val, pte);
499      }
500        break;
501
502      case AlphaISA::IPR_ITB_PTE: {
503          struct AlphaISA::PTE pte;
504
505          // FIXME: granularity hints NYI...
506          if (ITB_PTE_GH(val) != 0)
507              panic("PTE GH field != 0");
508
509          // write entire quad
510          ipr[idx] = val;
511
512          // construct PTE for new entry
513          pte.ppn = ITB_PTE_PPN(val);
514          pte.xre = ITB_PTE_XRE(val);
515          pte.xwe = 0;
516          pte.fonr = ITB_PTE_FONR(val);
517          pte.fonw = ITB_PTE_FONW(val);
518          pte.asma = ITB_PTE_ASMA(val);
519          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
520
521          // insert new TAG/PTE value into data TLB
522          tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
523      }
524        break;
525
526      case AlphaISA::IPR_ITB_IA:
527        // really a control write
528        ipr[idx] = 0;
529
530        tc->getITBPtr()->flushAll();
531        break;
532
533      case AlphaISA::IPR_ITB_IAP:
534        // really a control write
535        ipr[idx] = 0;
536
537        tc->getITBPtr()->flushProcesses();
538        break;
539
540      case AlphaISA::IPR_ITB_IS:
541        // really a control write
542        ipr[idx] = val;
543
544        tc->getITBPtr()->flushAddr(val,
545                                   ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
546        break;
547
548      default:
549        // invalid IPR
550        return new UnimplementedOpcodeFault;
551    }
552
553    // no error...
554    return NoFault;
555}
556
557
558void
559AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
560{
561    for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
562        dest->setMiscReg(i, src->readMiscReg(i));
563    }
564}
565
566
567/**
568 * Check for special simulator handling of specific PAL calls.
569 * If return value is false, actual PAL call will be suppressed.
570 */
571bool
572SimpleThread::simPalCheck(int palFunc)
573{
574    if (kernelStats)
575        kernelStats->callpal(palFunc, tc);
576
577    switch (palFunc) {
578      case PAL::halt:
579        halt();
580        if (--System::numSystemsRunning == 0)
581            exitSimLoop("all cpus halted");
582        break;
583
584      case PAL::bpt:
585      case PAL::bugchk:
586        if (system->breakpoint())
587            return false;
588        break;
589    }
590
591    return true;
592}
593
594#endif // FULL_SYSTEM
595