ev5.cc revision 2710:33af9611cf2a
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/tlb.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/osfpal.hh" 35#include "base/kgdb.h" 36#include "base/remote_gdb.hh" 37#include "base/stats/events.hh" 38#include "config/full_system.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "kern/kernel_stats.hh" 43#include "sim/debug.hh" 44#include "sim/sim_exit.hh" 45 46#if FULL_SYSTEM 47 48using namespace EV5; 49 50//////////////////////////////////////////////////////////////////////// 51// 52// Machine dependent functions 53// 54void 55AlphaISA::initCPU(ThreadContext *tc, int cpuId) 56{ 57 initIPRs(tc, cpuId); 58 59 tc->setIntReg(16, cpuId); 60 tc->setIntReg(0, cpuId); 61 62 tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); 63 tc->setNextPC(tc->readPC() + sizeof(MachInst)); 64} 65 66//////////////////////////////////////////////////////////////////////// 67// 68// 69// 70void 71AlphaISA::initIPRs(ThreadContext *tc, int cpuId) 72{ 73 for (int i = 0; i < NumInternalProcRegs; ++i) { 74 tc->setMiscReg(i, 0); 75 } 76 77 tc->setMiscReg(IPR_PAL_BASE, PalBase); 78 tc->setMiscReg(IPR_MCSR, 0x6); 79 tc->setMiscReg(IPR_PALtemp16, cpuId); 80} 81 82 83template <class CPU> 84void 85AlphaISA::processInterrupts(CPU *cpu) 86{ 87 //Check if there are any outstanding interrupts 88 //Handle the interrupts 89 int ipl = 0; 90 int summary = 0; 91 92 cpu->checkInterrupts = false; 93 94 if (cpu->readMiscReg(IPR_ASTRR)) 95 panic("asynchronous traps not implemented\n"); 96 97 if (cpu->readMiscReg(IPR_SIRR)) { 98 for (int i = INTLEVEL_SOFTWARE_MIN; 99 i < INTLEVEL_SOFTWARE_MAX; i++) { 100 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 101 // See table 4-19 of the 21164 hardware reference 102 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 103 summary |= (ULL(1) << i); 104 } 105 } 106 } 107 108 uint64_t interrupts = cpu->intr_status(); 109 110 if (interrupts) { 111 for (int i = INTLEVEL_EXTERNAL_MIN; 112 i < INTLEVEL_EXTERNAL_MAX; i++) { 113 if (interrupts & (ULL(1) << i)) { 114 // See table 4-19 of the 21164 hardware reference 115 ipl = i; 116 summary |= (ULL(1) << i); 117 } 118 } 119 } 120 121 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { 122 cpu->setMiscReg(IPR_ISR, summary); 123 cpu->setMiscReg(IPR_INTID, ipl); 124 cpu->trap(new InterruptFault); 125 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 126 cpu->readMiscReg(IPR_IPLR), ipl, summary); 127 } 128 129} 130 131template <class CPU> 132void 133AlphaISA::zeroRegisters(CPU *cpu) 134{ 135 // Insure ISA semantics 136 // (no longer very clean due to the change in setIntReg() in the 137 // cpu model. Consider changing later.) 138 cpu->thread->setIntReg(ZeroReg, 0); 139 cpu->thread->setFloatReg(ZeroReg, 0.0); 140} 141 142Fault 143SimpleThread::hwrei() 144{ 145 if (!inPalMode()) 146 return new UnimplementedOpcodeFault; 147 148 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); 149 150 if (!misspeculating()) { 151 if (kernelStats) 152 kernelStats->hwrei(); 153 154 cpu->checkInterrupts = true; 155 } 156 157 // FIXME: XXX check for interrupts? XXX 158 return NoFault; 159} 160 161int 162AlphaISA::MiscRegFile::getInstAsid() 163{ 164 return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 165} 166 167int 168AlphaISA::MiscRegFile::getDataAsid() 169{ 170 return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 171} 172 173AlphaISA::MiscReg 174AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) 175{ 176 uint64_t retval = 0; // return value, default 0 177 178 switch (idx) { 179 case AlphaISA::IPR_PALtemp0: 180 case AlphaISA::IPR_PALtemp1: 181 case AlphaISA::IPR_PALtemp2: 182 case AlphaISA::IPR_PALtemp3: 183 case AlphaISA::IPR_PALtemp4: 184 case AlphaISA::IPR_PALtemp5: 185 case AlphaISA::IPR_PALtemp6: 186 case AlphaISA::IPR_PALtemp7: 187 case AlphaISA::IPR_PALtemp8: 188 case AlphaISA::IPR_PALtemp9: 189 case AlphaISA::IPR_PALtemp10: 190 case AlphaISA::IPR_PALtemp11: 191 case AlphaISA::IPR_PALtemp12: 192 case AlphaISA::IPR_PALtemp13: 193 case AlphaISA::IPR_PALtemp14: 194 case AlphaISA::IPR_PALtemp15: 195 case AlphaISA::IPR_PALtemp16: 196 case AlphaISA::IPR_PALtemp17: 197 case AlphaISA::IPR_PALtemp18: 198 case AlphaISA::IPR_PALtemp19: 199 case AlphaISA::IPR_PALtemp20: 200 case AlphaISA::IPR_PALtemp21: 201 case AlphaISA::IPR_PALtemp22: 202 case AlphaISA::IPR_PALtemp23: 203 case AlphaISA::IPR_PAL_BASE: 204 205 case AlphaISA::IPR_IVPTBR: 206 case AlphaISA::IPR_DC_MODE: 207 case AlphaISA::IPR_MAF_MODE: 208 case AlphaISA::IPR_ISR: 209 case AlphaISA::IPR_EXC_ADDR: 210 case AlphaISA::IPR_IC_PERR_STAT: 211 case AlphaISA::IPR_DC_PERR_STAT: 212 case AlphaISA::IPR_MCSR: 213 case AlphaISA::IPR_ASTRR: 214 case AlphaISA::IPR_ASTER: 215 case AlphaISA::IPR_SIRR: 216 case AlphaISA::IPR_ICSR: 217 case AlphaISA::IPR_ICM: 218 case AlphaISA::IPR_DTB_CM: 219 case AlphaISA::IPR_IPLR: 220 case AlphaISA::IPR_INTID: 221 case AlphaISA::IPR_PMCTR: 222 // no side-effect 223 retval = ipr[idx]; 224 break; 225 226 case AlphaISA::IPR_CC: 227 retval |= ipr[idx] & ULL(0xffffffff00000000); 228 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 229 break; 230 231 case AlphaISA::IPR_VA: 232 retval = ipr[idx]; 233 break; 234 235 case AlphaISA::IPR_VA_FORM: 236 case AlphaISA::IPR_MM_STAT: 237 case AlphaISA::IPR_IFAULT_VA_FORM: 238 case AlphaISA::IPR_EXC_MASK: 239 case AlphaISA::IPR_EXC_SUM: 240 retval = ipr[idx]; 241 break; 242 243 case AlphaISA::IPR_DTB_PTE: 244 { 245 AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); 246 247 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 248 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 249 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 250 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 251 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 252 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 253 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 254 } 255 break; 256 257 // write only registers 258 case AlphaISA::IPR_HWINT_CLR: 259 case AlphaISA::IPR_SL_XMIT: 260 case AlphaISA::IPR_DC_FLUSH: 261 case AlphaISA::IPR_IC_FLUSH: 262 case AlphaISA::IPR_ALT_MODE: 263 case AlphaISA::IPR_DTB_IA: 264 case AlphaISA::IPR_DTB_IAP: 265 case AlphaISA::IPR_ITB_IA: 266 case AlphaISA::IPR_ITB_IAP: 267 fault = new UnimplementedOpcodeFault; 268 break; 269 270 default: 271 // invalid IPR 272 fault = new UnimplementedOpcodeFault; 273 break; 274 } 275 276 return retval; 277} 278 279#ifdef DEBUG 280// Cause the simulator to break when changing to the following IPL 281int break_ipl = -1; 282#endif 283 284Fault 285AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) 286{ 287 uint64_t old; 288 289 if (tc->misspeculating()) 290 return NoFault; 291 292 switch (idx) { 293 case AlphaISA::IPR_PALtemp0: 294 case AlphaISA::IPR_PALtemp1: 295 case AlphaISA::IPR_PALtemp2: 296 case AlphaISA::IPR_PALtemp3: 297 case AlphaISA::IPR_PALtemp4: 298 case AlphaISA::IPR_PALtemp5: 299 case AlphaISA::IPR_PALtemp6: 300 case AlphaISA::IPR_PALtemp7: 301 case AlphaISA::IPR_PALtemp8: 302 case AlphaISA::IPR_PALtemp9: 303 case AlphaISA::IPR_PALtemp10: 304 case AlphaISA::IPR_PALtemp11: 305 case AlphaISA::IPR_PALtemp12: 306 case AlphaISA::IPR_PALtemp13: 307 case AlphaISA::IPR_PALtemp14: 308 case AlphaISA::IPR_PALtemp15: 309 case AlphaISA::IPR_PALtemp16: 310 case AlphaISA::IPR_PALtemp17: 311 case AlphaISA::IPR_PALtemp18: 312 case AlphaISA::IPR_PALtemp19: 313 case AlphaISA::IPR_PALtemp20: 314 case AlphaISA::IPR_PALtemp21: 315 case AlphaISA::IPR_PALtemp22: 316 case AlphaISA::IPR_PAL_BASE: 317 case AlphaISA::IPR_IC_PERR_STAT: 318 case AlphaISA::IPR_DC_PERR_STAT: 319 case AlphaISA::IPR_PMCTR: 320 // write entire quad w/ no side-effect 321 ipr[idx] = val; 322 break; 323 324 case AlphaISA::IPR_CC_CTL: 325 // This IPR resets the cycle counter. We assume this only 326 // happens once... let's verify that. 327 assert(ipr[idx] == 0); 328 ipr[idx] = 1; 329 break; 330 331 case AlphaISA::IPR_CC: 332 // This IPR only writes the upper 64 bits. It's ok to write 333 // all 64 here since we mask out the lower 32 in rpcc (see 334 // isa_desc). 335 ipr[idx] = val; 336 break; 337 338 case AlphaISA::IPR_PALtemp23: 339 // write entire quad w/ no side-effect 340 old = ipr[idx]; 341 ipr[idx] = val; 342 if (tc->getKernelStats()) 343 tc->getKernelStats()->context(old, val, tc); 344 break; 345 346 case AlphaISA::IPR_DTB_PTE: 347 // write entire quad w/ no side-effect, tag is forthcoming 348 ipr[idx] = val; 349 break; 350 351 case AlphaISA::IPR_EXC_ADDR: 352 // second least significant bit in PC is always zero 353 ipr[idx] = val & ~2; 354 break; 355 356 case AlphaISA::IPR_ASTRR: 357 case AlphaISA::IPR_ASTER: 358 // only write least significant four bits - privilege mask 359 ipr[idx] = val & 0xf; 360 break; 361 362 case AlphaISA::IPR_IPLR: 363#ifdef DEBUG 364 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 365 debug_break(); 366#endif 367 368 // only write least significant five bits - interrupt level 369 ipr[idx] = val & 0x1f; 370 if (tc->getKernelStats()) 371 tc->getKernelStats()->swpipl(ipr[idx]); 372 break; 373 374 case AlphaISA::IPR_DTB_CM: 375 if (val & 0x18) { 376 if (tc->getKernelStats()) 377 tc->getKernelStats()->mode(Kernel::user, tc); 378 } else { 379 if (tc->getKernelStats()) 380 tc->getKernelStats()->mode(Kernel::kernel, tc); 381 } 382 383 case AlphaISA::IPR_ICM: 384 // only write two mode bits - processor mode 385 ipr[idx] = val & 0x18; 386 break; 387 388 case AlphaISA::IPR_ALT_MODE: 389 // only write two mode bits - processor mode 390 ipr[idx] = val & 0x18; 391 break; 392 393 case AlphaISA::IPR_MCSR: 394 // more here after optimization... 395 ipr[idx] = val; 396 break; 397 398 case AlphaISA::IPR_SIRR: 399 // only write software interrupt mask 400 ipr[idx] = val & 0x7fff0; 401 break; 402 403 case AlphaISA::IPR_ICSR: 404 ipr[idx] = val & ULL(0xffffff0300); 405 break; 406 407 case AlphaISA::IPR_IVPTBR: 408 case AlphaISA::IPR_MVPTBR: 409 ipr[idx] = val & ULL(0xffffffffc0000000); 410 break; 411 412 case AlphaISA::IPR_DC_TEST_CTL: 413 ipr[idx] = val & 0x1ffb; 414 break; 415 416 case AlphaISA::IPR_DC_MODE: 417 case AlphaISA::IPR_MAF_MODE: 418 ipr[idx] = val & 0x3f; 419 break; 420 421 case AlphaISA::IPR_ITB_ASN: 422 ipr[idx] = val & 0x7f0; 423 break; 424 425 case AlphaISA::IPR_DTB_ASN: 426 ipr[idx] = val & ULL(0xfe00000000000000); 427 break; 428 429 case AlphaISA::IPR_EXC_SUM: 430 case AlphaISA::IPR_EXC_MASK: 431 // any write to this register clears it 432 ipr[idx] = 0; 433 break; 434 435 case AlphaISA::IPR_INTID: 436 case AlphaISA::IPR_SL_RCV: 437 case AlphaISA::IPR_MM_STAT: 438 case AlphaISA::IPR_ITB_PTE_TEMP: 439 case AlphaISA::IPR_DTB_PTE_TEMP: 440 // read-only registers 441 return new UnimplementedOpcodeFault; 442 443 case AlphaISA::IPR_HWINT_CLR: 444 case AlphaISA::IPR_SL_XMIT: 445 case AlphaISA::IPR_DC_FLUSH: 446 case AlphaISA::IPR_IC_FLUSH: 447 // the following are write only 448 ipr[idx] = val; 449 break; 450 451 case AlphaISA::IPR_DTB_IA: 452 // really a control write 453 ipr[idx] = 0; 454 455 tc->getDTBPtr()->flushAll(); 456 break; 457 458 case AlphaISA::IPR_DTB_IAP: 459 // really a control write 460 ipr[idx] = 0; 461 462 tc->getDTBPtr()->flushProcesses(); 463 break; 464 465 case AlphaISA::IPR_DTB_IS: 466 // really a control write 467 ipr[idx] = val; 468 469 tc->getDTBPtr()->flushAddr(val, 470 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 471 break; 472 473 case AlphaISA::IPR_DTB_TAG: { 474 struct AlphaISA::PTE pte; 475 476 // FIXME: granularity hints NYI... 477 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 478 panic("PTE GH field != 0"); 479 480 // write entire quad 481 ipr[idx] = val; 482 483 // construct PTE for new entry 484 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 485 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 486 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 487 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 488 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 489 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 490 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 491 492 // insert new TAG/PTE value into data TLB 493 tc->getDTBPtr()->insert(val, pte); 494 } 495 break; 496 497 case AlphaISA::IPR_ITB_PTE: { 498 struct AlphaISA::PTE pte; 499 500 // FIXME: granularity hints NYI... 501 if (ITB_PTE_GH(val) != 0) 502 panic("PTE GH field != 0"); 503 504 // write entire quad 505 ipr[idx] = val; 506 507 // construct PTE for new entry 508 pte.ppn = ITB_PTE_PPN(val); 509 pte.xre = ITB_PTE_XRE(val); 510 pte.xwe = 0; 511 pte.fonr = ITB_PTE_FONR(val); 512 pte.fonw = ITB_PTE_FONW(val); 513 pte.asma = ITB_PTE_ASMA(val); 514 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 515 516 // insert new TAG/PTE value into data TLB 517 tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 518 } 519 break; 520 521 case AlphaISA::IPR_ITB_IA: 522 // really a control write 523 ipr[idx] = 0; 524 525 tc->getITBPtr()->flushAll(); 526 break; 527 528 case AlphaISA::IPR_ITB_IAP: 529 // really a control write 530 ipr[idx] = 0; 531 532 tc->getITBPtr()->flushProcesses(); 533 break; 534 535 case AlphaISA::IPR_ITB_IS: 536 // really a control write 537 ipr[idx] = val; 538 539 tc->getITBPtr()->flushAddr(val, 540 ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 541 break; 542 543 default: 544 // invalid IPR 545 return new UnimplementedOpcodeFault; 546 } 547 548 // no error... 549 return NoFault; 550} 551 552void 553AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) 554{ 555 for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { 556 dest->setMiscReg(i, src->readMiscReg(i)); 557 } 558} 559 560/** 561 * Check for special simulator handling of specific PAL calls. 562 * If return value is false, actual PAL call will be suppressed. 563 */ 564bool 565SimpleThread::simPalCheck(int palFunc) 566{ 567 if (kernelStats) 568 kernelStats->callpal(palFunc, tc); 569 570 switch (palFunc) { 571 case PAL::halt: 572 halt(); 573 if (--System::numSystemsRunning == 0) 574 exitSimLoop("all cpus halted"); 575 break; 576 577 case PAL::bpt: 578 case PAL::bugchk: 579 if (system->breakpoint()) 580 return false; 581 break; 582 } 583 584 return true; 585} 586 587#endif // FULL_SYSTEM 588