ev5.cc revision 2159
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/alpha/alpha_memory.hh" 30#include "arch/alpha/isa_traits.hh" 31#include "arch/alpha/osfpal.hh" 32#include "base/kgdb.h" 33#include "base/remote_gdb.hh" 34#include "base/stats/events.hh" 35#include "config/full_system.hh" 36#include "cpu/base.hh" 37#include "cpu/exec_context.hh" 38#include "cpu/fast/cpu.hh" 39#include "kern/kernel_stats.hh" 40#include "sim/debug.hh" 41#include "sim/sim_events.hh" 42 43#if FULL_SYSTEM 44 45using namespace EV5; 46 47//////////////////////////////////////////////////////////////////////// 48// 49// 50// 51void 52AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) 53{ 54 if (regs->pal_shadow == use_shadow) 55 panic("swap_palshadow: wrong PAL shadow state"); 56 57 regs->pal_shadow = use_shadow; 58 59 for (int i = 0; i < NumIntRegs; i++) { 60 if (reg_redir[i]) { 61 IntReg temp = regs->intRegFile[i]; 62 regs->intRegFile[i] = regs->palregs[i]; 63 regs->palregs[i] = temp; 64 } 65 } 66} 67 68//////////////////////////////////////////////////////////////////////// 69// 70// Machine dependent functions 71// 72void 73AlphaISA::initCPU(RegFile *regs, int cpuId) 74{ 75 initIPRs(®s->miscRegs, cpuId); 76 // CPU comes up with PAL regs enabled 77 swap_palshadow(regs, true); 78 79 regs->intRegFile[16] = cpuId; 80 regs->intRegFile[0] = cpuId; 81 82 regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + fault_addr(ResetFault); 83 regs->npc = regs->pc + sizeof(MachInst); 84} 85 86//////////////////////////////////////////////////////////////////////// 87// 88// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE 89// 90const Addr 91AlphaISA::fault_addr(Fault fault) 92{ 93 //Check for the system wide faults 94 if(fault == NoFault) return 0x0000; 95 else if(fault == MachineCheckFault) return 0x0401; 96 else if(fault == AlignmentFault) return 0x0301; 97 //Deal with the alpha specific faults 98 return ((AlphaFault*)fault)->vect; 99}; 100 101const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { 102 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 103 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, 104 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 105 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 }; 106 107//////////////////////////////////////////////////////////////////////// 108// 109// 110// 111void 112AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId) 113{ 114 miscRegs->clearIprs(); 115 116 miscRegs->setReg(IPR_PAL_BASE, PalBase); 117 miscRegs->setReg(IPR_MCSR, 0x6); 118 miscRegs->setReg(IPR_PALtemp16, cpuId); 119} 120 121 122template <class CPU> 123void 124AlphaISA::processInterrupts(CPU *cpu) 125{ 126 //Check if there are any outstanding interrupts 127 //Handle the interrupts 128 int ipl = 0; 129 int summary = 0; 130 131 cpu->checkInterrupts = false; 132 133 if (cpu->readMiscReg(IPR_ASTRR)) 134 panic("asynchronous traps not implemented\n"); 135 136 if (cpu->readMiscReg(IPR_SIRR)) { 137 for (int i = INTLEVEL_SOFTWARE_MIN; 138 i < INTLEVEL_SOFTWARE_MAX; i++) { 139 if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 140 // See table 4-19 of the 21164 hardware reference 141 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 142 summary |= (ULL(1) << i); 143 } 144 } 145 } 146 147 uint64_t interrupts = cpu->intr_status(); 148 149 if (interrupts) { 150 for (int i = INTLEVEL_EXTERNAL_MIN; 151 i < INTLEVEL_EXTERNAL_MAX; i++) { 152 if (interrupts & (ULL(1) << i)) { 153 // See table 4-19 of the 21164 hardware reference 154 ipl = i; 155 summary |= (ULL(1) << i); 156 } 157 } 158 } 159 160 if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) { 161 cpu->setMiscReg(IPR_ISR, summary); 162 cpu->setMiscReg(IPR_INTID, ipl); 163 cpu->trap(InterruptFault); 164 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 165 cpu->readMiscReg(IPR_IPLR), ipl, summary); 166 } 167 168} 169 170template <class CPU> 171void 172AlphaISA::zeroRegisters(CPU *cpu) 173{ 174 // Insure ISA semantics 175 // (no longer very clean due to the change in setIntReg() in the 176 // cpu model. Consider changing later.) 177 cpu->xc->setIntReg(ZeroReg, 0); 178 cpu->xc->setFloatRegDouble(ZeroReg, 0.0); 179} 180 181void 182ExecContext::ev5_trap(Fault fault) 183{ 184 DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc); 185 cpu->recordEvent(csprintf("Fault %s", fault->name)); 186 187 assert(!misspeculating()); 188 kernelStats->fault(fault); 189 190 if (fault == ArithmeticFault) 191 panic("Arithmetic traps are unimplemented!"); 192 193 // exception restart address 194 if (fault != InterruptFault || !inPalMode()) 195 setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc); 196 197 if (fault == PalFault || fault == ArithmeticFault /* || 198 fault == InterruptFault && !inPalMode() */) { 199 // traps... skip faulting instruction 200 setMiscReg(AlphaISA::IPR_EXC_ADDR, 201 readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 202 } 203 204 if (!inPalMode()) 205 AlphaISA::swap_palshadow(®s, true); 206 207 regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault); 208 regs.npc = regs.pc + sizeof(MachInst); 209} 210 211 212void 213AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) 214{ 215 bool use_pc = (fault == NoFault); 216 217 if (fault == ArithmeticFault) 218 panic("arithmetic faults NYI..."); 219 220 // compute exception restart address 221 if (use_pc || fault == PalFault || fault == ArithmeticFault) { 222 // traps... skip faulting instruction 223 regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4); 224 } else { 225 // fault, post fault at excepting instruction 226 regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc); 227 } 228 229 // jump to expection address (PAL PC bit set here as well...) 230 if (!use_pc) 231 regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + 232 fault_addr(fault); 233 else 234 regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc; 235 236 // that's it! (orders of magnitude less painful than x86) 237} 238 239Fault 240ExecContext::hwrei() 241{ 242 if (!inPalMode()) 243 return UnimplementedOpcodeFault; 244 245 setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR)); 246 247 if (!misspeculating()) { 248 kernelStats->hwrei(); 249 250 if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0) 251 AlphaISA::swap_palshadow(®s, false); 252 253 cpu->checkInterrupts = true; 254 } 255 256 // FIXME: XXX check for interrupts? XXX 257 return NoFault; 258} 259 260void 261AlphaISA::MiscRegFile::clearIprs() 262{ 263 bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); 264} 265 266AlphaISA::MiscReg 267AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) 268{ 269 uint64_t retval = 0; // return value, default 0 270 271 switch (idx) { 272 case AlphaISA::IPR_PALtemp0: 273 case AlphaISA::IPR_PALtemp1: 274 case AlphaISA::IPR_PALtemp2: 275 case AlphaISA::IPR_PALtemp3: 276 case AlphaISA::IPR_PALtemp4: 277 case AlphaISA::IPR_PALtemp5: 278 case AlphaISA::IPR_PALtemp6: 279 case AlphaISA::IPR_PALtemp7: 280 case AlphaISA::IPR_PALtemp8: 281 case AlphaISA::IPR_PALtemp9: 282 case AlphaISA::IPR_PALtemp10: 283 case AlphaISA::IPR_PALtemp11: 284 case AlphaISA::IPR_PALtemp12: 285 case AlphaISA::IPR_PALtemp13: 286 case AlphaISA::IPR_PALtemp14: 287 case AlphaISA::IPR_PALtemp15: 288 case AlphaISA::IPR_PALtemp16: 289 case AlphaISA::IPR_PALtemp17: 290 case AlphaISA::IPR_PALtemp18: 291 case AlphaISA::IPR_PALtemp19: 292 case AlphaISA::IPR_PALtemp20: 293 case AlphaISA::IPR_PALtemp21: 294 case AlphaISA::IPR_PALtemp22: 295 case AlphaISA::IPR_PALtemp23: 296 case AlphaISA::IPR_PAL_BASE: 297 298 case AlphaISA::IPR_IVPTBR: 299 case AlphaISA::IPR_DC_MODE: 300 case AlphaISA::IPR_MAF_MODE: 301 case AlphaISA::IPR_ISR: 302 case AlphaISA::IPR_EXC_ADDR: 303 case AlphaISA::IPR_IC_PERR_STAT: 304 case AlphaISA::IPR_DC_PERR_STAT: 305 case AlphaISA::IPR_MCSR: 306 case AlphaISA::IPR_ASTRR: 307 case AlphaISA::IPR_ASTER: 308 case AlphaISA::IPR_SIRR: 309 case AlphaISA::IPR_ICSR: 310 case AlphaISA::IPR_ICM: 311 case AlphaISA::IPR_DTB_CM: 312 case AlphaISA::IPR_IPLR: 313 case AlphaISA::IPR_INTID: 314 case AlphaISA::IPR_PMCTR: 315 // no side-effect 316 retval = ipr[idx]; 317 break; 318 319 case AlphaISA::IPR_CC: 320 retval |= ipr[idx] & ULL(0xffffffff00000000); 321 retval |= xc->cpu->curCycle() & ULL(0x00000000ffffffff); 322 break; 323 324 case AlphaISA::IPR_VA: 325 retval = ipr[idx]; 326 break; 327 328 case AlphaISA::IPR_VA_FORM: 329 case AlphaISA::IPR_MM_STAT: 330 case AlphaISA::IPR_IFAULT_VA_FORM: 331 case AlphaISA::IPR_EXC_MASK: 332 case AlphaISA::IPR_EXC_SUM: 333 retval = ipr[idx]; 334 break; 335 336 case AlphaISA::IPR_DTB_PTE: 337 { 338 AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating()); 339 340 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 341 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 342 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 343 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 344 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 345 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 346 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 347 } 348 break; 349 350 // write only registers 351 case AlphaISA::IPR_HWINT_CLR: 352 case AlphaISA::IPR_SL_XMIT: 353 case AlphaISA::IPR_DC_FLUSH: 354 case AlphaISA::IPR_IC_FLUSH: 355 case AlphaISA::IPR_ALT_MODE: 356 case AlphaISA::IPR_DTB_IA: 357 case AlphaISA::IPR_DTB_IAP: 358 case AlphaISA::IPR_ITB_IA: 359 case AlphaISA::IPR_ITB_IAP: 360 fault = UnimplementedOpcodeFault; 361 break; 362 363 default: 364 // invalid IPR 365 fault = UnimplementedOpcodeFault; 366 break; 367 } 368 369 return retval; 370} 371 372#ifdef DEBUG 373// Cause the simulator to break when changing to the following IPL 374int break_ipl = -1; 375#endif 376 377Fault 378AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) 379{ 380 uint64_t old; 381 382 if (xc->misspeculating()) 383 return NoFault; 384 385 switch (idx) { 386 case AlphaISA::IPR_PALtemp0: 387 case AlphaISA::IPR_PALtemp1: 388 case AlphaISA::IPR_PALtemp2: 389 case AlphaISA::IPR_PALtemp3: 390 case AlphaISA::IPR_PALtemp4: 391 case AlphaISA::IPR_PALtemp5: 392 case AlphaISA::IPR_PALtemp6: 393 case AlphaISA::IPR_PALtemp7: 394 case AlphaISA::IPR_PALtemp8: 395 case AlphaISA::IPR_PALtemp9: 396 case AlphaISA::IPR_PALtemp10: 397 case AlphaISA::IPR_PALtemp11: 398 case AlphaISA::IPR_PALtemp12: 399 case AlphaISA::IPR_PALtemp13: 400 case AlphaISA::IPR_PALtemp14: 401 case AlphaISA::IPR_PALtemp15: 402 case AlphaISA::IPR_PALtemp16: 403 case AlphaISA::IPR_PALtemp17: 404 case AlphaISA::IPR_PALtemp18: 405 case AlphaISA::IPR_PALtemp19: 406 case AlphaISA::IPR_PALtemp20: 407 case AlphaISA::IPR_PALtemp21: 408 case AlphaISA::IPR_PALtemp22: 409 case AlphaISA::IPR_PAL_BASE: 410 case AlphaISA::IPR_IC_PERR_STAT: 411 case AlphaISA::IPR_DC_PERR_STAT: 412 case AlphaISA::IPR_PMCTR: 413 // write entire quad w/ no side-effect 414 ipr[idx] = val; 415 break; 416 417 case AlphaISA::IPR_CC_CTL: 418 // This IPR resets the cycle counter. We assume this only 419 // happens once... let's verify that. 420 assert(ipr[idx] == 0); 421 ipr[idx] = 1; 422 break; 423 424 case AlphaISA::IPR_CC: 425 // This IPR only writes the upper 64 bits. It's ok to write 426 // all 64 here since we mask out the lower 32 in rpcc (see 427 // isa_desc). 428 ipr[idx] = val; 429 break; 430 431 case AlphaISA::IPR_PALtemp23: 432 // write entire quad w/ no side-effect 433 old = ipr[idx]; 434 ipr[idx] = val; 435 xc->kernelStats->context(old, val); 436 break; 437 438 case AlphaISA::IPR_DTB_PTE: 439 // write entire quad w/ no side-effect, tag is forthcoming 440 ipr[idx] = val; 441 break; 442 443 case AlphaISA::IPR_EXC_ADDR: 444 // second least significant bit in PC is always zero 445 ipr[idx] = val & ~2; 446 break; 447 448 case AlphaISA::IPR_ASTRR: 449 case AlphaISA::IPR_ASTER: 450 // only write least significant four bits - privilege mask 451 ipr[idx] = val & 0xf; 452 break; 453 454 case AlphaISA::IPR_IPLR: 455#ifdef DEBUG 456 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 457 debug_break(); 458#endif 459 460 // only write least significant five bits - interrupt level 461 ipr[idx] = val & 0x1f; 462 xc->kernelStats->swpipl(ipr[idx]); 463 break; 464 465 case AlphaISA::IPR_DTB_CM: 466 if (val & 0x18) 467 xc->kernelStats->mode(Kernel::user); 468 else 469 xc->kernelStats->mode(Kernel::kernel); 470 471 case AlphaISA::IPR_ICM: 472 // only write two mode bits - processor mode 473 ipr[idx] = val & 0x18; 474 break; 475 476 case AlphaISA::IPR_ALT_MODE: 477 // only write two mode bits - processor mode 478 ipr[idx] = val & 0x18; 479 break; 480 481 case AlphaISA::IPR_MCSR: 482 // more here after optimization... 483 ipr[idx] = val; 484 break; 485 486 case AlphaISA::IPR_SIRR: 487 // only write software interrupt mask 488 ipr[idx] = val & 0x7fff0; 489 break; 490 491 case AlphaISA::IPR_ICSR: 492 ipr[idx] = val & ULL(0xffffff0300); 493 break; 494 495 case AlphaISA::IPR_IVPTBR: 496 case AlphaISA::IPR_MVPTBR: 497 ipr[idx] = val & ULL(0xffffffffc0000000); 498 break; 499 500 case AlphaISA::IPR_DC_TEST_CTL: 501 ipr[idx] = val & 0x1ffb; 502 break; 503 504 case AlphaISA::IPR_DC_MODE: 505 case AlphaISA::IPR_MAF_MODE: 506 ipr[idx] = val & 0x3f; 507 break; 508 509 case AlphaISA::IPR_ITB_ASN: 510 ipr[idx] = val & 0x7f0; 511 break; 512 513 case AlphaISA::IPR_DTB_ASN: 514 ipr[idx] = val & ULL(0xfe00000000000000); 515 break; 516 517 case AlphaISA::IPR_EXC_SUM: 518 case AlphaISA::IPR_EXC_MASK: 519 // any write to this register clears it 520 ipr[idx] = 0; 521 break; 522 523 case AlphaISA::IPR_INTID: 524 case AlphaISA::IPR_SL_RCV: 525 case AlphaISA::IPR_MM_STAT: 526 case AlphaISA::IPR_ITB_PTE_TEMP: 527 case AlphaISA::IPR_DTB_PTE_TEMP: 528 // read-only registers 529 return UnimplementedOpcodeFault; 530 531 case AlphaISA::IPR_HWINT_CLR: 532 case AlphaISA::IPR_SL_XMIT: 533 case AlphaISA::IPR_DC_FLUSH: 534 case AlphaISA::IPR_IC_FLUSH: 535 // the following are write only 536 ipr[idx] = val; 537 break; 538 539 case AlphaISA::IPR_DTB_IA: 540 // really a control write 541 ipr[idx] = 0; 542 543 xc->dtb->flushAll(); 544 break; 545 546 case AlphaISA::IPR_DTB_IAP: 547 // really a control write 548 ipr[idx] = 0; 549 550 xc->dtb->flushProcesses(); 551 break; 552 553 case AlphaISA::IPR_DTB_IS: 554 // really a control write 555 ipr[idx] = val; 556 557 xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 558 break; 559 560 case AlphaISA::IPR_DTB_TAG: { 561 struct AlphaISA::PTE pte; 562 563 // FIXME: granularity hints NYI... 564 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 565 panic("PTE GH field != 0"); 566 567 // write entire quad 568 ipr[idx] = val; 569 570 // construct PTE for new entry 571 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 572 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 573 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 574 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 575 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 576 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 577 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 578 579 // insert new TAG/PTE value into data TLB 580 xc->dtb->insert(val, pte); 581 } 582 break; 583 584 case AlphaISA::IPR_ITB_PTE: { 585 struct AlphaISA::PTE pte; 586 587 // FIXME: granularity hints NYI... 588 if (ITB_PTE_GH(val) != 0) 589 panic("PTE GH field != 0"); 590 591 // write entire quad 592 ipr[idx] = val; 593 594 // construct PTE for new entry 595 pte.ppn = ITB_PTE_PPN(val); 596 pte.xre = ITB_PTE_XRE(val); 597 pte.xwe = 0; 598 pte.fonr = ITB_PTE_FONR(val); 599 pte.fonw = ITB_PTE_FONW(val); 600 pte.asma = ITB_PTE_ASMA(val); 601 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 602 603 // insert new TAG/PTE value into data TLB 604 xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 605 } 606 break; 607 608 case AlphaISA::IPR_ITB_IA: 609 // really a control write 610 ipr[idx] = 0; 611 612 xc->itb->flushAll(); 613 break; 614 615 case AlphaISA::IPR_ITB_IAP: 616 // really a control write 617 ipr[idx] = 0; 618 619 xc->itb->flushProcesses(); 620 break; 621 622 case AlphaISA::IPR_ITB_IS: 623 // really a control write 624 ipr[idx] = val; 625 626 xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 627 break; 628 629 default: 630 // invalid IPR 631 return UnimplementedOpcodeFault; 632 } 633 634 // no error... 635 return NoFault; 636} 637 638/** 639 * Check for special simulator handling of specific PAL calls. 640 * If return value is false, actual PAL call will be suppressed. 641 */ 642bool 643ExecContext::simPalCheck(int palFunc) 644{ 645 kernelStats->callpal(palFunc); 646 647 switch (palFunc) { 648 case PAL::halt: 649 halt(); 650 if (--System::numSystemsRunning == 0) 651 new SimExitEvent("all cpus halted"); 652 break; 653 654 case PAL::bpt: 655 case PAL::bugchk: 656 if (system->breakpoint()) 657 return false; 658 break; 659 } 660 661 return true; 662} 663 664//Forward instantiation for FastCPU object 665template 666void AlphaISA::processInterrupts(FastCPU *xc); 667 668//Forward instantiation for FastCPU object 669template 670void AlphaISA::zeroRegisters(FastCPU *xc); 671 672#endif // FULL_SYSTEM 673