ev5.cc revision 1858
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/alpha/alpha_memory.hh" 30#include "arch/alpha/isa_traits.hh" 31#include "arch/alpha/osfpal.hh" 32#include "base/kgdb.h" 33#include "base/remote_gdb.hh" 34#include "base/stats/events.hh" 35#include "config/full_system.hh" 36#include "cpu/base.hh" 37#include "cpu/exec_context.hh" 38#include "cpu/fast/cpu.hh" 39#include "kern/kernel_stats.hh" 40#include "sim/debug.hh" 41#include "sim/sim_events.hh" 42 43#if FULL_SYSTEM 44 45using namespace EV5; 46 47//////////////////////////////////////////////////////////////////////// 48// 49// 50// 51void 52AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow) 53{ 54 if (regs->pal_shadow == use_shadow) 55 panic("swap_palshadow: wrong PAL shadow state"); 56 57 regs->pal_shadow = use_shadow; 58 59 for (int i = 0; i < NumIntRegs; i++) { 60 if (reg_redir[i]) { 61 IntReg temp = regs->intRegFile[i]; 62 regs->intRegFile[i] = regs->palregs[i]; 63 regs->palregs[i] = temp; 64 } 65 } 66} 67 68//////////////////////////////////////////////////////////////////////// 69// 70// Machine dependent functions 71// 72void 73AlphaISA::initCPU(RegFile *regs) 74{ 75 initIPRs(regs); 76 // CPU comes up with PAL regs enabled 77 swap_palshadow(regs, true); 78 79 regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault]; 80 regs->npc = regs->pc + sizeof(MachInst); 81} 82 83//////////////////////////////////////////////////////////////////////// 84// 85// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE 86// 87Addr 88AlphaISA::fault_addr[Num_Faults] = { 89 0x0000, /* No_Fault */ 90 0x0001, /* Reset_Fault */ 91 0x0401, /* Machine_Check_Fault */ 92 0x0501, /* Arithmetic_Fault */ 93 0x0101, /* Interrupt_Fault */ 94 0x0201, /* Ndtb_Miss_Fault */ 95 0x0281, /* Pdtb_Miss_Fault */ 96 0x0301, /* Alignment_Fault */ 97 0x0381, /* DTB_Fault_Fault */ 98 0x0381, /* DTB_Acv_Fault */ 99 0x0181, /* ITB_Miss_Fault */ 100 0x0181, /* ITB_Fault_Fault */ 101 0x0081, /* ITB_Acv_Fault */ 102 0x0481, /* Unimplemented_Opcode_Fault */ 103 0x0581, /* Fen_Fault */ 104 0x2001, /* Pal_Fault */ 105 0x0501, /* Integer_Overflow_Fault: maps to Arithmetic_Fault */ 106}; 107 108const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = { 109 /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, 110 /* 8 */ 1, 1, 1, 1, 1, 1, 1, 0, 111 /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 112 /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 }; 113 114//////////////////////////////////////////////////////////////////////// 115// 116// 117// 118void 119AlphaISA::initIPRs(RegFile *regs) 120{ 121 uint64_t *ipr = regs->ipr; 122 123 bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg)); 124 ipr[IPR_PAL_BASE] = PalBase; 125 ipr[IPR_MCSR] = 0x6; 126} 127 128 129template <class CPU> 130void 131AlphaISA::processInterrupts(CPU *cpu) 132{ 133 //Check if there are any outstanding interrupts 134 //Handle the interrupts 135 int ipl = 0; 136 int summary = 0; 137 IntReg *ipr = cpu->getIprPtr(); 138 139 cpu->checkInterrupts = false; 140 141 if (ipr[IPR_ASTRR]) 142 panic("asynchronous traps not implemented\n"); 143 144 if (ipr[IPR_SIRR]) { 145 for (int i = INTLEVEL_SOFTWARE_MIN; 146 i < INTLEVEL_SOFTWARE_MAX; i++) { 147 if (ipr[IPR_SIRR] & (ULL(1) << i)) { 148 // See table 4-19 of the 21164 hardware reference 149 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 150 summary |= (ULL(1) << i); 151 } 152 } 153 } 154 155 uint64_t interrupts = cpu->intr_status(); 156 157 if (interrupts) { 158 for (int i = INTLEVEL_EXTERNAL_MIN; 159 i < INTLEVEL_EXTERNAL_MAX; i++) { 160 if (interrupts & (ULL(1) << i)) { 161 // See table 4-19 of the 21164 hardware reference 162 ipl = i; 163 summary |= (ULL(1) << i); 164 } 165 } 166 } 167 168 if (ipl && ipl > ipr[IPR_IPLR]) { 169 ipr[IPR_ISR] = summary; 170 ipr[IPR_INTID] = ipl; 171 cpu->trap(Interrupt_Fault); 172 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 173 ipr[IPR_IPLR], ipl, summary); 174 } 175 176} 177 178template <class CPU> 179void 180AlphaISA::zeroRegisters(CPU *cpu) 181{ 182 // Insure ISA semantics 183 // (no longer very clean due to the change in setIntReg() in the 184 // cpu model. Consider changing later.) 185 cpu->xc->setIntReg(ZeroReg, 0); 186 cpu->xc->setFloatRegDouble(ZeroReg, 0.0); 187} 188 189void 190ExecContext::ev5_trap(Fault fault) 191{ 192 DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc); 193 cpu->recordEvent(csprintf("Fault %s", FaultName(fault))); 194 195 assert(!misspeculating()); 196 kernelStats->fault(fault); 197 198 if (fault == Arithmetic_Fault) 199 panic("Arithmetic traps are unimplemented!"); 200 201 AlphaISA::InternalProcReg *ipr = regs.ipr; 202 203 // exception restart address 204 if (fault != Interrupt_Fault || !inPalMode()) 205 ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc; 206 207 if (fault == Pal_Fault || fault == Arithmetic_Fault /* || 208 fault == Interrupt_Fault && !inPalMode() */) { 209 // traps... skip faulting instruction 210 ipr[AlphaISA::IPR_EXC_ADDR] += 4; 211 } 212 213 if (!inPalMode()) 214 AlphaISA::swap_palshadow(®s, true); 215 216 regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault]; 217 regs.npc = regs.pc + sizeof(MachInst); 218} 219 220 221void 222AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) 223{ 224 InternalProcReg *ipr = regs->ipr; 225 bool use_pc = (fault == No_Fault); 226 227 if (fault == Arithmetic_Fault) 228 panic("arithmetic faults NYI..."); 229 230 // compute exception restart address 231 if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) { 232 // traps... skip faulting instruction 233 ipr[IPR_EXC_ADDR] = regs->pc + 4; 234 } else { 235 // fault, post fault at excepting instruction 236 ipr[IPR_EXC_ADDR] = regs->pc; 237 } 238 239 // jump to expection address (PAL PC bit set here as well...) 240 if (!use_pc) 241 regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault]; 242 else 243 regs->npc = ipr[IPR_PAL_BASE] + pc; 244 245 // that's it! (orders of magnitude less painful than x86) 246} 247 248Fault 249ExecContext::hwrei() 250{ 251 uint64_t *ipr = regs.ipr; 252 253 if (!inPalMode()) 254 return Unimplemented_Opcode_Fault; 255 256 setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); 257 258 if (!misspeculating()) { 259 kernelStats->hwrei(); 260 261 if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) 262 AlphaISA::swap_palshadow(®s, false); 263 264 cpu->checkInterrupts = true; 265 } 266 267 // FIXME: XXX check for interrupts? XXX 268 return No_Fault; 269} 270 271uint64_t 272ExecContext::readIpr(int idx, Fault &fault) 273{ 274 uint64_t *ipr = regs.ipr; 275 uint64_t retval = 0; // return value, default 0 276 277 switch (idx) { 278 case AlphaISA::IPR_PALtemp0: 279 case AlphaISA::IPR_PALtemp1: 280 case AlphaISA::IPR_PALtemp2: 281 case AlphaISA::IPR_PALtemp3: 282 case AlphaISA::IPR_PALtemp4: 283 case AlphaISA::IPR_PALtemp5: 284 case AlphaISA::IPR_PALtemp6: 285 case AlphaISA::IPR_PALtemp7: 286 case AlphaISA::IPR_PALtemp8: 287 case AlphaISA::IPR_PALtemp9: 288 case AlphaISA::IPR_PALtemp10: 289 case AlphaISA::IPR_PALtemp11: 290 case AlphaISA::IPR_PALtemp12: 291 case AlphaISA::IPR_PALtemp13: 292 case AlphaISA::IPR_PALtemp14: 293 case AlphaISA::IPR_PALtemp15: 294 case AlphaISA::IPR_PALtemp16: 295 case AlphaISA::IPR_PALtemp17: 296 case AlphaISA::IPR_PALtemp18: 297 case AlphaISA::IPR_PALtemp19: 298 case AlphaISA::IPR_PALtemp20: 299 case AlphaISA::IPR_PALtemp21: 300 case AlphaISA::IPR_PALtemp22: 301 case AlphaISA::IPR_PALtemp23: 302 case AlphaISA::IPR_PAL_BASE: 303 304 case AlphaISA::IPR_IVPTBR: 305 case AlphaISA::IPR_DC_MODE: 306 case AlphaISA::IPR_MAF_MODE: 307 case AlphaISA::IPR_ISR: 308 case AlphaISA::IPR_EXC_ADDR: 309 case AlphaISA::IPR_IC_PERR_STAT: 310 case AlphaISA::IPR_DC_PERR_STAT: 311 case AlphaISA::IPR_MCSR: 312 case AlphaISA::IPR_ASTRR: 313 case AlphaISA::IPR_ASTER: 314 case AlphaISA::IPR_SIRR: 315 case AlphaISA::IPR_ICSR: 316 case AlphaISA::IPR_ICM: 317 case AlphaISA::IPR_DTB_CM: 318 case AlphaISA::IPR_IPLR: 319 case AlphaISA::IPR_INTID: 320 case AlphaISA::IPR_PMCTR: 321 // no side-effect 322 retval = ipr[idx]; 323 break; 324 325 case AlphaISA::IPR_CC: 326 retval |= ipr[idx] & ULL(0xffffffff00000000); 327 retval |= cpu->curCycle() & ULL(0x00000000ffffffff); 328 break; 329 330 case AlphaISA::IPR_VA: 331 retval = ipr[idx]; 332 break; 333 334 case AlphaISA::IPR_VA_FORM: 335 case AlphaISA::IPR_MM_STAT: 336 case AlphaISA::IPR_IFAULT_VA_FORM: 337 case AlphaISA::IPR_EXC_MASK: 338 case AlphaISA::IPR_EXC_SUM: 339 retval = ipr[idx]; 340 break; 341 342 case AlphaISA::IPR_DTB_PTE: 343 { 344 AlphaISA::PTE &pte = dtb->index(!misspeculating()); 345 346 retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; 347 retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; 348 retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; 349 retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; 350 retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; 351 retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; 352 retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; 353 } 354 break; 355 356 // write only registers 357 case AlphaISA::IPR_HWINT_CLR: 358 case AlphaISA::IPR_SL_XMIT: 359 case AlphaISA::IPR_DC_FLUSH: 360 case AlphaISA::IPR_IC_FLUSH: 361 case AlphaISA::IPR_ALT_MODE: 362 case AlphaISA::IPR_DTB_IA: 363 case AlphaISA::IPR_DTB_IAP: 364 case AlphaISA::IPR_ITB_IA: 365 case AlphaISA::IPR_ITB_IAP: 366 fault = Unimplemented_Opcode_Fault; 367 break; 368 369 default: 370 // invalid IPR 371 fault = Unimplemented_Opcode_Fault; 372 break; 373 } 374 375 return retval; 376} 377 378#ifdef DEBUG 379// Cause the simulator to break when changing to the following IPL 380int break_ipl = -1; 381#endif 382 383Fault 384ExecContext::setIpr(int idx, uint64_t val) 385{ 386 uint64_t *ipr = regs.ipr; 387 uint64_t old; 388 389 if (misspeculating()) 390 return No_Fault; 391 392 switch (idx) { 393 case AlphaISA::IPR_PALtemp0: 394 case AlphaISA::IPR_PALtemp1: 395 case AlphaISA::IPR_PALtemp2: 396 case AlphaISA::IPR_PALtemp3: 397 case AlphaISA::IPR_PALtemp4: 398 case AlphaISA::IPR_PALtemp5: 399 case AlphaISA::IPR_PALtemp6: 400 case AlphaISA::IPR_PALtemp7: 401 case AlphaISA::IPR_PALtemp8: 402 case AlphaISA::IPR_PALtemp9: 403 case AlphaISA::IPR_PALtemp10: 404 case AlphaISA::IPR_PALtemp11: 405 case AlphaISA::IPR_PALtemp12: 406 case AlphaISA::IPR_PALtemp13: 407 case AlphaISA::IPR_PALtemp14: 408 case AlphaISA::IPR_PALtemp15: 409 case AlphaISA::IPR_PALtemp16: 410 case AlphaISA::IPR_PALtemp17: 411 case AlphaISA::IPR_PALtemp18: 412 case AlphaISA::IPR_PALtemp19: 413 case AlphaISA::IPR_PALtemp20: 414 case AlphaISA::IPR_PALtemp21: 415 case AlphaISA::IPR_PALtemp22: 416 case AlphaISA::IPR_PAL_BASE: 417 case AlphaISA::IPR_IC_PERR_STAT: 418 case AlphaISA::IPR_DC_PERR_STAT: 419 case AlphaISA::IPR_PMCTR: 420 // write entire quad w/ no side-effect 421 ipr[idx] = val; 422 break; 423 424 case AlphaISA::IPR_CC_CTL: 425 // This IPR resets the cycle counter. We assume this only 426 // happens once... let's verify that. 427 assert(ipr[idx] == 0); 428 ipr[idx] = 1; 429 break; 430 431 case AlphaISA::IPR_CC: 432 // This IPR only writes the upper 64 bits. It's ok to write 433 // all 64 here since we mask out the lower 32 in rpcc (see 434 // isa_desc). 435 ipr[idx] = val; 436 break; 437 438 case AlphaISA::IPR_PALtemp23: 439 // write entire quad w/ no side-effect 440 old = ipr[idx]; 441 ipr[idx] = val; 442 kernelStats->context(old, val); 443 break; 444 445 case AlphaISA::IPR_DTB_PTE: 446 // write entire quad w/ no side-effect, tag is forthcoming 447 ipr[idx] = val; 448 break; 449 450 case AlphaISA::IPR_EXC_ADDR: 451 // second least significant bit in PC is always zero 452 ipr[idx] = val & ~2; 453 break; 454 455 case AlphaISA::IPR_ASTRR: 456 case AlphaISA::IPR_ASTER: 457 // only write least significant four bits - privilege mask 458 ipr[idx] = val & 0xf; 459 break; 460 461 case AlphaISA::IPR_IPLR: 462#ifdef DEBUG 463 if (break_ipl != -1 && break_ipl == (val & 0x1f)) 464 debug_break(); 465#endif 466 467 // only write least significant five bits - interrupt level 468 ipr[idx] = val & 0x1f; 469 kernelStats->swpipl(ipr[idx]); 470 break; 471 472 case AlphaISA::IPR_DTB_CM: 473 if (val & 0x18) 474 kernelStats->mode(Kernel::user); 475 else 476 kernelStats->mode(Kernel::kernel); 477 478 case AlphaISA::IPR_ICM: 479 // only write two mode bits - processor mode 480 ipr[idx] = val & 0x18; 481 break; 482 483 case AlphaISA::IPR_ALT_MODE: 484 // only write two mode bits - processor mode 485 ipr[idx] = val & 0x18; 486 break; 487 488 case AlphaISA::IPR_MCSR: 489 // more here after optimization... 490 ipr[idx] = val; 491 break; 492 493 case AlphaISA::IPR_SIRR: 494 // only write software interrupt mask 495 ipr[idx] = val & 0x7fff0; 496 break; 497 498 case AlphaISA::IPR_ICSR: 499 ipr[idx] = val & ULL(0xffffff0300); 500 break; 501 502 case AlphaISA::IPR_IVPTBR: 503 case AlphaISA::IPR_MVPTBR: 504 ipr[idx] = val & ULL(0xffffffffc0000000); 505 break; 506 507 case AlphaISA::IPR_DC_TEST_CTL: 508 ipr[idx] = val & 0x1ffb; 509 break; 510 511 case AlphaISA::IPR_DC_MODE: 512 case AlphaISA::IPR_MAF_MODE: 513 ipr[idx] = val & 0x3f; 514 break; 515 516 case AlphaISA::IPR_ITB_ASN: 517 ipr[idx] = val & 0x7f0; 518 break; 519 520 case AlphaISA::IPR_DTB_ASN: 521 ipr[idx] = val & ULL(0xfe00000000000000); 522 break; 523 524 case AlphaISA::IPR_EXC_SUM: 525 case AlphaISA::IPR_EXC_MASK: 526 // any write to this register clears it 527 ipr[idx] = 0; 528 break; 529 530 case AlphaISA::IPR_INTID: 531 case AlphaISA::IPR_SL_RCV: 532 case AlphaISA::IPR_MM_STAT: 533 case AlphaISA::IPR_ITB_PTE_TEMP: 534 case AlphaISA::IPR_DTB_PTE_TEMP: 535 // read-only registers 536 return Unimplemented_Opcode_Fault; 537 538 case AlphaISA::IPR_HWINT_CLR: 539 case AlphaISA::IPR_SL_XMIT: 540 case AlphaISA::IPR_DC_FLUSH: 541 case AlphaISA::IPR_IC_FLUSH: 542 // the following are write only 543 ipr[idx] = val; 544 break; 545 546 case AlphaISA::IPR_DTB_IA: 547 // really a control write 548 ipr[idx] = 0; 549 550 dtb->flushAll(); 551 break; 552 553 case AlphaISA::IPR_DTB_IAP: 554 // really a control write 555 ipr[idx] = 0; 556 557 dtb->flushProcesses(); 558 break; 559 560 case AlphaISA::IPR_DTB_IS: 561 // really a control write 562 ipr[idx] = val; 563 564 dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 565 break; 566 567 case AlphaISA::IPR_DTB_TAG: { 568 struct AlphaISA::PTE pte; 569 570 // FIXME: granularity hints NYI... 571 if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0) 572 panic("PTE GH field != 0"); 573 574 // write entire quad 575 ipr[idx] = val; 576 577 // construct PTE for new entry 578 pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]); 579 pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]); 580 pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]); 581 pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]); 582 pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]); 583 pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]); 584 pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); 585 586 // insert new TAG/PTE value into data TLB 587 dtb->insert(val, pte); 588 } 589 break; 590 591 case AlphaISA::IPR_ITB_PTE: { 592 struct AlphaISA::PTE pte; 593 594 // FIXME: granularity hints NYI... 595 if (ITB_PTE_GH(val) != 0) 596 panic("PTE GH field != 0"); 597 598 // write entire quad 599 ipr[idx] = val; 600 601 // construct PTE for new entry 602 pte.ppn = ITB_PTE_PPN(val); 603 pte.xre = ITB_PTE_XRE(val); 604 pte.xwe = 0; 605 pte.fonr = ITB_PTE_FONR(val); 606 pte.fonw = ITB_PTE_FONW(val); 607 pte.asma = ITB_PTE_ASMA(val); 608 pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); 609 610 // insert new TAG/PTE value into data TLB 611 itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); 612 } 613 break; 614 615 case AlphaISA::IPR_ITB_IA: 616 // really a control write 617 ipr[idx] = 0; 618 619 itb->flushAll(); 620 break; 621 622 case AlphaISA::IPR_ITB_IAP: 623 // really a control write 624 ipr[idx] = 0; 625 626 itb->flushProcesses(); 627 break; 628 629 case AlphaISA::IPR_ITB_IS: 630 // really a control write 631 ipr[idx] = val; 632 633 itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); 634 break; 635 636 default: 637 // invalid IPR 638 return Unimplemented_Opcode_Fault; 639 } 640 641 // no error... 642 return No_Fault; 643} 644 645/** 646 * Check for special simulator handling of specific PAL calls. 647 * If return value is false, actual PAL call will be suppressed. 648 */ 649bool 650ExecContext::simPalCheck(int palFunc) 651{ 652 kernelStats->callpal(palFunc); 653 654 switch (palFunc) { 655 case PAL::halt: 656 halt(); 657 if (--System::numSystemsRunning == 0) 658 new SimExitEvent("all cpus halted"); 659 break; 660 661 case PAL::bpt: 662 case PAL::bugchk: 663 if (system->breakpoint()) 664 return false; 665 break; 666 } 667 668 return true; 669} 670 671//Forward instantiation for FastCPU object 672template 673void AlphaISA::processInterrupts(FastCPU *xc); 674 675//Forward instantiation for FastCPU object 676template 677void AlphaISA::zeroRegisters(FastCPU *xc); 678 679#endif // FULL_SYSTEM 680