ev5.cc revision 13611
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include "arch/alpha/faults.hh" 33#include "arch/alpha/isa_traits.hh" 34#include "arch/alpha/kernel_stats.hh" 35#include "arch/alpha/osfpal.hh" 36#include "arch/alpha/tlb.hh" 37#include "base/cp_annotate.hh" 38#include "base/debug.hh" 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/thread_context.hh" 42#include "sim/sim_exit.hh" 43 44namespace AlphaISA { 45 46template<typename T> 47TLB * 48getITBPtr(T *tc) 49{ 50 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr()); 51 assert(tlb); 52 return tlb; 53} 54 55template<typename T> 56TLB * 57getDTBPtr(T *tc) 58{ 59 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr()); 60 assert(tlb); 61 return tlb; 62} 63 64//////////////////////////////////////////////////////////////////////// 65// 66// Machine dependent functions 67// 68void 69initCPU(ThreadContext *tc, int cpuId) 70{ 71 initIPRs(tc, cpuId); 72 73 tc->setIntReg(16, cpuId); 74 tc->setIntReg(0, cpuId); 75 76 AlphaFault *reset = new ResetFault; 77 78 tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); 79 80 delete reset; 81} 82 83template <class CPU> 84void 85zeroRegisters(CPU *cpu) 86{ 87 // Insure ISA semantics 88 // (no longer very clean due to the change in setIntReg() in the 89 // cpu model. Consider changing later.) 90 cpu->thread->setIntReg(ZeroReg, 0); 91 cpu->thread->setFloatReg(ZeroReg, 0); 92} 93 94//////////////////////////////////////////////////////////////////////// 95// 96// 97// 98void 99initIPRs(ThreadContext *tc, int cpuId) 100{ 101 for (int i = 0; i < NumInternalProcRegs; ++i) { 102 tc->setMiscRegNoEffect(i, 0); 103 } 104 105 tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); 106 tc->setMiscRegNoEffect(IPR_MCSR, 0x6); 107 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); 108} 109 110MiscReg 111ISA::readIpr(int idx, ThreadContext *tc) 112{ 113 uint64_t retval = 0; // return value, default 0 114 115 switch (idx) { 116 case IPR_PALtemp0: 117 case IPR_PALtemp1: 118 case IPR_PALtemp2: 119 case IPR_PALtemp3: 120 case IPR_PALtemp4: 121 case IPR_PALtemp5: 122 case IPR_PALtemp6: 123 case IPR_PALtemp7: 124 case IPR_PALtemp8: 125 case IPR_PALtemp9: 126 case IPR_PALtemp10: 127 case IPR_PALtemp11: 128 case IPR_PALtemp12: 129 case IPR_PALtemp13: 130 case IPR_PALtemp14: 131 case IPR_PALtemp15: 132 case IPR_PALtemp16: 133 case IPR_PALtemp17: 134 case IPR_PALtemp18: 135 case IPR_PALtemp19: 136 case IPR_PALtemp20: 137 case IPR_PALtemp21: 138 case IPR_PALtemp22: 139 case IPR_PALtemp23: 140 case IPR_PAL_BASE: 141 142 case IPR_IVPTBR: 143 case IPR_DC_MODE: 144 case IPR_MAF_MODE: 145 case IPR_ISR: 146 case IPR_EXC_ADDR: 147 case IPR_IC_PERR_STAT: 148 case IPR_DC_PERR_STAT: 149 case IPR_MCSR: 150 case IPR_ASTRR: 151 case IPR_ASTER: 152 case IPR_SIRR: 153 case IPR_ICSR: 154 case IPR_ICM: 155 case IPR_DTB_CM: 156 case IPR_IPLR: 157 case IPR_INTID: 158 case IPR_PMCTR: 159 // no side-effect 160 retval = ipr[idx]; 161 break; 162 163 case IPR_CC: 164 retval |= ipr[idx] & ULL(0xffffffff00000000); 165 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); 166 break; 167 168 case IPR_VA: 169 retval = ipr[idx]; 170 break; 171 172 case IPR_VA_FORM: 173 case IPR_MM_STAT: 174 case IPR_IFAULT_VA_FORM: 175 case IPR_EXC_MASK: 176 case IPR_EXC_SUM: 177 retval = ipr[idx]; 178 break; 179 180 case IPR_DTB_PTE: 181 { 182 TlbEntry &entry = getDTBPtr(tc)->index(1); 183 184 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; 185 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; 186 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; 187 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; 188 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; 189 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; 190 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; 191 } 192 break; 193 194 // write only registers 195 case IPR_HWINT_CLR: 196 case IPR_SL_XMIT: 197 case IPR_DC_FLUSH: 198 case IPR_IC_FLUSH: 199 case IPR_ALT_MODE: 200 case IPR_DTB_IA: 201 case IPR_DTB_IAP: 202 case IPR_ITB_IA: 203 case IPR_ITB_IAP: 204 panic("Tried to read write only register %d\n", idx); 205 break; 206 207 default: 208 // invalid IPR 209 panic("Tried to read from invalid ipr %d\n", idx); 210 break; 211 } 212 213 return retval; 214} 215 216// Cause the simulator to break when changing to the following IPL 217int break_ipl = -1; 218 219void 220ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) 221{ 222 switch (idx) { 223 case IPR_PALtemp0: 224 case IPR_PALtemp1: 225 case IPR_PALtemp2: 226 case IPR_PALtemp3: 227 case IPR_PALtemp4: 228 case IPR_PALtemp5: 229 case IPR_PALtemp6: 230 case IPR_PALtemp7: 231 case IPR_PALtemp8: 232 case IPR_PALtemp9: 233 case IPR_PALtemp10: 234 case IPR_PALtemp11: 235 case IPR_PALtemp12: 236 case IPR_PALtemp13: 237 case IPR_PALtemp14: 238 case IPR_PALtemp15: 239 case IPR_PALtemp16: 240 case IPR_PALtemp17: 241 case IPR_PALtemp18: 242 case IPR_PALtemp19: 243 case IPR_PALtemp20: 244 case IPR_PALtemp21: 245 case IPR_PALtemp22: 246 case IPR_PAL_BASE: 247 case IPR_IC_PERR_STAT: 248 case IPR_DC_PERR_STAT: 249 case IPR_PMCTR: 250 // write entire quad w/ no side-effect 251 ipr[idx] = val; 252 break; 253 254 case IPR_CC_CTL: 255 // This IPR resets the cycle counter. We assume this only 256 // happens once... let's verify that. 257 assert(ipr[idx] == 0); 258 ipr[idx] = 1; 259 break; 260 261 case IPR_CC: 262 // This IPR only writes the upper 64 bits. It's ok to write 263 // all 64 here since we mask out the lower 32 in rpcc (see 264 // isa_desc). 265 ipr[idx] = val; 266 break; 267 268 case IPR_PALtemp23: 269 // write entire quad w/ no side-effect 270 if (tc->getKernelStats()) 271 tc->getKernelStats()->context(ipr[idx], val, tc); 272 ipr[idx] = val; 273 break; 274 275 case IPR_DTB_PTE: 276 // write entire quad w/ no side-effect, tag is forthcoming 277 ipr[idx] = val; 278 break; 279 280 case IPR_EXC_ADDR: 281 // second least significant bit in PC is always zero 282 ipr[idx] = val & ~2; 283 break; 284 285 case IPR_ASTRR: 286 case IPR_ASTER: 287 // only write least significant four bits - privilege mask 288 ipr[idx] = val & 0xf; 289 break; 290 291 case IPR_IPLR: 292 // only write least significant five bits - interrupt level 293 ipr[idx] = val & 0x1f; 294 if (tc->getKernelStats()) 295 tc->getKernelStats()->swpipl(ipr[idx]); 296 break; 297 298 case IPR_DTB_CM: 299 if (val & 0x18) { 300 if (tc->getKernelStats()) 301 tc->getKernelStats()->mode(Kernel::user, tc); 302 } else { 303 if (tc->getKernelStats()) 304 tc->getKernelStats()->mode(Kernel::kernel, tc); 305 } 306 M5_FALLTHROUGH; 307 308 case IPR_ICM: 309 // only write two mode bits - processor mode 310 ipr[idx] = val & 0x18; 311 break; 312 313 case IPR_ALT_MODE: 314 // only write two mode bits - processor mode 315 ipr[idx] = val & 0x18; 316 break; 317 318 case IPR_MCSR: 319 // more here after optimization... 320 ipr[idx] = val; 321 break; 322 323 case IPR_SIRR: 324 // only write software interrupt mask 325 ipr[idx] = val & 0x7fff0; 326 break; 327 328 case IPR_ICSR: 329 ipr[idx] = val & ULL(0xffffff0300); 330 break; 331 332 case IPR_IVPTBR: 333 case IPR_MVPTBR: 334 ipr[idx] = val & ULL(0xffffffffc0000000); 335 break; 336 337 case IPR_DC_TEST_CTL: 338 ipr[idx] = val & 0x1ffb; 339 break; 340 341 case IPR_DC_MODE: 342 case IPR_MAF_MODE: 343 ipr[idx] = val & 0x3f; 344 break; 345 346 case IPR_ITB_ASN: 347 ipr[idx] = val & 0x7f0; 348 break; 349 350 case IPR_DTB_ASN: 351 ipr[idx] = val & ULL(0xfe00000000000000); 352 break; 353 354 case IPR_EXC_SUM: 355 case IPR_EXC_MASK: 356 // any write to this register clears it 357 ipr[idx] = 0; 358 break; 359 360 case IPR_INTID: 361 case IPR_SL_RCV: 362 case IPR_MM_STAT: 363 case IPR_ITB_PTE_TEMP: 364 case IPR_DTB_PTE_TEMP: 365 // read-only registers 366 panic("Tried to write read only ipr %d\n", idx); 367 368 case IPR_HWINT_CLR: 369 case IPR_SL_XMIT: 370 case IPR_DC_FLUSH: 371 case IPR_IC_FLUSH: 372 // the following are write only 373 ipr[idx] = val; 374 break; 375 376 case IPR_DTB_IA: 377 // really a control write 378 ipr[idx] = 0; 379 380 getDTBPtr(tc)->flushAll(); 381 break; 382 383 case IPR_DTB_IAP: 384 // really a control write 385 ipr[idx] = 0; 386 387 getDTBPtr(tc)->flushProcesses(); 388 break; 389 390 case IPR_DTB_IS: 391 // really a control write 392 ipr[idx] = val; 393 394 getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); 395 break; 396 397 case IPR_DTB_TAG: { 398 struct TlbEntry entry; 399 400 // FIXME: granularity hints NYI... 401 if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) 402 panic("PTE GH field != 0"); 403 404 // write entire quad 405 ipr[idx] = val; 406 407 // construct PTE for new entry 408 entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]); 409 entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); 410 entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); 411 entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); 412 entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); 413 entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); 414 entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); 415 416 // insert new TAG/PTE value into data TLB 417 getDTBPtr(tc)->insert(val, entry); 418 } 419 break; 420 421 case IPR_ITB_PTE: { 422 struct TlbEntry entry; 423 424 // FIXME: granularity hints NYI... 425 if (ITB_PTE_GH(val) != 0) 426 panic("PTE GH field != 0"); 427 428 // write entire quad 429 ipr[idx] = val; 430 431 // construct PTE for new entry 432 entry.ppn = ITB_PTE_PPN(val); 433 entry.xre = ITB_PTE_XRE(val); 434 entry.xwe = 0; 435 entry.fonr = ITB_PTE_FONR(val); 436 entry.fonw = ITB_PTE_FONW(val); 437 entry.asma = ITB_PTE_ASMA(val); 438 entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); 439 440 // insert new TAG/PTE value into data TLB 441 getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry); 442 } 443 break; 444 445 case IPR_ITB_IA: 446 // really a control write 447 ipr[idx] = 0; 448 449 getITBPtr(tc)->flushAll(); 450 break; 451 452 case IPR_ITB_IAP: 453 // really a control write 454 ipr[idx] = 0; 455 456 getITBPtr(tc)->flushProcesses(); 457 break; 458 459 case IPR_ITB_IS: 460 // really a control write 461 ipr[idx] = val; 462 463 getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); 464 break; 465 466 default: 467 // invalid IPR 468 panic("Tried to write to invalid ipr %d\n", idx); 469 } 470 471 // no error... 472} 473 474void 475copyIprs(ThreadContext *src, ThreadContext *dest) 476{ 477 for (int i = 0; i < NumInternalProcRegs; ++i) 478 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 479} 480 481} // namespace AlphaISA 482 483using namespace AlphaISA; 484 485Fault 486SimpleThread::hwrei() 487{ 488 PCState pc = pcState(); 489 if (!(pc.pc() & 0x3)) 490 return std::make_shared<UnimplementedOpcodeFault>(); 491 492 pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR)); 493 pcState(pc); 494 495 CPA::cpa()->swAutoBegin(tc, pc.npc()); 496 497 if (kernelStats) 498 kernelStats->hwrei(); 499 500 // FIXME: XXX check for interrupts? XXX 501 return NoFault; 502} 503 504/** 505 * Check for special simulator handling of specific PAL calls. 506 * If return value is false, actual PAL call will be suppressed. 507 */ 508bool 509SimpleThread::simPalCheck(int palFunc) 510{ 511 if (kernelStats) 512 kernelStats->callpal(palFunc, tc); 513 514 switch (palFunc) { 515 case PAL::halt: 516 halt(); 517 if (--System::numSystemsRunning == 0) 518 exitSimLoop("all cpus halted"); 519 break; 520 521 case PAL::bpt: 522 case PAL::bugchk: 523 if (system->breakpoint()) 524 return false; 525 break; 526 } 527 528 return true; 529} 530