ev5.cc revision 10664:61a0b02aa800 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#include "arch/alpha/faults.hh"
33#include "arch/alpha/isa_traits.hh"
34#include "arch/alpha/kernel_stats.hh"
35#include "arch/alpha/osfpal.hh"
36#include "arch/alpha/tlb.hh"
37#include "base/cp_annotate.hh"
38#include "base/debug.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/thread_context.hh"
42#include "sim/sim_exit.hh"
43
44namespace AlphaISA {
45
46////////////////////////////////////////////////////////////////////////
47//
48//  Machine dependent functions
49//
50void
51initCPU(ThreadContext *tc, int cpuId)
52{
53    initIPRs(tc, cpuId);
54
55    tc->setIntReg(16, cpuId);
56    tc->setIntReg(0, cpuId);
57
58    AlphaFault *reset = new ResetFault;
59
60    tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect());
61
62    delete reset;
63}
64
65template <class CPU>
66void
67zeroRegisters(CPU *cpu)
68{
69    // Insure ISA semantics
70    // (no longer very clean due to the change in setIntReg() in the
71    // cpu model.  Consider changing later.)
72    cpu->thread->setIntReg(ZeroReg, 0);
73    cpu->thread->setFloatReg(ZeroReg, 0.0);
74}
75
76////////////////////////////////////////////////////////////////////////
77//
78//
79//
80void
81initIPRs(ThreadContext *tc, int cpuId)
82{
83    for (int i = 0; i < NumInternalProcRegs; ++i) {
84        tc->setMiscRegNoEffect(i, 0);
85    }
86
87    tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
88    tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
89    tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
90}
91
92MiscReg
93ISA::readIpr(int idx, ThreadContext *tc)
94{
95    uint64_t retval = 0;        // return value, default 0
96
97    switch (idx) {
98      case IPR_PALtemp0:
99      case IPR_PALtemp1:
100      case IPR_PALtemp2:
101      case IPR_PALtemp3:
102      case IPR_PALtemp4:
103      case IPR_PALtemp5:
104      case IPR_PALtemp6:
105      case IPR_PALtemp7:
106      case IPR_PALtemp8:
107      case IPR_PALtemp9:
108      case IPR_PALtemp10:
109      case IPR_PALtemp11:
110      case IPR_PALtemp12:
111      case IPR_PALtemp13:
112      case IPR_PALtemp14:
113      case IPR_PALtemp15:
114      case IPR_PALtemp16:
115      case IPR_PALtemp17:
116      case IPR_PALtemp18:
117      case IPR_PALtemp19:
118      case IPR_PALtemp20:
119      case IPR_PALtemp21:
120      case IPR_PALtemp22:
121      case IPR_PALtemp23:
122      case IPR_PAL_BASE:
123
124      case IPR_IVPTBR:
125      case IPR_DC_MODE:
126      case IPR_MAF_MODE:
127      case IPR_ISR:
128      case IPR_EXC_ADDR:
129      case IPR_IC_PERR_STAT:
130      case IPR_DC_PERR_STAT:
131      case IPR_MCSR:
132      case IPR_ASTRR:
133      case IPR_ASTER:
134      case IPR_SIRR:
135      case IPR_ICSR:
136      case IPR_ICM:
137      case IPR_DTB_CM:
138      case IPR_IPLR:
139      case IPR_INTID:
140      case IPR_PMCTR:
141        // no side-effect
142        retval = ipr[idx];
143        break;
144
145      case IPR_CC:
146        retval |= ipr[idx] & ULL(0xffffffff00000000);
147        retval |= tc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
148        break;
149
150      case IPR_VA:
151        retval = ipr[idx];
152        break;
153
154      case IPR_VA_FORM:
155      case IPR_MM_STAT:
156      case IPR_IFAULT_VA_FORM:
157      case IPR_EXC_MASK:
158      case IPR_EXC_SUM:
159        retval = ipr[idx];
160        break;
161
162      case IPR_DTB_PTE:
163        {
164            TlbEntry &entry = tc->getDTBPtr()->index(1);
165
166            retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
167            retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
168            retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
169            retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
170            retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
171            retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
172            retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
173        }
174        break;
175
176        // write only registers
177      case IPR_HWINT_CLR:
178      case IPR_SL_XMIT:
179      case IPR_DC_FLUSH:
180      case IPR_IC_FLUSH:
181      case IPR_ALT_MODE:
182      case IPR_DTB_IA:
183      case IPR_DTB_IAP:
184      case IPR_ITB_IA:
185      case IPR_ITB_IAP:
186        panic("Tried to read write only register %d\n", idx);
187        break;
188
189      default:
190        // invalid IPR
191        panic("Tried to read from invalid ipr %d\n", idx);
192        break;
193    }
194
195    return retval;
196}
197
198// Cause the simulator to break when changing to the following IPL
199int break_ipl = -1;
200
201void
202ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
203{
204    switch (idx) {
205      case IPR_PALtemp0:
206      case IPR_PALtemp1:
207      case IPR_PALtemp2:
208      case IPR_PALtemp3:
209      case IPR_PALtemp4:
210      case IPR_PALtemp5:
211      case IPR_PALtemp6:
212      case IPR_PALtemp7:
213      case IPR_PALtemp8:
214      case IPR_PALtemp9:
215      case IPR_PALtemp10:
216      case IPR_PALtemp11:
217      case IPR_PALtemp12:
218      case IPR_PALtemp13:
219      case IPR_PALtemp14:
220      case IPR_PALtemp15:
221      case IPR_PALtemp16:
222      case IPR_PALtemp17:
223      case IPR_PALtemp18:
224      case IPR_PALtemp19:
225      case IPR_PALtemp20:
226      case IPR_PALtemp21:
227      case IPR_PALtemp22:
228      case IPR_PAL_BASE:
229      case IPR_IC_PERR_STAT:
230      case IPR_DC_PERR_STAT:
231      case IPR_PMCTR:
232        // write entire quad w/ no side-effect
233        ipr[idx] = val;
234        break;
235
236      case IPR_CC_CTL:
237        // This IPR resets the cycle counter.  We assume this only
238        // happens once... let's verify that.
239        assert(ipr[idx] == 0);
240        ipr[idx] = 1;
241        break;
242
243      case IPR_CC:
244        // This IPR only writes the upper 64 bits.  It's ok to write
245        // all 64 here since we mask out the lower 32 in rpcc (see
246        // isa_desc).
247        ipr[idx] = val;
248        break;
249
250      case IPR_PALtemp23:
251        // write entire quad w/ no side-effect
252        if (tc->getKernelStats())
253            tc->getKernelStats()->context(ipr[idx], val, tc);
254        ipr[idx] = val;
255        break;
256
257      case IPR_DTB_PTE:
258        // write entire quad w/ no side-effect, tag is forthcoming
259        ipr[idx] = val;
260        break;
261
262      case IPR_EXC_ADDR:
263        // second least significant bit in PC is always zero
264        ipr[idx] = val & ~2;
265        break;
266
267      case IPR_ASTRR:
268      case IPR_ASTER:
269        // only write least significant four bits - privilege mask
270        ipr[idx] = val & 0xf;
271        break;
272
273      case IPR_IPLR:
274#ifdef DEBUG
275        if (break_ipl != -1 && break_ipl == (int)(val & 0x1f))
276            Debug::breakpoint();
277#endif
278
279        // only write least significant five bits - interrupt level
280        ipr[idx] = val & 0x1f;
281        if (tc->getKernelStats())
282            tc->getKernelStats()->swpipl(ipr[idx]);
283        break;
284
285      case IPR_DTB_CM:
286        if (val & 0x18) {
287            if (tc->getKernelStats())
288                tc->getKernelStats()->mode(Kernel::user, tc);
289        } else {
290            if (tc->getKernelStats())
291                tc->getKernelStats()->mode(Kernel::kernel, tc);
292        }
293
294      case IPR_ICM:
295        // only write two mode bits - processor mode
296        ipr[idx] = val & 0x18;
297        break;
298
299      case IPR_ALT_MODE:
300        // only write two mode bits - processor mode
301        ipr[idx] = val & 0x18;
302        break;
303
304      case IPR_MCSR:
305        // more here after optimization...
306        ipr[idx] = val;
307        break;
308
309      case IPR_SIRR:
310        // only write software interrupt mask
311        ipr[idx] = val & 0x7fff0;
312        break;
313
314      case IPR_ICSR:
315        ipr[idx] = val & ULL(0xffffff0300);
316        break;
317
318      case IPR_IVPTBR:
319      case IPR_MVPTBR:
320        ipr[idx] = val & ULL(0xffffffffc0000000);
321        break;
322
323      case IPR_DC_TEST_CTL:
324        ipr[idx] = val & 0x1ffb;
325        break;
326
327      case IPR_DC_MODE:
328      case IPR_MAF_MODE:
329        ipr[idx] = val & 0x3f;
330        break;
331
332      case IPR_ITB_ASN:
333        ipr[idx] = val & 0x7f0;
334        break;
335
336      case IPR_DTB_ASN:
337        ipr[idx] = val & ULL(0xfe00000000000000);
338        break;
339
340      case IPR_EXC_SUM:
341      case IPR_EXC_MASK:
342        // any write to this register clears it
343        ipr[idx] = 0;
344        break;
345
346      case IPR_INTID:
347      case IPR_SL_RCV:
348      case IPR_MM_STAT:
349      case IPR_ITB_PTE_TEMP:
350      case IPR_DTB_PTE_TEMP:
351        // read-only registers
352        panic("Tried to write read only ipr %d\n", idx);
353
354      case IPR_HWINT_CLR:
355      case IPR_SL_XMIT:
356      case IPR_DC_FLUSH:
357      case IPR_IC_FLUSH:
358        // the following are write only
359        ipr[idx] = val;
360        break;
361
362      case IPR_DTB_IA:
363        // really a control write
364        ipr[idx] = 0;
365
366        tc->getDTBPtr()->flushAll();
367        break;
368
369      case IPR_DTB_IAP:
370        // really a control write
371        ipr[idx] = 0;
372
373        tc->getDTBPtr()->flushProcesses();
374        break;
375
376      case IPR_DTB_IS:
377        // really a control write
378        ipr[idx] = val;
379
380        tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
381        break;
382
383      case IPR_DTB_TAG: {
384          struct TlbEntry entry;
385
386          // FIXME: granularity hints NYI...
387          if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
388              panic("PTE GH field != 0");
389
390          // write entire quad
391          ipr[idx] = val;
392
393          // construct PTE for new entry
394          entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
395          entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
396          entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
397          entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
398          entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
399          entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
400          entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
401
402          // insert new TAG/PTE value into data TLB
403          tc->getDTBPtr()->insert(val, entry);
404      }
405        break;
406
407      case IPR_ITB_PTE: {
408          struct TlbEntry entry;
409
410          // FIXME: granularity hints NYI...
411          if (ITB_PTE_GH(val) != 0)
412              panic("PTE GH field != 0");
413
414          // write entire quad
415          ipr[idx] = val;
416
417          // construct PTE for new entry
418          entry.ppn = ITB_PTE_PPN(val);
419          entry.xre = ITB_PTE_XRE(val);
420          entry.xwe = 0;
421          entry.fonr = ITB_PTE_FONR(val);
422          entry.fonw = ITB_PTE_FONW(val);
423          entry.asma = ITB_PTE_ASMA(val);
424          entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
425
426          // insert new TAG/PTE value into data TLB
427          tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry);
428      }
429        break;
430
431      case IPR_ITB_IA:
432        // really a control write
433        ipr[idx] = 0;
434
435        tc->getITBPtr()->flushAll();
436        break;
437
438      case IPR_ITB_IAP:
439        // really a control write
440        ipr[idx] = 0;
441
442        tc->getITBPtr()->flushProcesses();
443        break;
444
445      case IPR_ITB_IS:
446        // really a control write
447        ipr[idx] = val;
448
449        tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
450        break;
451
452      default:
453        // invalid IPR
454        panic("Tried to write to invalid ipr %d\n", idx);
455    }
456
457    // no error...
458}
459
460void
461copyIprs(ThreadContext *src, ThreadContext *dest)
462{
463    for (int i = 0; i < NumInternalProcRegs; ++i)
464        dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
465}
466
467} // namespace AlphaISA
468
469using namespace AlphaISA;
470
471Fault
472SimpleThread::hwrei()
473{
474    PCState pc = pcState();
475    if (!(pc.pc() & 0x3))
476        return std::make_shared<UnimplementedOpcodeFault>();
477
478    pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
479    pcState(pc);
480
481    CPA::cpa()->swAutoBegin(tc, pc.npc());
482
483    if (kernelStats)
484        kernelStats->hwrei();
485
486    // FIXME: XXX check for interrupts? XXX
487    return NoFault;
488}
489
490/**
491 * Check for special simulator handling of specific PAL calls.
492 * If return value is false, actual PAL call will be suppressed.
493 */
494bool
495SimpleThread::simPalCheck(int palFunc)
496{
497    if (kernelStats)
498        kernelStats->callpal(palFunc, tc);
499
500    switch (palFunc) {
501      case PAL::halt:
502        halt();
503        if (--System::numSystemsRunning == 0)
504            exitSimLoop("all cpus halted");
505        break;
506
507      case PAL::bpt:
508      case PAL::bugchk:
509        if (system->breakpoint())
510            return false;
511        break;
512    }
513
514    return true;
515}
516