SConscript revision 7756
1955SN/A# -*- mode:python -*-
2955SN/A
31762SN/A# Copyright (c) 2006 The Regents of The University of Michigan
4955SN/A# All rights reserved.
5955SN/A#
6955SN/A# Redistribution and use in source and binary forms, with or without
7955SN/A# modification, are permitted provided that the following conditions are
8955SN/A# met: redistributions of source code must retain the above copyright
9955SN/A# notice, this list of conditions and the following disclaimer;
10955SN/A# redistributions in binary form must reproduce the above copyright
11955SN/A# notice, this list of conditions and the following disclaimer in the
12955SN/A# documentation and/or other materials provided with the distribution;
13955SN/A# neither the name of the copyright holders nor the names of its
14955SN/A# contributors may be used to endorse or promote products derived from
15955SN/A# this software without specific prior written permission.
16955SN/A#
17955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu#
294762Snate@binkert.org# Authors: Steve Reinhardt
30955SN/A
315522Snate@binkert.orgimport sys
326143Snate@binkert.org
334762Snate@binkert.orgImport('*')
345522Snate@binkert.org
35955SN/A#################################################################
365522Snate@binkert.org#
37955SN/A# ISA "switch header" generation.
385522Snate@binkert.org#
394202Sbinkertn@umich.edu# Auto-generate arch headers that include the right ISA-specific
405742Snate@binkert.org# header based on the setting of THE_ISA preprocessor variable.
41955SN/A#
424381Sbinkertn@umich.edu#################################################################
434381Sbinkertn@umich.edu
448334Snate@binkert.org# List of headers to generate
45955SN/Aisa_switch_hdrs = Split('''
46955SN/A        faults.hh
474202Sbinkertn@umich.edu        interrupts.hh
48955SN/A	isa.hh
494382Sbinkertn@umich.edu        isa_traits.hh
504382Sbinkertn@umich.edu        kernel_stats.hh
514382Sbinkertn@umich.edu        locked_mem.hh
526654Snate@binkert.org        microcode_rom.hh
535517Snate@binkert.org        mmaped_ipr.hh
548614Sgblack@eecs.umich.edu        mt.hh
557674Snate@binkert.org        process.hh
566143Snate@binkert.org        predecoder.hh
576143Snate@binkert.org        registers.hh
586143Snate@binkert.org        remote_gdb.hh
598233Snate@binkert.org        stacktrace.hh
608233Snate@binkert.org        tlb.hh
618233Snate@binkert.org        types.hh
628233Snate@binkert.org        utility.hh
638233Snate@binkert.org        vtophys.hh
648334Snate@binkert.org        ''')
658334Snate@binkert.org
668233Snate@binkert.org# Set up this directory to support switching headers
678233Snate@binkert.orgmake_switching_dir('arch', isa_switch_hdrs, env)
688233Snate@binkert.org
698233Snate@binkert.org#################################################################
708233Snate@binkert.org#
718233Snate@binkert.org# Include architecture-specific files.
726143Snate@binkert.org#
738233Snate@binkert.org#################################################################
748233Snate@binkert.org
758233Snate@binkert.org#
766143Snate@binkert.org# Build a SCons scanner for ISA files
776143Snate@binkert.org#
786143Snate@binkert.orgimport SCons.Scanner
796143Snate@binkert.org
808233Snate@binkert.orgisa_scanner = SCons.Scanner.Classic("ISAScan",
818233Snate@binkert.org                                    [".isa", ".ISA"],
828233Snate@binkert.org                                    "SRCDIR",
836143Snate@binkert.org                                    r'^\s*##include\s+"([\w/.-]*)"')
848233Snate@binkert.org
858233Snate@binkert.orgenv.Append(SCANNERS = isa_scanner)
868233Snate@binkert.org
878233Snate@binkert.org#
886143Snate@binkert.org# Now create a Builder object that uses isa_parser.py to generate C++
896143Snate@binkert.org# output from the ISA description (*.isa) files.
906143Snate@binkert.org#
914762Snate@binkert.org
926143Snate@binkert.org# The emitter patches up the sources & targets to include the
938233Snate@binkert.org# autogenerated files as targets and isa parser itself as a source.
948233Snate@binkert.orgdef isa_desc_emitter(target, source, env):
958233Snate@binkert.org    cpu_models = list(env['CPU_MODELS'])
968233Snate@binkert.org    if env['USE_CHECKER']:
978233Snate@binkert.org        cpu_models.append('CheckerCPU')
986143Snate@binkert.org
998233Snate@binkert.org    # Several files are generated from the ISA description.
1008233Snate@binkert.org    # We always get the basic decoder and header file.
1018233Snate@binkert.org    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
1028233Snate@binkert.org    # We also get an execute file for each selected CPU model.
1036143Snate@binkert.org    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
1046143Snate@binkert.org
1056143Snate@binkert.org    return target, source + [ Value(m) for m in cpu_models ]
1066143Snate@binkert.org
1076143Snate@binkert.orgARCH_DIR = Dir('.')
1086143Snate@binkert.org
1096143Snate@binkert.org# import ply here because SCons screws with sys.path when performing actions.
1106143Snate@binkert.orgimport ply
1116143Snate@binkert.org
1127065Snate@binkert.orgdef isa_desc_action_func(target, source, env):
1136143Snate@binkert.org    # Add the current directory to the system path so we can import files
1148233Snate@binkert.org    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
1158233Snate@binkert.org    import isa_parser
1168233Snate@binkert.org
1178233Snate@binkert.org    models = [ s.get_contents() for s in source[1:] ]
1188233Snate@binkert.org    cpu_models = [CpuModel.dict[cpu] for cpu in models]
1198233Snate@binkert.org    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
1208233Snate@binkert.org    parser.parse_isa_desc(source[0].abspath)
1218233Snate@binkert.orgisa_desc_action = MakeAction(isa_desc_action_func, " [ISA DESC] $STRIP_SOURCE")
1228233Snate@binkert.org
1238233Snate@binkert.org# Also include the CheckerCPU as one of the models if it is being
1248233Snate@binkert.org# enabled via command line.
1258233Snate@binkert.orgisa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
1268233Snate@binkert.org
1278233Snate@binkert.orgenv.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
1288233Snate@binkert.org
1298233Snate@binkert.orgTraceFlag('IntRegs')
1308233Snate@binkert.orgTraceFlag('FloatRegs')
1318233Snate@binkert.orgTraceFlag('MiscRegs')
1328233Snate@binkert.orgCompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
1338233Snate@binkert.org