SConscript revision 4781
111723Sar4jc@virginia.edu# -*- mode:python -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu# Copyright (c) 2006 The Regents of The University of Michigan 411723Sar4jc@virginia.edu# All rights reserved. 511723Sar4jc@virginia.edu# 611723Sar4jc@virginia.edu# Redistribution and use in source and binary forms, with or without 711723Sar4jc@virginia.edu# modification, are permitted provided that the following conditions are 811723Sar4jc@virginia.edu# met: redistributions of source code must retain the above copyright 911723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer; 1011723Sar4jc@virginia.edu# redistributions in binary form must reproduce the above copyright 1111723Sar4jc@virginia.edu# notice, this list of conditions and the following disclaimer in the 1211723Sar4jc@virginia.edu# documentation and/or other materials provided with the distribution; 1311723Sar4jc@virginia.edu# neither the name of the copyright holders nor the names of its 1411723Sar4jc@virginia.edu# contributors may be used to endorse or promote products derived from 1511723Sar4jc@virginia.edu# this software without specific prior written permission. 1611723Sar4jc@virginia.edu# 1711723Sar4jc@virginia.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1811723Sar4jc@virginia.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1911723Sar4jc@virginia.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2011723Sar4jc@virginia.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2111723Sar4jc@virginia.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2211723Sar4jc@virginia.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2311723Sar4jc@virginia.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2411723Sar4jc@virginia.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2511723Sar4jc@virginia.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2611723Sar4jc@virginia.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2711723Sar4jc@virginia.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2811723Sar4jc@virginia.edu# 2911723Sar4jc@virginia.edu# Authors: Steve Reinhardt 3011723Sar4jc@virginia.edu 3111723Sar4jc@virginia.eduimport sys 3211723Sar4jc@virginia.edu 3311723Sar4jc@virginia.eduImport('*') 3411723Sar4jc@virginia.edu 3511723Sar4jc@virginia.edu################################################################# 3611723Sar4jc@virginia.edu# 3711723Sar4jc@virginia.edu# ISA "switch header" generation. 3811723Sar4jc@virginia.edu# 3911723Sar4jc@virginia.edu# Auto-generate arch headers that include the right ISA-specific 4011723Sar4jc@virginia.edu# header based on the setting of THE_ISA preprocessor variable. 4111723Sar4jc@virginia.edu# 4211723Sar4jc@virginia.edu################################################################# 4311723Sar4jc@virginia.edu 4411723Sar4jc@virginia.edu# List of headers to generate 4511723Sar4jc@virginia.eduisa_switch_hdrs = Split(''' 4611723Sar4jc@virginia.edu arguments.hh 4711723Sar4jc@virginia.edu faults.hh 4811723Sar4jc@virginia.edu interrupts.hh 4911723Sar4jc@virginia.edu isa_traits.hh 5011723Sar4jc@virginia.edu kernel_stats.hh 5111723Sar4jc@virginia.edu locked_mem.hh 5211723Sar4jc@virginia.edu mmaped_ipr.hh 5311723Sar4jc@virginia.edu process.hh 5411723Sar4jc@virginia.edu predecoder.hh 5511723Sar4jc@virginia.edu regfile.hh 5611723Sar4jc@virginia.edu remote_gdb.hh 5711723Sar4jc@virginia.edu stacktrace.hh 5811723Sar4jc@virginia.edu syscallreturn.hh 5911723Sar4jc@virginia.edu tlb.hh 6011723Sar4jc@virginia.edu types.hh 6111723Sar4jc@virginia.edu utility.hh 6211723Sar4jc@virginia.edu vtophys.hh 63 ''') 64 65# Set up this directory to support switching headers 66make_switching_dir('arch', isa_switch_hdrs, env) 67 68################################################################# 69# 70# Include architecture-specific files. 71# 72################################################################# 73 74# 75# Build a SCons scanner for ISA files 76# 77import SCons.Scanner 78 79isa_scanner = SCons.Scanner.Classic("ISAScan", 80 [".isa", ".ISA"], 81 "SRCDIR", 82 r'^\s*##include\s+"([\w/.-]*)"') 83 84env.Append(SCANNERS = isa_scanner) 85 86# 87# Now create a Builder object that uses isa_parser.py to generate C++ 88# output from the ISA description (*.isa) files. 89# 90 91# Convert to File node to fix path 92isa_parser = File('isa_parser.py') 93cpu_models_file = File('../cpu/cpu_models.py') 94 95# This sucks in the defintions of the CpuModel objects. 96execfile(cpu_models_file.srcnode().abspath) 97 98# Several files are generated from the ISA description. 99# We always get the basic decoder and header file. 100isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh' ] 101# We also get an execute file for each selected CPU model. 102isa_desc_gen_files += [CpuModel.dict[cpu].filename 103 for cpu in env['CPU_MODELS']] 104 105# Also include the CheckerCPU as one of the models if it is being 106# enabled via command line. 107if env['USE_CHECKER']: 108 isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] 109 110# The emitter patches up the sources & targets to include the 111# autogenerated files as targets and isa parser itself as a source. 112def isa_desc_emitter(target, source, env): 113 return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 114 115# Pieces are in place, so create the builder. 116python = sys.executable # use same Python binary used to run scons 117 118# Also include the CheckerCPU as one of the models if it is being 119# enabled via command line. 120if env['USE_CHECKER']: 121 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', 122 emitter = isa_desc_emitter) 123else: 124 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 125 emitter = isa_desc_emitter) 126 127env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 128