SConscript revision 4182
16019Shines@cs.fsu.edu# -*- mode:python -*-
26019Shines@cs.fsu.edu
37100Sgblack@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
47100Sgblack@eecs.umich.edu# All rights reserved.
57100Sgblack@eecs.umich.edu#
67100Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
77100Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are
87100Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright
97100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
107100Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
117100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
127100Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution;
137100Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its
147100Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from
156019Shines@cs.fsu.edu# this software without specific prior written permission.
166019Shines@cs.fsu.edu#
176019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
186019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
196019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
206019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
216019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
226019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
236019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
246019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
256019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
266019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
276019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
286019Shines@cs.fsu.edu#
296019Shines@cs.fsu.edu# Authors: Steve Reinhardt
306019Shines@cs.fsu.edu
316019Shines@cs.fsu.eduimport os.path, sys
326019Shines@cs.fsu.edu
336019Shines@cs.fsu.edu# Import build environment variable from SConstruct.
346019Shines@cs.fsu.eduImport('env')
356019Shines@cs.fsu.edu
366019Shines@cs.fsu.edu# Right now there are no source files immediately in this directory
376019Shines@cs.fsu.edusources = []
386019Shines@cs.fsu.edu
396019Shines@cs.fsu.edu#################################################################
406019Shines@cs.fsu.edu#
416019Shines@cs.fsu.edu# ISA "switch header" generation.
426757SAli.Saidi@ARM.com#
436019Shines@cs.fsu.edu# Auto-generate arch headers that include the right ISA-specific
446019Shines@cs.fsu.edu# header based on the setting of THE_ISA preprocessor variable.
456019Shines@cs.fsu.edu#
466019Shines@cs.fsu.edu#################################################################
476019Shines@cs.fsu.edu
486019Shines@cs.fsu.edu# List of headers to generate
496019Shines@cs.fsu.eduisa_switch_hdrs = Split('''
506019Shines@cs.fsu.edu	arguments.hh
517170Sgblack@eecs.umich.edu	faults.hh
526253Sgblack@eecs.umich.edu	interrupts.hh
537202Sgblack@eecs.umich.edu	isa_traits.hh
546253Sgblack@eecs.umich.edu	kernel_stats.hh
556253Sgblack@eecs.umich.edu        locked_mem.hh
567396Sgblack@eecs.umich.edu        mmaped_ipr.hh
577405SAli.Saidi@ARM.com	process.hh
587259Sgblack@eecs.umich.edu	predecoder.hh
597423Sgblack@eecs.umich.edu	regfile.hh
606397Sgblack@eecs.umich.edu	remote_gdb.hh
616019Shines@cs.fsu.edu	stacktrace.hh
626757SAli.Saidi@ARM.com	syscallreturn.hh
637752SWilliam.Wang@arm.com	tlb.hh
646019Shines@cs.fsu.edu	types.hh
656397Sgblack@eecs.umich.edu	utility.hh
666019Shines@cs.fsu.edu	vtophys.hh
676397Sgblack@eecs.umich.edu        ''')
686019Shines@cs.fsu.edu
697404SAli.Saidi@ARM.com# Set up this directory to support switching headers
706735Sgblack@eecs.umich.eduenv.make_switching_dir('arch', isa_switch_hdrs, env)
717100Sgblack@eecs.umich.edu
726019Shines@cs.fsu.edu#################################################################
736757SAli.Saidi@ARM.com#
746757SAli.Saidi@ARM.com# Include architecture-specific files.
756757SAli.Saidi@ARM.com#
767694SAli.Saidi@ARM.com#################################################################
777585SAli.Saidi@arm.com
787404SAli.Saidi@ARM.com#
796757SAli.Saidi@ARM.com# Build a SCons scanner for ISA files
806757SAli.Saidi@ARM.com#
816757SAli.Saidi@ARM.comimport SCons.Scanner
826019Shines@cs.fsu.edu
836019Shines@cs.fsu.eduisa_scanner = SCons.Scanner.Classic("ISAScan",
846019Shines@cs.fsu.edu                                    [".isa", ".ISA"],
856019Shines@cs.fsu.edu                                    "SRCDIR",
866019Shines@cs.fsu.edu                                    r'^\s*##include\s+"([\w/.-]*)"')
876019Shines@cs.fsu.edu
886019Shines@cs.fsu.eduenv.Append(SCANNERS = isa_scanner)
896019Shines@cs.fsu.edu
906019Shines@cs.fsu.edu#
916019Shines@cs.fsu.edu# Now create a Builder object that uses isa_parser.py to generate C++
926019Shines@cs.fsu.edu# output from the ISA description (*.isa) files.
936019Shines@cs.fsu.edu#
94
95# Convert to File node to fix path
96isa_parser = File('isa_parser.py')
97cpu_models_file = File('../cpu/cpu_models.py')
98
99# This sucks in the defintions of the CpuModel objects.
100execfile(cpu_models_file.srcnode().abspath)
101
102# Several files are generated from the ISA description.
103# We always get the basic decoder and header file.
104isa_desc_gen_files = Split('decoder.cc decoder.hh')
105# We also get an execute file for each selected CPU model.
106isa_desc_gen_files += [CpuModel.dict[cpu].filename
107                       for cpu in env['CPU_MODELS']]
108
109# Also include the CheckerCPU as one of the models if it is being
110# enabled via command line.
111if env['USE_CHECKER']:
112    isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename]
113
114# The emitter patches up the sources & targets to include the
115# autogenerated files as targets and isa parser itself as a source.
116def isa_desc_emitter(target, source, env):
117    return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
118
119# Pieces are in place, so create the builder.
120python = sys.executable  # use same Python binary used to run scons
121
122# Also include the CheckerCPU as one of the models if it is being
123# enabled via command line.
124if env['USE_CHECKER']:
125    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
126                               emitter = isa_desc_emitter)
127else:
128    isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
129                               emitter = isa_desc_emitter)
130
131env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
132
133#
134# Now include other ISA-specific sources from the ISA subdirectories.
135#
136
137isa = env['TARGET_ISA'] # someday this may be a list of ISAs
138
139# Let the target architecture define what additional sources it needs
140sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env')
141
142Return('sources')
143