SConscript revision 3520
16691Stjones1@inf.ed.ac.uk# -*- mode:python -*- 26691Stjones1@inf.ed.ac.uk 36691Stjones1@inf.ed.ac.uk# Copyright (c) 2006 The Regents of The University of Michigan 46691Stjones1@inf.ed.ac.uk# All rights reserved. 56691Stjones1@inf.ed.ac.uk# 66691Stjones1@inf.ed.ac.uk# Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk# modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk# met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk# redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk# documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk# neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk# contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk# this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk# 176691Stjones1@inf.ed.ac.uk# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk# 296691Stjones1@inf.ed.ac.uk# Authors: Steve Reinhardt 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.ukimport os.path, sys 326691Stjones1@inf.ed.ac.uk 336691Stjones1@inf.ed.ac.uk# Import build environment variable from SConstruct. 346691Stjones1@inf.ed.ac.ukImport('env') 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.uk# Right now there are no source files immediately in this directory 379022Sgblack@eecs.umich.edusources = [] 386691Stjones1@inf.ed.ac.uk 396691Stjones1@inf.ed.ac.uk################################################################# 406691Stjones1@inf.ed.ac.uk# 416691Stjones1@inf.ed.ac.uk# ISA "switch header" generation. 426691Stjones1@inf.ed.ac.uk# 436691Stjones1@inf.ed.ac.uk# Auto-generate arch headers that include the right ISA-specific 448745Sgblack@eecs.umich.edu# header based on the setting of THE_ISA preprocessor variable. 458772Sgblack@eecs.umich.edu# 468772Sgblack@eecs.umich.edu################################################################# 476691Stjones1@inf.ed.ac.uk 488772Sgblack@eecs.umich.edu# List of headers to generate 498792Sgblack@eecs.umich.eduisa_switch_hdrs = Split(''' 506691Stjones1@inf.ed.ac.uk arguments.hh 517506Stjones1@inf.ed.ac.uk faults.hh 528759Sgblack@eecs.umich.edu interrupts.hh 536691Stjones1@inf.ed.ac.uk isa_traits.hh 548745Sgblack@eecs.umich.edu locked_mem.hh 556691Stjones1@inf.ed.ac.uk process.hh 568745Sgblack@eecs.umich.edu regfile.hh 578335Snate@binkert.org stacktrace.hh 586691Stjones1@inf.ed.ac.uk syscallreturn.hh 596691Stjones1@inf.ed.ac.uk tlb.hh 606691Stjones1@inf.ed.ac.uk types.hh 616691Stjones1@inf.ed.ac.uk utility.hh 626691Stjones1@inf.ed.ac.uk vtophys.hh 636691Stjones1@inf.ed.ac.uk ''') 646691Stjones1@inf.ed.ac.uk 656691Stjones1@inf.ed.ac.uk# Generate the header. target[0] is the full path of the output 666691Stjones1@inf.ed.ac.uk# header to generate. 'source' is a dummy variable, since we get the 67# list of ISAs from env['ALL_ISA_LIST']. 68def gen_switch_hdr(target, source, env): 69 fname = str(target[0]) 70 basename = os.path.basename(fname) 71 f = open(fname, 'w') 72 f.write('#include "arch/isa_specific.hh"\n') 73 cond = '#if' 74 for isa in env['ALL_ISA_LIST']: 75 f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n' 76 % (cond, isa.upper(), isa, basename)) 77 cond = '#elif' 78 f.write('#else\n#error "THE_ISA not set"\n#endif\n') 79 f.close() 80 return 0 81 82# String to print when generating header 83def gen_switch_hdr_string(target, source, env): 84 return "Generating ISA switch header " + str(target[0]) 85 86# Build SCons Action object. 'varlist' specifies env vars that this 87# action depends on; when env['ALL_ISA_LIST'] changes these actions 88# should get re-executed. 89switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string, 90 varlist=['ALL_ISA_LIST']) 91 92# Instantiate actions for each header 93for hdr in isa_switch_hdrs: 94 env.Command(hdr, [], switch_hdr_action) 95 96################################################################# 97# 98# Include architecture-specific files. 99# 100################################################################# 101 102# 103# Build a SCons scanner for ISA files 104# 105import SCons.Scanner 106 107isa_scanner = SCons.Scanner.Classic("ISAScan", 108 [".isa", ".ISA"], 109 "SRCDIR", 110 r'^\s*##include\s+"([\w/.-]*)"') 111 112env.Append(SCANNERS = isa_scanner) 113 114# 115# Now create a Builder object that uses isa_parser.py to generate C++ 116# output from the ISA description (*.isa) files. 117# 118 119# Convert to File node to fix path 120isa_parser = File('isa_parser.py') 121cpu_models_file = File('../cpu/cpu_models.py') 122 123# This sucks in the defintions of the CpuModel objects. 124execfile(cpu_models_file.srcnode().abspath) 125 126# Several files are generated from the ISA description. 127# We always get the basic decoder and header file. 128isa_desc_gen_files = Split('decoder.cc decoder.hh') 129# We also get an execute file for each selected CPU model. 130isa_desc_gen_files += [CpuModel.dict[cpu].filename 131 for cpu in env['CPU_MODELS']] 132 133# Also include the CheckerCPU as one of the models if it is being 134# enabled via command line. 135if env['USE_CHECKER']: 136 isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] 137 138# The emitter patches up the sources & targets to include the 139# autogenerated files as targets and isa parser itself as a source. 140def isa_desc_emitter(target, source, env): 141 return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 142 143# Pieces are in place, so create the builder. 144python = sys.executable # use same Python binary used to run scons 145 146# Also include the CheckerCPU as one of the models if it is being 147# enabled via command line. 148if env['USE_CHECKER']: 149 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', 150 emitter = isa_desc_emitter) 151else: 152 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 153 emitter = isa_desc_emitter) 154 155env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 156 157# 158# Now include other ISA-specific sources from the ISA subdirectories. 159# 160 161isa = env['TARGET_ISA'] # someday this may be a list of ISAs 162 163# Let the target architecture define what additional sources it needs 164sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env') 165 166Return('sources') 167