SConscript revision 2733
16019Shines@cs.fsu.edu# -*- mode:python -*- 26019Shines@cs.fsu.edu 310037SARM gem5 Developers# Copyright (c) 2006 The Regents of The University of Michigan 47100Sgblack@eecs.umich.edu# All rights reserved. 57100Sgblack@eecs.umich.edu# 67100Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 77100Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 87100Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 97100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 107100Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 117100Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 127100Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 137100Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 147100Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu# this software without specific prior written permission. 166019Shines@cs.fsu.edu# 176019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu# 296019Shines@cs.fsu.edu# Authors: Steve Reinhardt 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.eduimport os.path, sys 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu# Import build environment variable from SConstruct. 346019Shines@cs.fsu.eduImport('env') 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edu# Right now there are no source files immediately in this directory 376019Shines@cs.fsu.edusources = [] 386019Shines@cs.fsu.edu 396019Shines@cs.fsu.edu################################################################# 406019Shines@cs.fsu.edu# 416019Shines@cs.fsu.edu# ISA "switch header" generation. 426757SAli.Saidi@ARM.com# 436019Shines@cs.fsu.edu# Auto-generate arch headers that include the right ISA-specific 446019Shines@cs.fsu.edu# header based on the setting of THE_ISA preprocessor variable. 456019Shines@cs.fsu.edu# 466019Shines@cs.fsu.edu################################################################# 476019Shines@cs.fsu.edu 4811320Ssteve.reinhardt@amd.com# List of headers to generate 496019Shines@cs.fsu.eduisa_switch_hdrs = Split(''' 509022Sgblack@eecs.umich.edu arguments.hh 516019Shines@cs.fsu.edu constants.hh 5212640Sgiacomo.travaglini@arm.com faults.hh 5310037SARM gem5 Developers isa_traits.hh 5410037SARM gem5 Developers process.hh 557170Sgblack@eecs.umich.edu regfile.hh 566253Sgblack@eecs.umich.edu stacktrace.hh 5710037SARM gem5 Developers tlb.hh 587202Sgblack@eecs.umich.edu types.hh 5910037SARM gem5 Developers utility.hh 606253Sgblack@eecs.umich.edu vtophys.hh 6110611SAndreas.Sandberg@ARM.com ''') 626253Sgblack@eecs.umich.edu 637396Sgblack@eecs.umich.edu# Generate the header. target[0] is the full path of the output 6410037SARM gem5 Developers# header to generate. 'source' is a dummy variable, since we get the 658745Sgblack@eecs.umich.edu# list of ISAs from env['ALL_ISA_LIST']. 667405SAli.Saidi@ARM.comdef gen_switch_hdr(target, source, env): 6710461SAndreas.Sandberg@ARM.com fname = str(target[0]) 688782Sgblack@eecs.umich.edu basename = os.path.basename(fname) 698782Sgblack@eecs.umich.edu f = open(fname, 'w') 708782Sgblack@eecs.umich.edu f.write('#include "arch/isa_specific.hh"\n') 7110810Sbr@bsdpad.com cond = '#if' 7210810Sbr@bsdpad.com for isa in env['ALL_ISA_LIST']: 7310810Sbr@bsdpad.com f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n' 747259Sgblack@eecs.umich.edu % (cond, isa.upper(), isa, basename)) 758757Sgblack@eecs.umich.edu cond = '#elif' 7610461SAndreas.Sandberg@ARM.com f.write('#else\n#error "THE_ISA not set"\n#endif\n') 778782Sgblack@eecs.umich.edu f.close() 788757Sgblack@eecs.umich.edu return 0 7912531Sandreas.sandberg@arm.com 808777Sgblack@eecs.umich.edu# String to print when generating header 818782Sgblack@eecs.umich.edudef gen_switch_hdr_string(target, source, env): 828756Sgblack@eecs.umich.edu return "Generating ISA switch header " + str(target[0]) 8310037SARM gem5 Developers 8410037SARM gem5 Developers# Build SCons Action object. 'varlist' specifies env vars that this 856019Shines@cs.fsu.edu# action depends on; when env['ALL_ISA_LIST'] changes these actions 8612605Sgiacomo.travaglini@arm.com# should get re-executed. 876757SAli.Saidi@ARM.comswitch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string, 888757Sgblack@eecs.umich.edu varlist=['ALL_ISA_LIST']) 896019Shines@cs.fsu.edu 908745Sgblack@eecs.umich.edu# Instantiate actions for each header 919384SAndreas.Sandberg@arm.comfor hdr in isa_switch_hdrs: 926397Sgblack@eecs.umich.edu env.Command(hdr, [], switch_hdr_action) 9312531Sandreas.sandberg@arm.com 948782Sgblack@eecs.umich.edu################################################################# 956019Shines@cs.fsu.edu# 9610461SAndreas.Sandberg@ARM.com# Include architecture-specific files. 976397Sgblack@eecs.umich.edu# 988335Snate@binkert.org################################################################# 9912531Sandreas.sandberg@arm.com 1009023Sgblack@eecs.umich.edu# 1019023Sgblack@eecs.umich.edu# Build a SCons scanner for ISA files 10210461SAndreas.Sandberg@ARM.com# 1038335Snate@binkert.orgimport SCons.Scanner 1046019Shines@cs.fsu.edu 10510196SCurtis.Dunham@arm.comisa_scanner = SCons.Scanner.Classic("ISAScan", 10612222Sgabeblack@google.com [".isa", ".ISA"], 107 "SRCDIR", 108 r'^\s*##include\s+"([\w/.-]*)"') 109 110env.Append(SCANNERS = isa_scanner) 111 112# 113# Now create a Builder object that uses isa_parser.py to generate C++ 114# output from the ISA description (*.isa) files. 115# 116 117# Convert to File node to fix path 118isa_parser = File('isa_parser.py') 119cpu_models_file = File('../cpu/cpu_models.py') 120 121# This sucks in the defintions of the CpuModel objects. 122execfile(cpu_models_file.srcnode().abspath) 123 124# Several files are generated from the ISA description. 125# We always get the basic decoder and header file. 126isa_desc_gen_files = Split('decoder.cc decoder.hh') 127# We also get an execute file for each selected CPU model. 128isa_desc_gen_files += [CpuModel.dict[cpu].filename 129 for cpu in env['CPU_MODELS']] 130 131# The emitter patches up the sources & targets to include the 132# autogenerated files as targets and isa parser itself as a source. 133def isa_desc_emitter(target, source, env): 134 return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 135 136# Pieces are in place, so create the builder. 137python = sys.executable # use same Python binary used to run scons 138isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 139 emitter = isa_desc_emitter) 140 141env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 142 143# 144# Now include other ISA-specific sources from the ISA subdirectories. 145# 146 147isa = env['TARGET_ISA'] # someday this may be a list of ISAs 148 149# Let the target architecture define what additional sources it needs 150sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env') 151 152Return('sources') 153