mmu.cc revision 10915:71ace17ccb3d
111308Santhony.gutierrez@amd.com/*
211308Santhony.gutierrez@amd.com * Copyright (c) 2014-2015 ARM Limited
311308Santhony.gutierrez@amd.com * All rights reserved
411308Santhony.gutierrez@amd.com *
511308Santhony.gutierrez@amd.com * Licensed under the Apache License, Version 2.0 (the "License");
611308Santhony.gutierrez@amd.com * you may not use this file except in compliance with the License.
711308Santhony.gutierrez@amd.com * You may obtain a copy of the License at
811308Santhony.gutierrez@amd.com *
911308Santhony.gutierrez@amd.com *     http://www.apache.org/licenses/LICENSE-2.0
1011308Santhony.gutierrez@amd.com *
1111308Santhony.gutierrez@amd.com * Unless required by applicable law or agreed to in writing, software
1211308Santhony.gutierrez@amd.com * distributed under the License is distributed on an "AS IS" BASIS,
1311308Santhony.gutierrez@amd.com * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
1411308Santhony.gutierrez@amd.com * See the License for the specific language governing permissions and
1511308Santhony.gutierrez@amd.com * limitations under the License.
1611308Santhony.gutierrez@amd.com *
1711308Santhony.gutierrez@amd.com * Authors: Andreas Sandberg
1811308Santhony.gutierrez@amd.com */
1911308Santhony.gutierrez@amd.com
2011308Santhony.gutierrez@amd.com#include "mmu.hh"
2111308Santhony.gutierrez@amd.com
2211308Santhony.gutierrez@amd.com#include "gpu.hh"
2311308Santhony.gutierrez@amd.com#include "regutils.hh"
2411308Santhony.gutierrez@amd.com
2511308Santhony.gutierrez@amd.comnamespace NoMali {
2611308Santhony.gutierrez@amd.com
2711308Santhony.gutierrez@amd.comMMU::MMU(GPU &_gpu)
2811308Santhony.gutierrez@amd.com    : GPUBlockInt(_gpu,
2911308Santhony.gutierrez@amd.com                  RegAddr(MMU_IRQ_RAWSTAT),
3011308Santhony.gutierrez@amd.com                  RegAddr(MMU_IRQ_CLEAR),
3111308Santhony.gutierrez@amd.com                  RegAddr(MMU_IRQ_MASK),
3211308Santhony.gutierrez@amd.com                  RegAddr(MMU_IRQ_STATUS)),
3311308Santhony.gutierrez@amd.com      regs(BLOCK_NUM_REGS)
3411308Santhony.gutierrez@amd.com{
3511308Santhony.gutierrez@amd.com}
3611308Santhony.gutierrez@amd.com
3711308Santhony.gutierrez@amd.comMMU::~MMU()
3811308Santhony.gutierrez@amd.com{
3911308Santhony.gutierrez@amd.com}
4011308Santhony.gutierrez@amd.com
4111308Santhony.gutierrez@amd.comvoid
4211308Santhony.gutierrez@amd.comMMU::writeReg(RegAddr addr, uint32_t value)
4311308Santhony.gutierrez@amd.com{
4411308Santhony.gutierrez@amd.com    switch (addr.value) {
4511308Santhony.gutierrez@amd.com      case MMU_IRQ_RAWSTAT:
4611308Santhony.gutierrez@amd.com      case MMU_IRQ_CLEAR:
4711308Santhony.gutierrez@amd.com      case MMU_IRQ_MASK:
4811308Santhony.gutierrez@amd.com      case MMU_IRQ_STATUS:
4911308Santhony.gutierrez@amd.com        GPUBlockInt::writeReg(addr, value);
5011308Santhony.gutierrez@amd.com        break;
5111308Santhony.gutierrez@amd.com
5211308Santhony.gutierrez@amd.com      default:
5311308Santhony.gutierrez@amd.com        // Ignore writes by default
5411308Santhony.gutierrez@amd.com        break;
5511308Santhony.gutierrez@amd.com    };
5611308Santhony.gutierrez@amd.com}
5711308Santhony.gutierrez@amd.com
5811308Santhony.gutierrez@amd.comvoid
5911308Santhony.gutierrez@amd.comMMU::onInterrupt(int set)
6011308Santhony.gutierrez@amd.com{
6111308Santhony.gutierrez@amd.com    gpu.intMMU(set);
6211308Santhony.gutierrez@amd.com}
6311308Santhony.gutierrez@amd.com
6411308Santhony.gutierrez@amd.com}
6511308Santhony.gutierrez@amd.com