gpucontrol.hh revision 10915
110915Sandreas.sandberg@arm.com/*
210915Sandreas.sandberg@arm.com * Copyright (c) 2014-2015 ARM Limited
310915Sandreas.sandberg@arm.com * All rights reserved
410915Sandreas.sandberg@arm.com *
510915Sandreas.sandberg@arm.com * Licensed under the Apache License, Version 2.0 (the "License");
610915Sandreas.sandberg@arm.com * you may not use this file except in compliance with the License.
710915Sandreas.sandberg@arm.com * You may obtain a copy of the License at
810915Sandreas.sandberg@arm.com *
910915Sandreas.sandberg@arm.com *     http://www.apache.org/licenses/LICENSE-2.0
1010915Sandreas.sandberg@arm.com *
1110915Sandreas.sandberg@arm.com * Unless required by applicable law or agreed to in writing, software
1210915Sandreas.sandberg@arm.com * distributed under the License is distributed on an "AS IS" BASIS,
1310915Sandreas.sandberg@arm.com * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
1410915Sandreas.sandberg@arm.com * See the License for the specific language governing permissions and
1510915Sandreas.sandberg@arm.com * limitations under the License.
1610915Sandreas.sandberg@arm.com *
1710915Sandreas.sandberg@arm.com * Authors: Andreas Sandberg
1810915Sandreas.sandberg@arm.com */
1910915Sandreas.sandberg@arm.com
2010915Sandreas.sandberg@arm.com#ifndef _LIBNOMALIMODEL_GPUCONTROL_HH
2110915Sandreas.sandberg@arm.com#define _LIBNOMALIMODEL_GPUCONTROL_HH
2210915Sandreas.sandberg@arm.com
2310915Sandreas.sandberg@arm.com#include <vector>
2410915Sandreas.sandberg@arm.com
2510915Sandreas.sandberg@arm.com#include "types.hh"
2610915Sandreas.sandberg@arm.com#include "gpublock.hh"
2710915Sandreas.sandberg@arm.com
2810915Sandreas.sandberg@arm.comnamespace NoMali {
2910915Sandreas.sandberg@arm.com
3010915Sandreas.sandberg@arm.comclass GPU;
3110915Sandreas.sandberg@arm.com
3210915Sandreas.sandberg@arm.com/**
3310915Sandreas.sandberg@arm.com * Limited GPU control block implementation.
3410915Sandreas.sandberg@arm.com *
3510915Sandreas.sandberg@arm.com * This is a minimal implementation of the Midgard GPU control
3610915Sandreas.sandberg@arm.com * block. It contains the stuff necessary to do command decoding and
3710915Sandreas.sandberg@arm.com * dispatch, interrupt handling, and GPU block ready handling.
3810915Sandreas.sandberg@arm.com *
3910915Sandreas.sandberg@arm.com * An actual GPU implementation should specialize this class to setup
4010915Sandreas.sandberg@arm.com * the following registers from the reset() method:
4110915Sandreas.sandberg@arm.com * <ul>
4210915Sandreas.sandberg@arm.com *   <li>GPU_ID
4310915Sandreas.sandberg@arm.com *   <li>Feature registers (XX_FEATURES)
4410915Sandreas.sandberg@arm.com *   <li>Present registers (XX_PRESENT)
4510915Sandreas.sandberg@arm.com *   <li>Thread discovery (THREAD_XX)
4610915Sandreas.sandberg@arm.com *   <li>Present registers (XX_PRESENT)
4710915Sandreas.sandberg@arm.com * </ul>
4810915Sandreas.sandberg@arm.com */
4910915Sandreas.sandberg@arm.comclass GPUControl
5010915Sandreas.sandberg@arm.com    : public GPUBlockInt
5110915Sandreas.sandberg@arm.com{
5210915Sandreas.sandberg@arm.com  public:
5310915Sandreas.sandberg@arm.com    GPUControl(GPU &_gpu);
5410915Sandreas.sandberg@arm.com    virtual ~GPUControl();
5510915Sandreas.sandberg@arm.com
5610915Sandreas.sandberg@arm.com    virtual void reset() override = 0;
5710915Sandreas.sandberg@arm.com
5810915Sandreas.sandberg@arm.com    void writeReg(RegAddr idx, uint32_t value) override;
5910915Sandreas.sandberg@arm.com
6010915Sandreas.sandberg@arm.com  protected:
6110915Sandreas.sandberg@arm.com    void onInterrupt(int set) override;
6210915Sandreas.sandberg@arm.com
6310915Sandreas.sandberg@arm.com    /**
6410915Sandreas.sandberg@arm.com     * @{
6510915Sandreas.sandberg@arm.com     * @name GPU control block commands
6610915Sandreas.sandberg@arm.com     */
6710915Sandreas.sandberg@arm.com
6810915Sandreas.sandberg@arm.com    /**
6910915Sandreas.sandberg@arm.com     * Control command dispatcher.
7010915Sandreas.sandberg@arm.com     *
7110915Sandreas.sandberg@arm.com     * This method is called whenever there is a write to the
7210915Sandreas.sandberg@arm.com     * GPU_COMMAND register. The method uses a lookup table to call
7310915Sandreas.sandberg@arm.com     * the right command handling method.
7410915Sandreas.sandberg@arm.com     *
7510915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
7610915Sandreas.sandberg@arm.com     * specification)
7710915Sandreas.sandberg@arm.com     */
7810915Sandreas.sandberg@arm.com    virtual void gpuCommand(uint32_t cmd);
7910915Sandreas.sandberg@arm.com    /**
8010915Sandreas.sandberg@arm.com     * Command handler for No-ops.
8110915Sandreas.sandberg@arm.com     *
8210915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
8310915Sandreas.sandberg@arm.com     * specification)
8410915Sandreas.sandberg@arm.com     */
8510915Sandreas.sandberg@arm.com    virtual void cmdNop(uint32_t cmd);
8610915Sandreas.sandberg@arm.com    /**
8710915Sandreas.sandberg@arm.com     * Command handler for GPU-wide hard resets
8810915Sandreas.sandberg@arm.com     *
8910915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
9010915Sandreas.sandberg@arm.com     * specification)
9110915Sandreas.sandberg@arm.com     */
9210915Sandreas.sandberg@arm.com    virtual void cmdHardReset(uint32_t cmd);
9310915Sandreas.sandberg@arm.com    /**
9410915Sandreas.sandberg@arm.com     * Command handler for GPU-wide soft resets
9510915Sandreas.sandberg@arm.com     *
9610915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
9710915Sandreas.sandberg@arm.com     * specification)
9810915Sandreas.sandberg@arm.com     */
9910915Sandreas.sandberg@arm.com    virtual void cmdSoftReset(uint32_t cmd);
10010915Sandreas.sandberg@arm.com    /**
10110915Sandreas.sandberg@arm.com     * Command handler for performance counter clear operations.
10210915Sandreas.sandberg@arm.com     *
10310915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
10410915Sandreas.sandberg@arm.com     * specification)
10510915Sandreas.sandberg@arm.com     */
10610915Sandreas.sandberg@arm.com    virtual void cmdPerfCntClear(uint32_t cmd);
10710915Sandreas.sandberg@arm.com    /**
10810915Sandreas.sandberg@arm.com     * Command handler for performance counter sample operations.
10910915Sandreas.sandberg@arm.com     *
11010915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
11110915Sandreas.sandberg@arm.com     * specification)
11210915Sandreas.sandberg@arm.com     */
11310915Sandreas.sandberg@arm.com    virtual void cmdPerfCntSample(uint32_t cmd);
11410915Sandreas.sandberg@arm.com    /**
11510915Sandreas.sandberg@arm.com     * Command handler for cycle counter start operations.
11610915Sandreas.sandberg@arm.com     *
11710915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
11810915Sandreas.sandberg@arm.com     * specification)
11910915Sandreas.sandberg@arm.com     */
12010915Sandreas.sandberg@arm.com    virtual void cmdCycleCountStart(uint32_t cmd);
12110915Sandreas.sandberg@arm.com    /**
12210915Sandreas.sandberg@arm.com     * Command handler for cycle counter stop operations.
12310915Sandreas.sandberg@arm.com     *
12410915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
12510915Sandreas.sandberg@arm.com     * specification)
12610915Sandreas.sandberg@arm.com     */
12710915Sandreas.sandberg@arm.com    virtual void cmdCycleCountStop(uint32_t cmd);
12810915Sandreas.sandberg@arm.com    /**
12910915Sandreas.sandberg@arm.com     * Command handler for cache cleaning operations.
13010915Sandreas.sandberg@arm.com     *
13110915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
13210915Sandreas.sandberg@arm.com     * specification)
13310915Sandreas.sandberg@arm.com     */
13410915Sandreas.sandberg@arm.com    virtual void cmdCleanCaches(uint32_t cmd);
13510915Sandreas.sandberg@arm.com    /**
13610915Sandreas.sandberg@arm.com     * Command handler for cache clean and invalidate operations.
13710915Sandreas.sandberg@arm.com     *
13810915Sandreas.sandberg@arm.com     * @param cmd Command number (see the Midgard architecture
13910915Sandreas.sandberg@arm.com     * specification)
14010915Sandreas.sandberg@arm.com     */
14110915Sandreas.sandberg@arm.com    virtual void cmdCleanInvCaches(uint32_t cmd);
14210915Sandreas.sandberg@arm.com
14310915Sandreas.sandberg@arm.com    /** @} */
14410915Sandreas.sandberg@arm.com
14510915Sandreas.sandberg@arm.com  protected:
14610915Sandreas.sandberg@arm.com    typedef void (GPUControl::*cmd_t)(uint32_t);
14710915Sandreas.sandberg@arm.com    /**
14810915Sandreas.sandberg@arm.com     * Mapping between command IDs and command handling methods.
14910915Sandreas.sandberg@arm.com     *
15010915Sandreas.sandberg@arm.com     * @note The order of this vector <i>MUST</i> correspond to the
15110915Sandreas.sandberg@arm.com     * GPU control command IDs in the Midgard architecture
15210915Sandreas.sandberg@arm.com     * specification.
15310915Sandreas.sandberg@arm.com     */
15410915Sandreas.sandberg@arm.com    static const std::vector<cmd_t> cmds;
15510915Sandreas.sandberg@arm.com};
15610915Sandreas.sandberg@arm.com
15710915Sandreas.sandberg@arm.com}
15810915Sandreas.sandberg@arm.com
15910915Sandreas.sandberg@arm.com#endif // _LIBNOMALIMODEL_GPUCONTROL_HH
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