power_region0.xml revision 10235:0db28826e333
1<?xml version="1.0" ?> 2<component id="root" name="root"> 3 <component id="system" name="system" type="System"> 4 <param name="core_tech_node" value="40"/> 5 <param name="target_core_clockrate" value="2400"/> 6 <param name="temperature" value="360"/> 7 <param name="interconnect_projection_type" value="0"/> 8 <param name="device_type" value="0"/> 9 <param name="machine_bits" value="64"/> 10 <param name="virtual_address_width" value="64"/> 11 <param name="physical_address_width" value="52"/> 12 <param name="virtual_memory_page_size" value="4096"/> 13 <param name="wire_is_mat_type" value="2"/> 14 <param name="wire_os_mat_type" value="2"/> 15 <param name="delay_wt" value="100"/> 16 <param name="area_wt" value="0"/> 17 <param name="dynamic_power_wt" value="100"/> 18 <param name="leakage_power_wt" value="0"/> 19 <param name="cycle_time_wt" value="0"/> 20 <param name="delay_dev" value="10000"/> 21 <param name="area_dev" value="10000"/> 22 <param name="dynamic_power_dev" value="10000"/> 23 <param name="leakage_power_dev" value="10000"/> 24 <param name="cycle_time_dev" value="10000"/> 25 <param name="ed" value="2"/> 26 <param name="burst_len" value="1"/> 27 <param name="int_prefetch_w" value="1"/> 28 <param name="page_sz_bits" value="0"/> 29 <param name="rpters_in_htree" value="1"/> 30 <param name="ver_htree_wires_over_array" value="0"/> 31 <param name="nuca" value="0"/> 32 <param name="nuca_bank_count" value="0"/> 33 <param name="force_cache_config" value="0"/> 34 <param name="wt" value="0"/> 35 <param name="force_wiretype" value="0"/> 36 <param name="print_detail" value="1"/> 37 <param name="add_ecc_b_" value="1"/> 38 <stat name="total_cycles" value="1856694"/> 39 <component id="system.core0" name="core0" type="Core"> 40 <param name="opt_local" value="0"/> 41 <param name="clock_rate" value="2000"/> 42 <param name="instruction_length" value="32"/> 43 <param name="opcode_width" value="6"/> 44 <param name="machine_type" value="1"/> 45 <param name="number_hardware_threads" value="1"/> 46 <param name="fetch_width" value="1"/> 47 <param name="number_instruction_fetch_ports" value="1"/> 48 <param name="decode_width" value="1"/> 49 <param name="issue_width" value="1"/> 50 <param name="peak_issue_width" value="1"/> 51 <param name="commit_width" value="1"/> 52 <param name="fp_issue_width" value="1"/> 53 <param name="prediction_width" value="1"/> 54 <param name="int_pipelines" value="1"/> 55 <param name="fp_pipelines" value="1"/> 56 <param name="int_pipeline_depth" value="7"/> 57 <param name="fp_pipeline_depth" value="10"/> 58 <param name="ALU_per_core" value="1"/> 59 <param name="FPU_per_core" value="1"/> 60 <param name="MUL_per_core" value="1"/> 61 <param name="instruction_buffer_size" value="16"/> 62 <param name="instruction_window_scheme" value="0"/> 63 <param name="instruction_window_size" value="0"/> 64 <param name="fp_instruction_window_size" value="0"/> 65 <param name="ROB_size" value="0"/> 66 <param name="archi_Regs_IRF_size" value="32"/> 67 <param name="archi_Regs_FRF_size" value="32"/> 68 <param name="phy_Regs_IRF_size" value="32"/> 69 <param name="phy_Regs_FRF_size" value="32"/> 70 <param name="rename_scheme" value="0"/> 71 <param name="register_window_size" value="0"/> 72 <param name="store_buffer_size" value="8"/> 73 <param name="load_buffer_size" value="0"/> 74 <param name="memory_ports" value="1"/> 75 <param name="RAS_size" value="32"/> 76 <param name="execu_wire_mat_type" value="2"/> 77 <param name="execu_bypass_base_width" value="1"/> 78 <param name="execu_bypass_base_height" value="1"/> 79 <param name="execu_bypass_start_wiring_level"value="3"/> 80 <param name="execu_bypass_route_over_perc" value="1"/> 81 <param name="globalCheckpoint" value="32"/> 82 <param name="perThreadState" value="8"/> 83 <param name="ROB_assoc" value="1"/> 84 <param name="ROB_nbanks" value="1"/> 85 <param name="ROB_tag_width" value="0"/> 86 <param name="scheduler_assoc" value="0"/> 87 <param name="scheduler_nbanks" value="1"/> 88 <param name="register_window_assoc" value="1"/> 89 <param name="register_window_nbanks" value="1"/> 90 <param name="register_window_tag_width" value="0"/> 91 <param name="register_window_rw_ports" value="1"/> 92 <param name="phy_Regs_IRF_assoc" value="1"/> 93 <param name="phy_Regs_IRF_nbanks" value="1"/> 94 <param name="phy_Regs_IRF_tag_width" value="0"/> 95 <param name="phy_Regs_IRF_rd_ports" value="1"/> 96 <param name="phy_Regs_IRF_wr_ports" value="1"/> 97 <param name="phy_Regs_FRF_assoc" value="1"/> 98 <param name="phy_Regs_FRF_nbanks" value="1"/> 99 <param name="phy_Regs_FRF_tag_width" value="0"/> 100 <param name="phy_Regs_FRF_rd_ports" value="1"/> 101 <param name="phy_Regs_FRF_wr_ports" value="1"/> 102 <param name="front_rat_nbanks" value="1"/> 103 <param name="front_rat_rw_ports" value="1"/> 104 <param name="retire_rat_nbanks" value="1"/> 105 <param name="retire_rat_rw_ports" value="0"/> 106 <param name="freelist_nbanks" value="1"/> 107 <param name="freelist_rw_ports" value="1"/> 108 <param name="load_buffer_assoc" value="0"/> 109 <param name="load_buffer_nbanks" value="1"/> 110 <param name="store_buffer_assoc" value="0"/> 111 <param name="store_buffer_nbanks" value="1"/> 112 <param name="instruction_buffer_assoc" value="1"/> 113 <param name="instruction_buffer_nbanks" value="1"/> 114 <param name="instruction_buffer_tag_width" value="0"/> 115 <stat name="total_instructions" value="332405"/> 116 <stat name="int_instructions" value="330557"/> 117 <stat name="fp_instructions" value="1649"/> 118 <stat name="branch_instructions" value="32405"/> 119 <stat name="branch_mispredictions" value="4132"/> 120 <stat name="load_instructions" value="45636"/> 121 <stat name="store_instructions" value="44771"/> 122 <stat name="committed_instructions" value="332405"/> 123 <stat name="committed_int_instructions" value="330557"/> 124 <stat name="committed_fp_instructions" value="1649"/> 125 <stat name="total_cycles" value="9496951709"/> 126 <stat name="idle_cycles" value="103"/> 127 <stat name="busy_cycles" value="9496951606"/> 128 <stat name="ROB_reads" value="332405"/> 129 <stat name="ROB_writes" value="332405"/> 130 <stat name="rename_reads" value="960725"/> 131 <stat name="rename_writes" value="317221"/> 132 <stat name="fp_rename_reads" value="2772"/> 133 <stat name="fp_rename_writes" value="1288"/> 134 <stat name="inst_window_reads" value="330557"/> 135 <stat name="inst_window_writes" value="330557"/> 136 <stat name="inst_window_wakeup_accesses" value="330557"/> 137 <stat name="fp_inst_window_reads" value="1649"/> 138 <stat name="fp_inst_window_writes" value="1649"/> 139 <stat name="fp_inst_window_wakeup_accesses" value="1649"/> 140 <stat name="int_regfile_reads" value="960725"/> 141 <stat name="float_regfile_reads" value="2772"/> 142 <stat name="int_regfile_writes" value="317221"/> 143 <stat name="float_regfile_writes" value="1288"/> 144 <stat name="function_calls" value="2546"/> 145 <stat name="context_switches" value="3"/> 146 <stat name="ialu_accesses" value="330157"/> 147 <stat name="fpu_accesses" value="1649"/> 148 <stat name="mul_accesses" value="400"/> 149 <stat name="cdb_alu_accesses" value="330157"/> 150 <stat name="cdb_mul_accesses" value="400"/> 151 <stat name="cdb_fpu_accesses" value="1649"/> 152 <stat name="IFU_duty_cycle" value="1"/> 153 <stat name="LSU_duty_cycle" value="1"/> 154 <stat name="MemManU_I_duty_cycle" value="1"/> 155 <stat name="MemManU_D_duty_cycle" value="1"/> 156 <stat name="ALU_duty_cycle" value="1"/> 157 <stat name="MUL_duty_cycle" value="1"/> 158 <stat name="FPU_duty_cycle" value="1"/> 159 <stat name="ALU_cdb_duty_cycle" value="1"/> 160 <stat name="MUL_cdb_duty_cycle" value="1"/> 161 <stat name="FPU_cdb_duty_cycle" value="1"/> 162 <component id="system.core0.bpred" name="bpred" type="BranchPredictor"> 163 <param name="assoc" value="1"/> 164 <param name="nbanks" value="1"/> 165 <param name="local_l1_predictor_size" value="10"/> 166 <param name="local_l2_predictor_size" value="3"/> 167 <param name="local_predictor_entries" value="1024"/> 168 <param name="global_predictor_entries" value="4096"/> 169 <param name="global_predictor_bits" value="2"/> 170 <param name="chooser_predictor_entries" value="4096"/> 171 <param name="chooser_predictor_bits" value="2"/> 172 </component> 173 <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> 174 <param name="number_entries" value="64"/> 175 <param name="latency" value="2"/> 176 <param name="throughput" value="2"/> 177 <param name="assoc" value="0"/> 178 <param name="nbanks" value="1"/> 179 <stat name="total_accesses" value="72"/> 180 <stat name="total_misses" value="36"/> 181 <stat name="conflicts" value="0"/> 182 </component> 183 <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> 184 <param name="number_entries" value="64"/> 185 <param name="latency" value="2"/> 186 <param name="throughput" value="2"/> 187 <param name="assoc" value="0"/> 188 <param name="nbanks" value="1"/> 189 <stat name="read_accesses" value="534"/> 190 <stat name="write_accesses" value="0"/> 191 <stat name="read_misses" value="25"/> 192 <stat name="write_misses" value="0"/> 193 <stat name="conflicts" value="0"/> 194 </component> 195 <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> 196 <param name="size" value="8192"/> 197 <param name="block_size" value="4"/> 198 <param name="assoc" value="2"/> 199 <param name="num_banks" value="1"/> 200 <param name="latency" value="1"/> 201 <param name="throughput" value="3"/> 202 <param name="rw_ports" value="1"/> 203 <stat name="read_accesses" value="43"/> 204 <stat name="write_accesses" value="943"/> 205 </component> 206 </component> 207 </component> 208</component> 209