power_region0.xml revision 10235:0db28826e333
1<?xml version="1.0" ?> 2<component id="root" name="root"> 3 <component id="system" name="system" type="System"> 4 <param name="core_tech_node" value="40"/> 5 <param name="target_core_clockrate" value="3000"/> 6 <param name="temperature" value="360"/> 7 <param name="interconnect_projection_type" value="0"/> 8 <param name="device_type" value="0"/> 9 <param name="machine_bits" value="64"/> 10 <param name="virtual_address_width" value="64"/> 11 <param name="physical_address_width" value="52"/> 12 <param name="virtual_memory_page_size" value="4096"/> 13 <param name="wire_is_mat_type" value="2"/> 14 <param name="wire_os_mat_type" value="2"/> 15 <param name="delay_wt" value="100"/> 16 <param name="area_wt" value="0"/> 17 <param name="dynamic_power_wt" value="100"/> 18 <param name="leakage_power_wt" value="0"/> 19 <param name="cycle_time_wt" value="0"/> 20 <param name="delay_dev" value="10000"/> 21 <param name="area_dev" value="10000"/> 22 <param name="dynamic_power_dev" value="10000"/> 23 <param name="leakage_power_dev" value="10000"/> 24 <param name="cycle_time_dev" value="10000"/> 25 <param name="ed" value="2"/> 26 <param name="burst_len" value="1"/> 27 <param name="int_prefetch_w" value="1"/> 28 <param name="page_sz_bits" value="0"/> 29 <param name="rpters_in_htree" value="1"/> 30 <param name="ver_htree_wires_over_array" value="0"/> 31 <param name="nuca" value="0"/> 32 <param name="nuca_bank_count" value="0"/> 33 <param name="force_cache_config" value="0"/> 34 <param name="wt" value="0"/> 35 <param name="force_wiretype" value="0"/> 36 <param name="print_detail" value="1"/> 37 <param name="add_ecc_b_" value="1"/> 38 <stat name="total_cycles" value="1856694"/> 39 <component id="system.core0" name="core0" type="Core"> 40 <param name="opt_local" value="0"/> 41 <param name="clock_rate" value="2000"/> 42 <param name="instruction_length" value="32"/> 43 <param name="opcode_width" value="6"/> 44 <param name="machine_type" value="1"/> 45 <param name="number_hardware_threads" value="1"/> 46 <param name="fetch_width" value="1"/> 47 <param name="number_instruction_fetch_ports" value="1"/> 48 <param name="decode_width" value="1"/> 49 <param name="issue_width" value="1"/> 50 <param name="peak_issue_width" value="1"/> 51 <param name="commit_width" value="1"/> 52 <param name="fp_issue_width" value="1"/> 53 <param name="prediction_width" value="1"/> 54 <param name="int_pipelines" value="1"/> 55 <param name="fp_pipelines" value="1"/> 56 <param name="int_pipeline_depth" value="7"/> 57 <param name="fp_pipeline_depth" value="10"/> 58 <param name="ALU_per_core" value="1"/> 59 <param name="FPU_per_core" value="1"/> 60 <param name="MUL_per_core" value="1"/> 61 <param name="instruction_buffer_size" value="16"/> 62 <param name="instruction_window_scheme" value="0"/> 63 <param name="instruction_window_size" value="0"/> 64 <param name="fp_instruction_window_size" value="0"/> 65 <param name="ROB_size" value="0"/> 66 <param name="archi_Regs_IRF_size" value="32"/> 67 <param name="archi_Regs_FRF_size" value="32"/> 68 <param name="phy_Regs_IRF_size" value="32"/> 69 <param name="phy_Regs_FRF_size" value="32"/> 70 <param name="rename_scheme" value="0"/> 71 <param name="register_window_size" value="0"/> 72 <param name="store_buffer_size" value="8"/> 73 <param name="load_buffer_size" value="0"/> 74 <param name="memory_ports" value="1"/> 75 <param name="RAS_size" value="32"/> 76 <param name="execu_wire_mat_type" value="2"/> 77 <param name="execu_bypass_base_width" value="1"/> 78 <param name="execu_bypass_base_height" value="1"/> 79 <param name="execu_bypass_start_wiring_level"value="3"/> 80 <param name="execu_bypass_route_over_perc" value="1"/> 81 <param name="globalCheckpoint" value="32"/> 82 <param name="perThreadState" value="8"/> 83 <param name="ROB_assoc" value="1"/> 84 <param name="ROB_nbanks" value="1"/> 85 <param name="ROB_tag_width" value="0"/> 86 <param name="scheduler_assoc" value="0"/> 87 <param name="scheduler_nbanks" value="1"/> 88 <param name="register_window_assoc" value="1"/> 89 <param name="register_window_nbanks" value="1"/> 90 <param name="register_window_tag_width" value="0"/> 91 <param name="register_window_rw_ports" value="1"/> 92 <param name="phy_Regs_IRF_assoc" value="1"/> 93 <param name="phy_Regs_IRF_nbanks" value="1"/> 94 <param name="phy_Regs_IRF_tag_width" value="0"/> 95 <param name="phy_Regs_IRF_rd_ports" value="1"/> 96 <param name="phy_Regs_IRF_wr_ports" value="1"/> 97 <param name="phy_Regs_FRF_assoc" value="1"/> 98 <param name="phy_Regs_FRF_nbanks" value="1"/> 99 <param name="phy_Regs_FRF_tag_width" value="0"/> 100 <param name="phy_Regs_FRF_rd_ports" value="1"/> 101 <param name="phy_Regs_FRF_wr_ports" value="1"/> 102 <param name="front_rat_nbanks" value="1"/> 103 <param name="front_rat_rw_ports" value="1"/> 104 <param name="retire_rat_nbanks" value="1"/> 105 <param name="retire_rat_rw_ports" value="0"/> 106 <param name="freelist_nbanks" value="1"/> 107 <param name="freelist_rw_ports" value="1"/> 108 <param name="load_buffer_assoc" value="0"/> 109 <param name="load_buffer_nbanks" value="1"/> 110 <param name="store_buffer_assoc" value="0"/> 111 <param name="store_buffer_nbanks" value="1"/> 112 <param name="instruction_buffer_assoc" value="1"/> 113 <param name="instruction_buffer_nbanks" value="1"/> 114 <param name="instruction_buffer_tag_width" value="0"/> 115 <stat name="total_instructions" value="332405"/> 116 <stat name="int_instructions" value="330557"/> 117 <stat name="fp_instructions" value="1649"/> 118 <stat name="branch_instructions" value="8263"/> 119 <stat name="branch_mispredictions" value="53"/> 120 <stat name="load_instructions" value="45636"/> 121 <stat name="store_instructions" value="44771"/> 122 <stat name="committed_instructions" value="332405"/> 123 <stat name="committed_int_instructions" value="330557"/> 124 <stat name="committed_fp_instructions" value="1649"/> 125 <stat name="total_cycles" value="9496951709"/> 126 <stat name="idle_cycles" value="0"/> 127 <stat name="busy_cycles" value="9496951709"/> 128 <stat name="ROB_reads" value="332405"/> 129 <stat name="ROB_writes" value="332405"/> 130 <stat name="rename_reads" value="960725"/> 131 <stat name="rename_writes" value="317221"/> 132 <stat name="fp_rename_reads" value="2772"/> 133 <stat name="fp_rename_writes" value="1288"/> 134 <stat name="inst_window_reads" value="330557"/> 135 <stat name="inst_window_writes" value="330557"/> 136 <stat name="inst_window_wakeup_accesses" value="330557"/> 137 <stat name="fp_inst_window_reads" value="1649"/> 138 <stat name="fp_inst_window_writes" value="1649"/> 139 <stat name="fp_inst_window_wakeup_accesses" value="1649"/> 140 <stat name="int_regfile_reads" value="960725"/> 141 <stat name="float_regfile_reads" value="2772"/> 142 <stat name="int_regfile_writes" value="317221"/> 143 <stat name="float_regfile_writes" value="1288"/> 144 <stat name="function_calls" value="5"/> 145 <stat name="context_switches" value="1"/> 146 <stat name="ialu_accesses" value="330157"/> 147 <stat name="fpu_accesses" value="1649"/> 148 <stat name="mul_accesses" value="200"/> 149 <stat name="cdb_alu_accesses" value="330157"/> 150 <stat name="cdb_mul_accesses" value="200"/> 151 <stat name="cdb_fpu_accesses" value="1649"/> 152 <stat name="IFU_duty_cycle" value="1"/> 153 <stat name="LSU_duty_cycle" value="1"/> 154 <stat name="MemManU_I_duty_cycle" value="1"/> 155 <stat name="MemManU_D_duty_cycle" value="1"/> 156 <stat name="ALU_duty_cycle" value="1"/> 157 <stat name="MUL_duty_cycle" value="1"/> 158 <stat name="FPU_duty_cycle" value="1"/> 159 <stat name="ALU_cdb_duty_cycle" value="1"/> 160 <stat name="MUL_cdb_duty_cycle" value="1"/> 161 <stat name="FPU_cdb_duty_cycle" value="1"/> 162 <component id="system.core0.bpred" name="bpred" type="BranchPredictor"> 163 <param name="assoc" value="1"/> 164 <param name="nbanks" value="1"/> 165 <param name="local_l1_predictor_size" value="10"/> 166 <param name="local_l2_predictor_size" value="3"/> 167 <param name="local_predictor_entries" value="1024"/> 168 <param name="global_predictor_entries" value="4096"/> 169 <param name="global_predictor_bits" value="2"/> 170 <param name="chooser_predictor_entries" value="4096"/> 171 <param name="chooser_predictor_bits" value="2"/> 172 </component> 173 <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> 174 <param name="number_entries" value="64"/> 175 <param name="latency" value="8"/> 176 <param name="throughput" value="3"/> 177 <param name="assoc" value="0"/> 178 <param name="nbanks" value="1"/> 179 <stat name="total_accesses" value="8263"/> 180 <stat name="total_misses" value="5"/> 181 <stat name="conflicts" value="1"/> 182 </component> 183 <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> 184 <param name="number_entries" value="64"/> 185 <param name="latency" value="8"/> 186 <param name="throughput" value="3"/> 187 <param name="assoc" value="0"/> 188 <param name="nbanks" value="1"/> 189 <stat name="read_accesses" value="108476"/> 190 <stat name="write_accesses" value="78"/> 191 <stat name="read_misses" value="7"/> 192 <stat name="write_misses" value="0"/> 193 <stat name="conflicts" value="7"/> 194 </component> 195 <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> 196 <param name="size" value="8192"/> 197 <param name="block_size" value="4"/> 198 <param name="assoc" value="2"/> 199 <param name="num_banks" value="1"/> 200 <param name="latency" value="1"/> 201 <param name="throughput" value="3"/> 202 <param name="rw_ports" value="1"/> 203 <stat name="read_accesses" value="43"/> 204 <stat name="write_accesses" value="943"/> 205 </component> 206 </component> 207 <component id="system.core1" name="core1" type="Core"> 208 <param name="opt_local" value="0"/> 209 <param name="clock_rate" value="2000"/> 210 <param name="instruction_length" value="32"/> 211 <param name="opcode_width" value="6"/> 212 <param name="machine_type" value="1"/> 213 <param name="number_hardware_threads" value="1"/> 214 <param name="fetch_width" value="1"/> 215 <param name="number_instruction_fetch_ports" value="1"/> 216 <param name="decode_width" value="1"/> 217 <param name="issue_width" value="1"/> 218 <param name="peak_issue_width" value="1"/> 219 <param name="commit_width" value="1"/> 220 <param name="fp_issue_width" value="1"/> 221 <param name="prediction_width" value="1"/> 222 <param name="int_pipelines" value="1"/> 223 <param name="fp_pipelines" value="1"/> 224 <param name="int_pipeline_depth" value="7"/> 225 <param name="fp_pipeline_depth" value="10"/> 226 <param name="ALU_per_core" value="1"/> 227 <param name="FPU_per_core" value="1"/> 228 <param name="MUL_per_core" value="1"/> 229 <param name="instruction_buffer_size" value="16"/> 230 <param name="instruction_window_scheme" value="0"/> 231 <param name="instruction_window_size" value="0"/> 232 <param name="fp_instruction_window_size" value="0"/> 233 <param name="ROB_size" value="0"/> 234 <param name="archi_Regs_IRF_size" value="32"/> 235 <param name="archi_Regs_FRF_size" value="32"/> 236 <param name="phy_Regs_IRF_size" value="32"/> 237 <param name="phy_Regs_FRF_size" value="32"/> 238 <param name="rename_scheme" value="0"/> 239 <param name="register_window_size" value="0"/> 240 <param name="store_buffer_size" value="8"/> 241 <param name="load_buffer_size" value="0"/> 242 <param name="memory_ports" value="1"/> 243 <param name="RAS_size" value="32"/> 244 <param name="execu_wire_mat_type" value="2"/> 245 <param name="execu_bypass_base_width" value="1"/> 246 <param name="execu_bypass_base_height" value="1"/> 247 <param name="execu_bypass_start_wiring_level"value="3"/> 248 <param name="execu_bypass_route_over_perc" value="1"/> 249 <param name="globalCheckpoint" value="32"/> 250 <param name="perThreadState" value="8"/> 251 <param name="ROB_assoc" value="1"/> 252 <param name="ROB_nbanks" value="1"/> 253 <param name="ROB_tag_width" value="0"/> 254 <param name="scheduler_assoc" value="0"/> 255 <param name="scheduler_nbanks" value="1"/> 256 <param name="register_window_assoc" value="1"/> 257 <param name="register_window_nbanks" value="1"/> 258 <param name="register_window_tag_width" value="0"/> 259 <param name="register_window_rw_ports" value="1"/> 260 <param name="phy_Regs_IRF_assoc" value="1"/> 261 <param name="phy_Regs_IRF_nbanks" value="1"/> 262 <param name="phy_Regs_IRF_tag_width" value="0"/> 263 <param name="phy_Regs_IRF_rd_ports" value="1"/> 264 <param name="phy_Regs_IRF_wr_ports" value="1"/> 265 <param name="phy_Regs_FRF_assoc" value="1"/> 266 <param name="phy_Regs_FRF_nbanks" value="1"/> 267 <param name="phy_Regs_FRF_tag_width" value="0"/> 268 <param name="phy_Regs_FRF_rd_ports" value="1"/> 269 <param name="phy_Regs_FRF_wr_ports" value="1"/> 270 <param name="front_rat_nbanks" value="1"/> 271 <param name="front_rat_rw_ports" value="1"/> 272 <param name="retire_rat_nbanks" value="1"/> 273 <param name="retire_rat_rw_ports" value="0"/> 274 <param name="freelist_nbanks" value="1"/> 275 <param name="freelist_rw_ports" value="1"/> 276 <param name="load_buffer_assoc" value="0"/> 277 <param name="load_buffer_nbanks" value="1"/> 278 <param name="store_buffer_assoc" value="0"/> 279 <param name="store_buffer_nbanks" value="1"/> 280 <param name="instruction_buffer_assoc" value="1"/> 281 <param name="instruction_buffer_nbanks" value="1"/> 282 <param name="instruction_buffer_tag_width" value="0"/> 283 <stat name="total_instructions" value="4358"/> 284 <stat name="int_instructions" value="4336"/> 285 <stat name="fp_instructions" value="22"/> 286 <stat name="branch_instructions" value="1358"/> 287 <stat name="branch_mispredictions" value="14"/> 288 <stat name="load_instructions" value="715"/> 289 <stat name="store_instructions" value="406"/> 290 <stat name="committed_instructions" value="4358"/> 291 <stat name="committed_int_instructions" value="4336"/> 292 <stat name="committed_fp_instructions" value="22"/> 293 <stat name="total_cycles" value="9496737874"/> 294 <stat name="ROB_reads" value="4358"/> 295 <stat name="ROB_writes" value="4358"/> 296 <stat name="rename_reads" value="12614"/> 297 <stat name="rename_writes" value="4404"/> 298 <stat name="fp_rename_reads" value="22"/> 299 <stat name="fp_rename_writes" value="22"/> 300 <stat name="inst_window_reads" value="4336"/> 301 <stat name="inst_window_writes" value="4336"/> 302 <stat name="inst_window_wakeup_accesses" value="4336"/> 303 <stat name="fp_inst_window_reads" value="22"/> 304 <stat name="fp_inst_window_writes" value="22"/> 305 <stat name="fp_inst_window_wakeup_accesses" value="22"/> 306 <stat name="int_regfile_reads" value="12614"/> 307 <stat name="float_regfile_reads" value="44"/> 308 <stat name="int_regfile_writes" value="4404"/> 309 <stat name="float_regfile_writes" value="22"/> 310 <stat name="function_calls" value="3"/> 311 <stat name="context_switches" value="1"/> 312 <stat name="ialu_accesses" value="4236"/> 313 <stat name="fpu_accesses" value="22"/> 314 <stat name="mul_accesses" value="100"/> 315 <stat name="cdb_alu_accesses" value="4236"/> 316 <stat name="cdb_mul_accesses" value="100"/> 317 <stat name="cdb_fpu_accesses" value="22"/> 318 <stat name="IFU_duty_cycle" value="1"/> 319 <stat name="LSU_duty_cycle" value="1"/> 320 <stat name="MemManU_I_duty_cycle" value="1"/> 321 <stat name="MemManU_D_duty_cycle" value="1"/> 322 <stat name="ALU_duty_cycle" value="1"/> 323 <stat name="MUL_duty_cycle" value="1"/> 324 <stat name="FPU_duty_cycle" value="1"/> 325 <stat name="ALU_cdb_duty_cycle" value="1"/> 326 <stat name="MUL_cdb_duty_cycle" value="1"/> 327 <stat name="FPU_cdb_duty_cycle" value="1"/> 328 <component id="system.core1.bpred" name="bpred" type="BranchPredictor"> 329 <param name="assoc" value="1"/> 330 <param name="nbanks" value="1"/> 331 <param name="local_l1_predictor_size" value="10"/> 332 <param name="local_l2_predictor_size" value="3"/> 333 <param name="local_predictor_entries" value="1024"/> 334 <param name="global_predictor_entries" value="4096"/> 335 <param name="global_predictor_bits" value="2"/> 336 <param name="chooser_predictor_entries" value="4096"/> 337 <param name="chooser_predictor_bits" value="2"/> 338 </component> 339 <component id="system.core1.itlb" name="itlb" type="InstructionTLB"> 340 <param name="number_entries" value="64"/> 341 <param name="latency" value="8"/> 342 <param name="throughput" value="3"/> 343 <param name="assoc" value="0"/> 344 <param name="nbanks" value="1"/> 345 <stat name="total_accesses" value="253291"/> 346 <stat name="total_misses" value="6"/> 347 <stat name="conflicts" value="5"/> 348 </component> 349 <component id="system.core1.dtlb" name="dtlb" type="DataTLB"> 350 <param name="number_entries" value="64"/> 351 <param name="latency" value="8"/> 352 <param name="throughput" value="3"/> 353 <param name="assoc" value="0"/> 354 <param name="nbanks" value="1"/> 355 <stat name="read_accesses" value="91498"/> 356 <stat name="write_accesses" value="29"/> 357 <stat name="read_misses" value="3"/> 358 <stat name="write_misses" value="0"/> 359 <stat name="conflicts" value="3"/> 360 </component> 361 <component id="system.core1.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> 362 <param name="size" value="8192"/> 363 <param name="block_size" value="4"/> 364 <param name="assoc" value="2"/> 365 <param name="num_banks" value="1"/> 366 <param name="latency" value="1"/> 367 <param name="throughput" value="3"/> 368 <param name="rw_ports" value="1"/> 369 <stat name="read_accesses" value="43"/> 370 <stat name="write_accesses" value="943"/> 371 </component> 372 </component> 373 <component id="system.mc" name="mc" type="MemoryController"> 374 <param name="mc_clock" value="800"/> 375 <param name="tech_type" value="2"/> 376 <param name="mc_type" value="0"/> 377 <param name="num_mcs" value="1"/> 378 <param name="type" value="0"/> 379 <param name="LVDS" value="1"/> 380 <param name="withPHY" value="1"/> 381 <param name="llc_line_length" value="64"/> 382 <param name="memory_channels_per_mc" value="2"/> 383 <param name="req_window_size_per_channel" value="128"/> 384 <param name="IO_buffer_size_per_channel" value="128"/> 385 <param name="databus_width" value="128"/> 386 <param name="addressbus_width" value="51"/> 387 <param name="opcode_width" value="16"/> 388 <param name="peak_transfer_rate" value="6400"/> 389 <param name="number_ranks" value="2"/> 390 <param name="reorder_buffer_assoc" value="0"/> 391 <param name="reorder_buffer_nbanks" value="1"/> 392 <param name="read_buffer_assoc" value="1"/> 393 <param name="read_buffer_nbanks" value="1"/> 394 <param name="read_buffer_tag_width" value="0"/> 395 <param name="write_buffer_assoc" value="1"/> 396 <param name="write_buffer_nbanks" value="1"/> 397 <param name="write_buffer_tag_width" value="0"/> 398 <param name="wire_mat_type" value="2"/> 399 <param name="wire_type" value="0"/> 400 <stat name="memory_reads" value="274"/> 401 <stat name="memory_writes" value="86"/> 402 <stat name="duty_cycle" value="0.5"/> 403 </component> 404 <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> 405 <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> 406 <param name="level" value="1"/> 407 <param name="size" value="32768"/> 408 <param name="block_size" value="64"/> 409 <param name="assoc" value="2"/> 410 <param name="num_banks" value="1"/> 411 <param name="latency" value="2"/> 412 <param name="throughput" value="1"/> 413 <param name="miss_buffer_size" value="2"/> 414 <param name="fetch_buffer_size" value="2"/> 415 <param name="prefetch_buffer_size" value="2"/> 416 <param name="writeback_buffer_size" value="2"/> 417 <param name="device_type" value="0"/> 418 <param name="clockrate" value="0"/> 419 <param name="tech_type" value="0"/> 420 <param name="Directory_type" value="2"/> 421 <param name="core_type" value="1"/> 422 <param name="wire_mat_type" value="2"/> 423 <param name="wire_type" value="0"/> 424 <param name="miss_buffer_assoc" value="0"/> 425 <param name="fetch_buffer_assoc" value="0"/> 426 <param name="prefetch_buffer_assoc" value="0"/> 427 <param name="writeback_buffer_assoc" value="0"/> 428 <param name="miss_buffer_banks" value="1"/> 429 <param name="fetch_buffer_banks" value="1"/> 430 <param name="prefetch_buffer_banks" value="1"/> 431 <param name="writeback_buffer_banks" value="1"/> 432 <param name="cache_access_mode" value="0"/> 433 <param name="miss_buff_access_mode" value="2"/> 434 <param name="fetch_buff_access_mode" value="2"/> 435 <param name="prefetch_buff_access_mode" value="2"/> 436 <param name="writeback_buff_access_mode"value="2"/> 437 <param name="cache_rw_ports" value="1"/> 438 <param name="cache_rd_ports" value="0"/> 439 <param name="cache_wr_ports" value="0"/> 440 <param name="cache_se_rd_ports" value="0"/> 441 <param name="cache_search_ports" value="0"/> 442 <param name="miss_buff_rw_ports" value="1"/> 443 <param name="miss_buff_rd_ports" value="0"/> 444 <param name="miss_buff_wr_ports" value="0"/> 445 <param name="miss_buff_se_rd_ports" value="0"/> 446 <param name="miss_buff_search_ports" value="1"/> 447 <param name="fetch_buff_rw_ports" value="1"/> 448 <param name="fetch_buff_rd_ports" value="0"/> 449 <param name="fetch_buff_wr_ports" value="0"/> 450 <param name="fetch_buff_se_rd_ports" value="0"/> 451 <param name="fetch_buff_search_ports" value="1"/> 452 <param name="pf_buff_rw_ports" value="1"/> 453 <param name="pf_buff_rd_ports" value="0"/> 454 <param name="pf_buff_wr_ports" value="0"/> 455 <param name="pf_buff_se_rd_ports" value="0"/> 456 <param name="pf_buff_search_ports" value="1"/> 457 <param name="wb_buff_rw_ports" value="1"/> 458 <param name="wb_buff_rd_ports" value="0"/> 459 <param name="wb_buff_wr_ports" value="0"/> 460 <param name="wb_buff_se_rd_ports" value="0"/> 461 <param name="wb_buff_search_ports" value="1"/> 462 <param name="pure_ram" value="0"/> 463 <stat name="num_data_array_reads" value="47291"/> 464 <stat name="num_data_array_writes" value="51619"/> 465 <stat name="num_tag_array_reads" value="91498"/> 466 <stat name="num_tag_array_writes" value="17078"/> 467 <stat name="read_misses" value="156"/> 468 <stat name="write_misses" value="92"/> 469 <stat name="conflicts" value="148"/> 470 <stat name="duty_cycle" value="1"/> 471 </component> 472 <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> 473 <param name="level" value="1"/> 474 <param name="size" value="32768"/> 475 <param name="block_size" value="64"/> 476 <param name="assoc" value="2"/> 477 <param name="num_banks" value="1"/> 478 <param name="latency" value="2"/> 479 <param name="throughput" value="1"/> 480 <param name="miss_buffer_size" value="2"/> 481 <param name="fetch_buffer_size" value="2"/> 482 <param name="prefetch_buffer_size" value="2"/> 483 <param name="writeback_buffer_size" value="2"/> 484 <param name="device_type" value="0"/> 485 <param name="clockrate" value="0"/> 486 <param name="tech_type" value="0"/> 487 <param name="Directory_type" value="2"/> 488 <param name="core_type" value="1"/> 489 <param name="wire_mat_type" value="2"/> 490 <param name="wire_type" value="0"/> 491 <param name="miss_buffer_assoc" value="0"/> 492 <param name="fetch_buffer_assoc" value="0"/> 493 <param name="prefetch_buffer_assoc" value="0"/> 494 <param name="writeback_buffer_assoc" value="0"/> 495 <param name="miss_buffer_banks" value="1"/> 496 <param name="fetch_buffer_banks" value="1"/> 497 <param name="prefetch_buffer_banks" value="1"/> 498 <param name="writeback_buffer_banks" value="1"/> 499 <param name="cache_access_mode" value="0"/> 500 <param name="miss_buff_access_mode" value="2"/> 501 <param name="fetch_buff_access_mode" value="2"/> 502 <param name="prefetch_buff_access_mode" value="2"/> 503 <param name="writeback_buff_access_mode"value="2"/> 504 <param name="cache_rw_ports" value="1"/> 505 <param name="cache_rd_ports" value="0"/> 506 <param name="cache_wr_ports" value="0"/> 507 <param name="cache_se_rd_ports" value="0"/> 508 <param name="cache_search_ports" value="0"/> 509 <param name="miss_buff_rw_ports" value="1"/> 510 <param name="miss_buff_rd_ports" value="0"/> 511 <param name="miss_buff_wr_ports" value="0"/> 512 <param name="miss_buff_se_rd_ports" value="0"/> 513 <param name="miss_buff_search_ports" value="1"/> 514 <param name="fetch_buff_rw_ports" value="1"/> 515 <param name="fetch_buff_rd_ports" value="0"/> 516 <param name="fetch_buff_wr_ports" value="0"/> 517 <param name="fetch_buff_se_rd_ports" value="0"/> 518 <param name="fetch_buff_search_ports" value="1"/> 519 <param name="pf_buff_rw_ports" value="1"/> 520 <param name="pf_buff_rd_ports" value="0"/> 521 <param name="pf_buff_wr_ports" value="0"/> 522 <param name="pf_buff_se_rd_ports" value="0"/> 523 <param name="pf_buff_search_ports" value="1"/> 524 <param name="wb_buff_rw_ports" value="1"/> 525 <param name="wb_buff_rd_ports" value="0"/> 526 <param name="wb_buff_wr_ports" value="0"/> 527 <param name="wb_buff_se_rd_ports" value="0"/> 528 <param name="wb_buff_search_ports" value="1"/> 529 <param name="pure_ram" value="0"/> 530 <stat name="num_data_array_reads" value="253831"/> 531 <stat name="num_data_array_writes" value="3497"/> 532 <stat name="num_tag_array_reads" value="253291"/> 533 <stat name="num_tag_array_writes" value="10845"/> 534 <stat name="read_misses" value="456"/> 535 <stat name="write_misses" value="92"/> 536 <stat name="conflicts" value="448"/> 537 <stat name="duty_cycle" value="1"/> 538 </component> 539 <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> 540 <param name="level" value="2"/> 541 <param name="size" value="2097152"/> 542 <param name="block_size" value="64"/> 543 <param name="assoc" value="16"/> 544 <param name="num_banks" value="1"/> 545 <param name="latency" value="10"/> 546 <param name="throughput" value="1"/> 547 <param name="miss_buffer_size" value="2"/> 548 <param name="fetch_buffer_size" value="2"/> 549 <param name="prefetch_buffer_size" value="2"/> 550 <param name="writeback_buffer_size" value="2"/> 551 <param name="device_type" value="0"/> 552 <param name="clockrate" value="0"/> 553 <param name="tech_type" value="0"/> 554 <param name="Directory_type" value="2"/> 555 <param name="core_type" value="1"/> 556 <param name="wire_mat_type" value="2"/> 557 <param name="wire_type" value="0"/> 558 <param name="miss_buffer_assoc" value="0"/> 559 <param name="fetch_buffer_assoc" value="0"/> 560 <param name="prefetch_buffer_assoc" value="0"/> 561 <param name="writeback_buffer_assoc" value="0"/> 562 <param name="miss_buffer_banks" value="1"/> 563 <param name="fetch_buffer_banks" value="1"/> 564 <param name="prefetch_buffer_banks" value="1"/> 565 <param name="writeback_buffer_banks" value="1"/> 566 <param name="cache_access_mode" value="1"/> 567 <param name="miss_buff_access_mode" value="0"/> 568 <param name="fetch_buff_access_mode" value="0"/> 569 <param name="prefetch_buff_access_mode" value="0"/> 570 <param name="writeback_buff_access_mode"value="0"/> 571 <param name="cache_rw_ports" value="1"/> 572 <param name="cache_rd_ports" value="0"/> 573 <param name="cache_wr_ports" value="0"/> 574 <param name="cache_se_rd_ports" value="0"/> 575 <param name="cache_search_ports" value="0"/> 576 <param name="miss_buff_rw_ports" value="1"/> 577 <param name="miss_buff_rd_ports" value="0"/> 578 <param name="miss_buff_wr_ports" value="0"/> 579 <param name="miss_buff_se_rd_ports" value="0"/> 580 <param name="miss_buff_search_ports" value="1"/> 581 <param name="fetch_buff_rw_ports" value="1"/> 582 <param name="fetch_buff_rd_ports" value="0"/> 583 <param name="fetch_buff_wr_ports" value="0"/> 584 <param name="fetch_buff_se_rd_ports" value="0"/> 585 <param name="fetch_buff_search_ports" value="1"/> 586 <param name="pf_buff_rw_ports" value="1"/> 587 <param name="pf_buff_rd_ports" value="0"/> 588 <param name="pf_buff_wr_ports" value="0"/> 589 <param name="pf_buff_se_rd_ports" value="0"/> 590 <param name="pf_buff_search_ports" value="1"/> 591 <param name="wb_buff_rw_ports" value="1"/> 592 <param name="wb_buff_rd_ports" value="0"/> 593 <param name="wb_buff_wr_ports" value="0"/> 594 <param name="wb_buff_se_rd_ports" value="0"/> 595 <param name="wb_buff_search_ports" value="1"/> 596 <param name="pure_ram" value="0"/> 597 <stat name="num_data_array_reads" value="274"/> 598 <stat name="num_data_array_writes" value="8086"/> 599 <stat name="num_tag_array_reads" value="3959"/> 600 <stat name="num_tag_array_writes" value="12046"/> 601 <stat name="read_misses" value="56"/> 602 <stat name="write_misses" value="32"/> 603 <stat name="conflicts" value="88"/> 604 <stat name="duty_cycle" value="1"/> 605 </component> 606 </component> 607 <component id="system.l1_cntrl1" name="l1_cntrl1" type="CacheController"> 608 <component id="system.l1_cntrl1.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> 609 <param name="level" value="1"/> 610 <param name="size" value="32768"/> 611 <param name="block_size" value="64"/> 612 <param name="assoc" value="2"/> 613 <param name="num_banks" value="1"/> 614 <param name="latency" value="2"/> 615 <param name="throughput" value="1"/> 616 <param name="miss_buffer_size" value="2"/> 617 <param name="fetch_buffer_size" value="2"/> 618 <param name="prefetch_buffer_size" value="2"/> 619 <param name="writeback_buffer_size" value="2"/> 620 <param name="device_type" value="0"/> 621 <param name="clockrate" value="0"/> 622 <param name="tech_type" value="0"/> 623 <param name="Directory_type" value="2"/> 624 <param name="core_type" value="1"/> 625 <param name="wire_mat_type" value="2"/> 626 <param name="wire_type" value="0"/> 627 <param name="miss_buffer_assoc" value="0"/> 628 <param name="fetch_buffer_assoc" value="0"/> 629 <param name="prefetch_buffer_assoc" value="0"/> 630 <param name="writeback_buffer_assoc" value="0"/> 631 <param name="miss_buffer_banks" value="1"/> 632 <param name="fetch_buffer_banks" value="1"/> 633 <param name="prefetch_buffer_banks" value="1"/> 634 <param name="writeback_buffer_banks" value="1"/> 635 <param name="cache_access_mode" value="0"/> 636 <param name="miss_buff_access_mode" value="2"/> 637 <param name="fetch_buff_access_mode" value="2"/> 638 <param name="prefetch_buff_access_mode" value="2"/> 639 <param name="writeback_buff_access_mode"value="2"/> 640 <param name="cache_rw_ports" value="1"/> 641 <param name="cache_rd_ports" value="0"/> 642 <param name="cache_wr_ports" value="0"/> 643 <param name="cache_se_rd_ports" value="0"/> 644 <param name="cache_search_ports" value="0"/> 645 <param name="miss_buff_rw_ports" value="1"/> 646 <param name="miss_buff_rd_ports" value="0"/> 647 <param name="miss_buff_wr_ports" value="0"/> 648 <param name="miss_buff_se_rd_ports" value="0"/> 649 <param name="miss_buff_search_ports" value="1"/> 650 <param name="fetch_buff_rw_ports" value="1"/> 651 <param name="fetch_buff_rd_ports" value="0"/> 652 <param name="fetch_buff_wr_ports" value="0"/> 653 <param name="fetch_buff_se_rd_ports" value="0"/> 654 <param name="fetch_buff_search_ports" value="1"/> 655 <param name="pf_buff_rw_ports" value="1"/> 656 <param name="pf_buff_rd_ports" value="0"/> 657 <param name="pf_buff_wr_ports" value="0"/> 658 <param name="pf_buff_se_rd_ports" value="0"/> 659 <param name="pf_buff_search_ports" value="1"/> 660 <param name="wb_buff_rw_ports" value="1"/> 661 <param name="wb_buff_rd_ports" value="0"/> 662 <param name="wb_buff_wr_ports" value="0"/> 663 <param name="wb_buff_se_rd_ports" value="0"/> 664 <param name="wb_buff_search_ports" value="1"/> 665 <param name="pure_ram" value="0"/> 666 <stat name="num_data_array_reads" value="631"/> 667 <stat name="num_data_array_writes" value="527"/> 668 <stat name="num_tag_array_reads" value="6356"/> 669 <stat name="num_tag_array_writes" value="297"/> 670 <stat name="read_misses" value="36"/> 671 <stat name="write_misses" value="12"/> 672 <stat name="conflicts" value="48"/> 673 <stat name="duty_cycle" value="1"/> 674 </component> 675 <component id="system.l1_cntrl1.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> 676 <param name="level" value="1"/> 677 <param name="size" value="32768"/> 678 <param name="block_size" value="64"/> 679 <param name="assoc" value="2"/> 680 <param name="num_banks" value="1"/> 681 <param name="latency" value="2"/> 682 <param name="throughput" value="1"/> 683 <param name="miss_buffer_size" value="2"/> 684 <param name="fetch_buffer_size" value="2"/> 685 <param name="prefetch_buffer_size" value="2"/> 686 <param name="writeback_buffer_size" value="2"/> 687 <param name="device_type" value="0"/> 688 <param name="clockrate" value="0"/> 689 <param name="tech_type" value="0"/> 690 <param name="Directory_type" value="2"/> 691 <param name="core_type" value="1"/> 692 <param name="wire_mat_type" value="2"/> 693 <param name="wire_type" value="0"/> 694 <param name="miss_buffer_assoc" value="0"/> 695 <param name="fetch_buffer_assoc" value="0"/> 696 <param name="prefetch_buffer_assoc" value="0"/> 697 <param name="writeback_buffer_assoc" value="0"/> 698 <param name="miss_buffer_banks" value="1"/> 699 <param name="fetch_buffer_banks" value="1"/> 700 <param name="prefetch_buffer_banks" value="1"/> 701 <param name="writeback_buffer_banks" value="1"/> 702 <param name="cache_access_mode" value="0"/> 703 <param name="miss_buff_access_mode" value="2"/> 704 <param name="fetch_buff_access_mode" value="2"/> 705 <param name="prefetch_buff_access_mode" value="2"/> 706 <param name="writeback_buff_access_mode"value="2"/> 707 <param name="cache_rw_ports" value="1"/> 708 <param name="cache_rd_ports" value="0"/> 709 <param name="cache_wr_ports" value="0"/> 710 <param name="cache_se_rd_ports" value="0"/> 711 <param name="cache_search_ports" value="0"/> 712 <param name="miss_buff_rw_ports" value="1"/> 713 <param name="miss_buff_rd_ports" value="0"/> 714 <param name="miss_buff_wr_ports" value="0"/> 715 <param name="miss_buff_se_rd_ports" value="0"/> 716 <param name="miss_buff_search_ports" value="1"/> 717 <param name="fetch_buff_rw_ports" value="1"/> 718 <param name="fetch_buff_rd_ports" value="0"/> 719 <param name="fetch_buff_wr_ports" value="0"/> 720 <param name="fetch_buff_se_rd_ports" value="0"/> 721 <param name="fetch_buff_search_ports" value="1"/> 722 <param name="pf_buff_rw_ports" value="1"/> 723 <param name="pf_buff_rd_ports" value="0"/> 724 <param name="pf_buff_wr_ports" value="0"/> 725 <param name="pf_buff_se_rd_ports" value="0"/> 726 <param name="pf_buff_search_ports" value="1"/> 727 <param name="wb_buff_rw_ports" value="1"/> 728 <param name="wb_buff_rd_ports" value="0"/> 729 <param name="wb_buff_wr_ports" value="0"/> 730 <param name="wb_buff_se_rd_ports" value="0"/> 731 <param name="wb_buff_search_ports" value="1"/> 732 <param name="pure_ram" value="0"/> 733 <stat name="num_data_array_reads" value="2879"/> 734 <stat name="num_data_array_writes" value="182"/> 735 <stat name="num_tag_array_reads" value="8263"/> 736 <stat name="num_tag_array_writes" value="551"/> 737 <stat name="read_misses" value="156"/> 738 <stat name="write_misses" value="92"/> 739 <stat name="conflicts" value="148"/> 740 <stat name="duty_cycle" value="1"/> 741 </component> 742 <component id="system.l1_cntrl1.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> 743 <param name="level" value="2"/> 744 <param name="size" value="2097152"/> 745 <param name="block_size" value="64"/> 746 <param name="assoc" value="16"/> 747 <param name="num_banks" value="1"/> 748 <param name="latency" value="10"/> 749 <param name="throughput" value="1"/> 750 <param name="miss_buffer_size" value="2"/> 751 <param name="fetch_buffer_size" value="2"/> 752 <param name="prefetch_buffer_size" value="2"/> 753 <param name="writeback_buffer_size" value="2"/> 754 <param name="device_type" value="0"/> 755 <param name="clockrate" value="0"/> 756 <param name="tech_type" value="0"/> 757 <param name="Directory_type" value="2"/> 758 <param name="core_type" value="1"/> 759 <param name="wire_mat_type" value="2"/> 760 <param name="wire_type" value="0"/> 761 <param name="miss_buffer_assoc" value="0"/> 762 <param name="fetch_buffer_assoc" value="0"/> 763 <param name="prefetch_buffer_assoc" value="0"/> 764 <param name="writeback_buffer_assoc" value="0"/> 765 <param name="miss_buffer_banks" value="1"/> 766 <param name="fetch_buffer_banks" value="1"/> 767 <param name="prefetch_buffer_banks" value="1"/> 768 <param name="writeback_buffer_banks" value="1"/> 769 <param name="cache_access_mode" value="1"/> 770 <param name="miss_buff_access_mode" value="0"/> 771 <param name="fetch_buff_access_mode" value="0"/> 772 <param name="prefetch_buff_access_mode" value="0"/> 773 <param name="writeback_buff_access_mode"value="0"/> 774 <param name="cache_rw_ports" value="1"/> 775 <param name="cache_rd_ports" value="0"/> 776 <param name="cache_wr_ports" value="0"/> 777 <param name="cache_se_rd_ports" value="0"/> 778 <param name="cache_search_ports" value="0"/> 779 <param name="miss_buff_rw_ports" value="1"/> 780 <param name="miss_buff_rd_ports" value="0"/> 781 <param name="miss_buff_wr_ports" value="0"/> 782 <param name="miss_buff_se_rd_ports" value="0"/> 783 <param name="miss_buff_search_ports" value="1"/> 784 <param name="fetch_buff_rw_ports" value="1"/> 785 <param name="fetch_buff_rd_ports" value="0"/> 786 <param name="fetch_buff_wr_ports" value="0"/> 787 <param name="fetch_buff_se_rd_ports" value="0"/> 788 <param name="fetch_buff_search_ports" value="1"/> 789 <param name="pf_buff_rw_ports" value="1"/> 790 <param name="pf_buff_rd_ports" value="0"/> 791 <param name="pf_buff_wr_ports" value="0"/> 792 <param name="pf_buff_se_rd_ports" value="0"/> 793 <param name="pf_buff_search_ports" value="1"/> 794 <param name="wb_buff_rw_ports" value="1"/> 795 <param name="wb_buff_rd_ports" value="0"/> 796 <param name="wb_buff_wr_ports" value="0"/> 797 <param name="wb_buff_se_rd_ports" value="0"/> 798 <param name="wb_buff_search_ports" value="1"/> 799 <param name="pure_ram" value="0"/> 800 <stat name="num_data_array_reads" value="3"/> 801 <stat name="num_data_array_writes" value="10"/> 802 <stat name="num_tag_array_reads" value="5210"/> 803 <stat name="num_tag_array_writes" value="13"/> 804 <stat name="read_misses" value="462"/> 805 <stat name="write_misses" value="0"/> 806 <stat name="conflicts" value="462"/> 807 <stat name="duty_cycle" value="1"/> 808 </component> 809 </component> 810 </component> 811</component> 812