uca.cc revision 10234
110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu 3510152Satgutier@umich.edu#include <cmath> 3610152Satgutier@umich.edu#include <iostream> 3710152Satgutier@umich.edu 3810152Satgutier@umich.edu#include "uca.h" 3910152Satgutier@umich.edu 4010152Satgutier@umich.eduUCA::UCA(const DynamicParameter & dyn_p) 4110234Syasuko.eckert@amd.com : dp(dyn_p), bank(dp), nbanks(g_ip->nbanks), refresh_power(0) { 4210234Syasuko.eckert@amd.com int num_banks_ver_dir = 1 << ((bank.area.h > bank.area.w) ? _log2(nbanks) 4310234Syasuko.eckert@amd.com / 2 : (_log2(nbanks) - _log2(nbanks) / 2)); 4410234Syasuko.eckert@amd.com int num_banks_hor_dir = nbanks / num_banks_ver_dir; 4510152Satgutier@umich.edu 4610234Syasuko.eckert@amd.com if (dp.use_inp_params) { 4710234Syasuko.eckert@amd.com RWP = dp.num_rw_ports; 4810234Syasuko.eckert@amd.com ERP = dp.num_rd_ports; 4910234Syasuko.eckert@amd.com EWP = dp.num_wr_ports; 5010234Syasuko.eckert@amd.com SCHP = dp.num_search_ports; 5110234Syasuko.eckert@amd.com } else { 5210234Syasuko.eckert@amd.com RWP = g_ip->num_rw_ports; 5310234Syasuko.eckert@amd.com ERP = g_ip->num_rd_ports; 5410234Syasuko.eckert@amd.com EWP = g_ip->num_wr_ports; 5510234Syasuko.eckert@amd.com SCHP = g_ip->num_search_ports; 5610234Syasuko.eckert@amd.com } 5710152Satgutier@umich.edu 5810234Syasuko.eckert@amd.com num_addr_b_bank = (dp.number_addr_bits_mat + dp.number_subbanks_decode) * 5910234Syasuko.eckert@amd.com (RWP + ERP + EWP); 6010234Syasuko.eckert@amd.com num_di_b_bank = dp.num_di_b_bank_per_port * (RWP + EWP); 6110234Syasuko.eckert@amd.com num_do_b_bank = dp.num_do_b_bank_per_port * (RWP + ERP); 6210234Syasuko.eckert@amd.com num_si_b_bank = dp.num_si_b_bank_per_port * SCHP; 6310234Syasuko.eckert@amd.com num_so_b_bank = dp.num_so_b_bank_per_port * SCHP; 6410152Satgutier@umich.edu 6510234Syasuko.eckert@amd.com if (!dp.fully_assoc && !dp.pure_cam) { 6610152Satgutier@umich.edu 6710234Syasuko.eckert@amd.com if (g_ip->fast_access && dp.is_tag == false) { 6810234Syasuko.eckert@amd.com num_do_b_bank *= g_ip->data_assoc; 6910234Syasuko.eckert@amd.com } 7010152Satgutier@umich.edu 7110234Syasuko.eckert@amd.com htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 7210234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 0, 7310234Syasuko.eckert@amd.com num_do_b_bank, 0, num_banks_ver_dir * 2, 7410234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Add_htree, true); 7510234Syasuko.eckert@amd.com htree_in_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 7610234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 0, 7710234Syasuko.eckert@amd.com num_do_b_bank, 0, num_banks_ver_dir * 2, 7810234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Data_in_htree, true); 7910234Syasuko.eckert@amd.com htree_out_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 8010234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 0, 8110234Syasuko.eckert@amd.com num_do_b_bank, 0, num_banks_ver_dir * 2, 8210234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Data_out_htree, true); 8310234Syasuko.eckert@amd.com } 8410152Satgutier@umich.edu 8510234Syasuko.eckert@amd.com else { 8610152Satgutier@umich.edu 8710234Syasuko.eckert@amd.com htree_in_add = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 8810234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 8910234Syasuko.eckert@amd.com num_si_b_bank, num_do_b_bank, num_so_b_bank, 9010234Syasuko.eckert@amd.com num_banks_ver_dir * 2, num_banks_hor_dir * 2, 9110234Syasuko.eckert@amd.com Add_htree, true); 9210234Syasuko.eckert@amd.com htree_in_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 9310234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 9410234Syasuko.eckert@amd.com num_si_b_bank, num_do_b_bank, num_so_b_bank, 9510234Syasuko.eckert@amd.com num_banks_ver_dir * 2, num_banks_hor_dir * 2, 9610234Syasuko.eckert@amd.com Data_in_htree, true); 9710234Syasuko.eckert@amd.com htree_out_data = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 9810234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 9910234Syasuko.eckert@amd.com num_si_b_bank, num_do_b_bank, 10010234Syasuko.eckert@amd.com num_so_b_bank, num_banks_ver_dir * 2, 10110234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Data_out_htree, true); 10210234Syasuko.eckert@amd.com htree_in_search = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 10310234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 10410234Syasuko.eckert@amd.com num_si_b_bank, num_do_b_bank, 10510234Syasuko.eckert@amd.com num_so_b_bank, num_banks_ver_dir * 2, 10610234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Data_in_htree, true); 10710234Syasuko.eckert@amd.com htree_out_search = new Htree2(g_ip->wt, bank.area.w, bank.area.h, 10810234Syasuko.eckert@amd.com num_addr_b_bank, num_di_b_bank, 10910234Syasuko.eckert@amd.com num_si_b_bank, num_do_b_bank, 11010234Syasuko.eckert@amd.com num_so_b_bank, num_banks_ver_dir * 2, 11110234Syasuko.eckert@amd.com num_banks_hor_dir * 2, Data_out_htree, 11210234Syasuko.eckert@amd.com true); 11310234Syasuko.eckert@amd.com } 11410152Satgutier@umich.edu 11510234Syasuko.eckert@amd.com area.w = htree_in_data->area.w; 11610234Syasuko.eckert@amd.com area.h = htree_in_data->area.h; 11710152Satgutier@umich.edu 11810234Syasuko.eckert@amd.com area_all_dataramcells = bank.mat.subarray.get_total_cell_area() * dp.num_subarrays * g_ip->nbanks; 11910152Satgutier@umich.edu// cout<<"area cell"<<area_all_dataramcells<<endl; 12010152Satgutier@umich.edu// cout<<area.get_area()<<endl; 12110234Syasuko.eckert@amd.com // delay calculation 12210234Syasuko.eckert@amd.com double inrisetime = 0.0; 12310234Syasuko.eckert@amd.com compute_delays(inrisetime); 12410234Syasuko.eckert@amd.com compute_power_energy(); 12510152Satgutier@umich.edu} 12610152Satgutier@umich.edu 12710152Satgutier@umich.edu 12810152Satgutier@umich.edu 12910234Syasuko.eckert@amd.comUCA::~UCA() { 13010234Syasuko.eckert@amd.com delete htree_in_add; 13110234Syasuko.eckert@amd.com delete htree_in_data; 13210234Syasuko.eckert@amd.com delete htree_out_data; 13310152Satgutier@umich.edu} 13410152Satgutier@umich.edu 13510152Satgutier@umich.edu 13610152Satgutier@umich.edu 13710234Syasuko.eckert@amd.comdouble UCA::compute_delays(double inrisetime) { 13810234Syasuko.eckert@amd.com double outrisetime = bank.compute_delays(inrisetime); 13910152Satgutier@umich.edu 14010234Syasuko.eckert@amd.com double delay_array_to_mat = htree_in_add->delay + bank.htree_in_add->delay; 14110234Syasuko.eckert@amd.com double max_delay_before_row_decoder = delay_array_to_mat + bank.mat.r_predec->delay; 14210234Syasuko.eckert@amd.com delay_array_to_sa_mux_lev_1_decoder = delay_array_to_mat + 14310234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_predec->delay + 14410234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_dec->delay; 14510234Syasuko.eckert@amd.com delay_array_to_sa_mux_lev_2_decoder = delay_array_to_mat + 14610234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->delay + 14710234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_dec->delay; 14810234Syasuko.eckert@amd.com double delay_inside_mat = bank.mat.row_dec->delay + bank.mat.delay_bitline + bank.mat.delay_sa; 14910152Satgutier@umich.edu 15010234Syasuko.eckert@amd.com delay_before_subarray_output_driver = 15110234Syasuko.eckert@amd.com MAX(MAX(max_delay_before_row_decoder + delay_inside_mat, // row_path 15210234Syasuko.eckert@amd.com delay_array_to_mat + bank.mat.b_mux_predec->delay + bank.mat.bit_mux_dec->delay + bank.mat.delay_sa), // col_path 15310234Syasuko.eckert@amd.com MAX(delay_array_to_sa_mux_lev_1_decoder, // sa_mux_lev_1_path 15410234Syasuko.eckert@amd.com delay_array_to_sa_mux_lev_2_decoder)); // sa_mux_lev_2_path 15510234Syasuko.eckert@amd.com delay_from_subarray_out_drv_to_out = bank.mat.delay_subarray_out_drv_htree + 15610234Syasuko.eckert@amd.com bank.htree_out_data->delay + htree_out_data->delay; 15710234Syasuko.eckert@amd.com access_time = bank.mat.delay_comparator; 15810152Satgutier@umich.edu 15910234Syasuko.eckert@amd.com double ram_delay_inside_mat; 16010234Syasuko.eckert@amd.com if (dp.fully_assoc) { 16110234Syasuko.eckert@amd.com //delay of FA contains both CAM tag and RAM data 16210234Syasuko.eckert@amd.com { //delay of CAM 16310234Syasuko.eckert@amd.com ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline; 16410234Syasuko.eckert@amd.com access_time = htree_in_add->delay + bank.htree_in_add->delay; 16510234Syasuko.eckert@amd.com //delay of fully-associative data array 16610234Syasuko.eckert@amd.com access_time += ram_delay_inside_mat + delay_from_subarray_out_drv_to_out; 16710234Syasuko.eckert@amd.com } 16810234Syasuko.eckert@amd.com } else { 16910234Syasuko.eckert@amd.com access_time = delay_before_subarray_output_driver + delay_from_subarray_out_drv_to_out; //data_acc_path 17010152Satgutier@umich.edu } 17110152Satgutier@umich.edu 17210234Syasuko.eckert@amd.com if (dp.is_main_mem) { 17310234Syasuko.eckert@amd.com double t_rcd = max_delay_before_row_decoder + delay_inside_mat; 17410234Syasuko.eckert@amd.com double cas_latency = MAX(delay_array_to_sa_mux_lev_1_decoder, delay_array_to_sa_mux_lev_2_decoder) + 17510234Syasuko.eckert@amd.com delay_from_subarray_out_drv_to_out; 17610234Syasuko.eckert@amd.com access_time = t_rcd + cas_latency; 17710234Syasuko.eckert@amd.com } 17810152Satgutier@umich.edu 17910234Syasuko.eckert@amd.com double temp; 18010152Satgutier@umich.edu 18110234Syasuko.eckert@amd.com if (!dp.fully_assoc) { 18210234Syasuko.eckert@amd.com temp = delay_inside_mat + bank.mat.delay_wl_reset + bank.mat.delay_bl_restore;//TODO: Sheng: revisit 18310234Syasuko.eckert@amd.com if (dp.is_dram) { 18410234Syasuko.eckert@amd.com temp += bank.mat.delay_writeback; // temp stores random cycle time 18510234Syasuko.eckert@amd.com } 18610152Satgutier@umich.edu 18710152Satgutier@umich.edu 18810234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.r_predec->delay); 18910234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.b_mux_predec->delay); 19010234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); 19110234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); 19210234Syasuko.eckert@amd.com } else { 19310234Syasuko.eckert@amd.com ram_delay_inside_mat = bank.mat.delay_bitline + bank.mat.delay_matchchline; 19410234Syasuko.eckert@amd.com temp = ram_delay_inside_mat + bank.mat.delay_cam_sl_restore + bank.mat.delay_cam_ml_reset + bank.mat.delay_bl_restore 19510234Syasuko.eckert@amd.com + bank.mat.delay_hit_miss_reset + bank.mat.delay_wl_reset; 19610152Satgutier@umich.edu 19710234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.b_mux_predec->delay);//TODO: Sheng revisit whether distinguish cam and ram bitline etc. 19810234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.sa_mux_lev_1_predec->delay); 19910234Syasuko.eckert@amd.com temp = MAX(temp, bank.mat.sa_mux_lev_2_predec->delay); 20010234Syasuko.eckert@amd.com } 20110152Satgutier@umich.edu 20210234Syasuko.eckert@amd.com // The following is true only if the input parameter "repeaters_in_htree" is set to false --Nav 20310234Syasuko.eckert@amd.com if (g_ip->rpters_in_htree == false) { 20410234Syasuko.eckert@amd.com temp = MAX(temp, bank.htree_in_add->max_unpipelined_link_delay); 20510234Syasuko.eckert@amd.com } 20610234Syasuko.eckert@amd.com cycle_time = temp; 20710152Satgutier@umich.edu 20810234Syasuko.eckert@amd.com double delay_req_network = max_delay_before_row_decoder; 20910234Syasuko.eckert@amd.com double delay_rep_network = delay_from_subarray_out_drv_to_out; 21010234Syasuko.eckert@amd.com multisubbank_interleave_cycle_time = MAX(delay_req_network, delay_rep_network); 21110234Syasuko.eckert@amd.com 21210234Syasuko.eckert@amd.com if (dp.is_main_mem) { 21310234Syasuko.eckert@amd.com multisubbank_interleave_cycle_time = htree_in_add->delay; 21410234Syasuko.eckert@amd.com precharge_delay = htree_in_add->delay + 21510234Syasuko.eckert@amd.com bank.htree_in_add->delay + bank.mat.delay_writeback + 21610234Syasuko.eckert@amd.com bank.mat.delay_wl_reset + bank.mat.delay_bl_restore; 21710234Syasuko.eckert@amd.com cycle_time = access_time + precharge_delay; 21810234Syasuko.eckert@amd.com } else { 21910234Syasuko.eckert@amd.com precharge_delay = 0; 22010234Syasuko.eckert@amd.com } 22110234Syasuko.eckert@amd.com 22210234Syasuko.eckert@amd.com double dram_array_availability = 0; 22310234Syasuko.eckert@amd.com if (dp.is_dram) { 22410234Syasuko.eckert@amd.com dram_array_availability = (1 - dp.num_r_subarray * cycle_time / dp.dram_refresh_period) * 100; 22510234Syasuko.eckert@amd.com } 22610234Syasuko.eckert@amd.com 22710234Syasuko.eckert@amd.com return outrisetime; 22810152Satgutier@umich.edu} 22910152Satgutier@umich.edu 23010152Satgutier@umich.edu 23110152Satgutier@umich.edu 23210152Satgutier@umich.edu// note: currently, power numbers are for a bank of an array 23310234Syasuko.eckert@amd.comvoid UCA::compute_power_energy() { 23410234Syasuko.eckert@amd.com bank.compute_power_energy(); 23510234Syasuko.eckert@amd.com power = bank.power; 23610152Satgutier@umich.edu 23710234Syasuko.eckert@amd.com power_routing_to_bank.readOp.dynamic = htree_in_add->power.readOp.dynamic + htree_out_data->power.readOp.dynamic; 23810234Syasuko.eckert@amd.com power_routing_to_bank.writeOp.dynamic = htree_in_add->power.readOp.dynamic + htree_in_data->power.readOp.dynamic; 23910234Syasuko.eckert@amd.com if (dp.fully_assoc || dp.pure_cam) 24010234Syasuko.eckert@amd.com power_routing_to_bank.searchOp.dynamic = 24110234Syasuko.eckert@amd.com htree_in_search->power.searchOp.dynamic + 24210234Syasuko.eckert@amd.com htree_out_search->power.searchOp.dynamic; 24310152Satgutier@umich.edu 24410234Syasuko.eckert@amd.com power_routing_to_bank.readOp.leakage += 24510234Syasuko.eckert@amd.com htree_in_add->power.readOp.leakage + 24610234Syasuko.eckert@amd.com htree_in_data->power.readOp.leakage + 24710234Syasuko.eckert@amd.com htree_out_data->power.readOp.leakage; 24810152Satgutier@umich.edu 24910234Syasuko.eckert@amd.com power_routing_to_bank.readOp.gate_leakage += 25010234Syasuko.eckert@amd.com htree_in_add->power.readOp.gate_leakage + 25110234Syasuko.eckert@amd.com htree_in_data->power.readOp.gate_leakage + 25210234Syasuko.eckert@amd.com htree_out_data->power.readOp.gate_leakage; 25310234Syasuko.eckert@amd.com if (dp.fully_assoc || dp.pure_cam) { 25410152Satgutier@umich.edu power_routing_to_bank.readOp.leakage += htree_in_search->power.readOp.leakage + htree_out_search->power.readOp.leakage; 25510152Satgutier@umich.edu power_routing_to_bank.readOp.gate_leakage += htree_in_search->power.readOp.gate_leakage + htree_out_search->power.readOp.gate_leakage; 25610234Syasuko.eckert@amd.com } 25710152Satgutier@umich.edu 25810234Syasuko.eckert@amd.com power.searchOp.dynamic += power_routing_to_bank.searchOp.dynamic; 25910234Syasuko.eckert@amd.com power.readOp.dynamic += power_routing_to_bank.readOp.dynamic; 26010234Syasuko.eckert@amd.com power.readOp.leakage += power_routing_to_bank.readOp.leakage; 26110234Syasuko.eckert@amd.com power.readOp.gate_leakage += power_routing_to_bank.readOp.gate_leakage; 26210152Satgutier@umich.edu 26310234Syasuko.eckert@amd.com // calculate total write energy per access 26410234Syasuko.eckert@amd.com power.writeOp.dynamic = power.readOp.dynamic 26510234Syasuko.eckert@amd.com - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir 26610234Syasuko.eckert@amd.com + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir 26710234Syasuko.eckert@amd.com - power_routing_to_bank.readOp.dynamic 26810234Syasuko.eckert@amd.com + power_routing_to_bank.writeOp.dynamic 26910234Syasuko.eckert@amd.com + bank.htree_in_data->power.readOp.dynamic 27010234Syasuko.eckert@amd.com - bank.htree_out_data->power.readOp.dynamic; 27110152Satgutier@umich.edu 27210234Syasuko.eckert@amd.com if (dp.is_dram == false) { 27310234Syasuko.eckert@amd.com power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; 27410234Syasuko.eckert@amd.com } 27510152Satgutier@umich.edu 27610234Syasuko.eckert@amd.com dyn_read_energy_from_closed_page = power.readOp.dynamic; 27710234Syasuko.eckert@amd.com dyn_read_energy_from_open_page = power.readOp.dynamic - 27810234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.dynamic + 27910234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.dynamic + 28010234Syasuko.eckert@amd.com bank.mat.power_bl_precharge_eq_drv.readOp.dynamic + 28110234Syasuko.eckert@amd.com bank.mat.power_sa.readOp.dynamic + 28210234Syasuko.eckert@amd.com bank.mat.power_bitline.readOp.dynamic) * dp.num_act_mats_hor_dir; 28310152Satgutier@umich.edu 28410234Syasuko.eckert@amd.com dyn_read_energy_remaining_words_in_burst = 28510234Syasuko.eckert@amd.com (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1) * 28610234Syasuko.eckert@amd.com ((bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + 28710234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + 28810234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + 28910234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + 29010234Syasuko.eckert@amd.com bank.mat.power_subarray_out_drv.readOp.dynamic) * dp.num_act_mats_hor_dir + 29110234Syasuko.eckert@amd.com bank.htree_out_data->power.readOp.dynamic + 29210234Syasuko.eckert@amd.com power_routing_to_bank.readOp.dynamic); 29310234Syasuko.eckert@amd.com dyn_read_energy_from_closed_page += dyn_read_energy_remaining_words_in_burst; 29410234Syasuko.eckert@amd.com dyn_read_energy_from_open_page += dyn_read_energy_remaining_words_in_burst; 29510152Satgutier@umich.edu 29610234Syasuko.eckert@amd.com activate_energy = htree_in_add->power.readOp.dynamic + 29710234Syasuko.eckert@amd.com bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_act + 29810234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.dynamic + 29910234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.dynamic + 30010234Syasuko.eckert@amd.com bank.mat.power_sa.readOp.dynamic) * dp.num_act_mats_hor_dir; 30110234Syasuko.eckert@amd.com read_energy = (htree_in_add->power.readOp.dynamic + 30210234Syasuko.eckert@amd.com bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_rd_or_wr + 30310234Syasuko.eckert@amd.com (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + 30410234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + 30510234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + 30610234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic + 30710234Syasuko.eckert@amd.com bank.mat.power_subarray_out_drv.readOp.dynamic) * dp.num_act_mats_hor_dir + 30810234Syasuko.eckert@amd.com bank.htree_out_data->power.readOp.dynamic + 30910234Syasuko.eckert@amd.com htree_in_data->power.readOp.dynamic) * g_ip->burst_len; 31010234Syasuko.eckert@amd.com write_energy = (htree_in_add->power.readOp.dynamic + 31110234Syasuko.eckert@amd.com bank.htree_in_add->power_bit.readOp.dynamic * bank.num_addr_b_routed_to_mat_for_rd_or_wr + 31210234Syasuko.eckert@amd.com htree_in_data->power.readOp.dynamic + 31310234Syasuko.eckert@amd.com bank.htree_in_data->power.readOp.dynamic + 31410234Syasuko.eckert@amd.com (bank.mat.sa_mux_lev_1_predec->power.readOp.dynamic + 31510234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.dynamic + 31610234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.dynamic + 31710234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.dynamic) * dp.num_act_mats_hor_dir) * g_ip->burst_len; 31810234Syasuko.eckert@amd.com precharge_energy = (bank.mat.power_bitline.readOp.dynamic + 31910234Syasuko.eckert@amd.com bank.mat.power_bl_precharge_eq_drv.readOp.dynamic) * dp.num_act_mats_hor_dir; 32010152Satgutier@umich.edu 32110234Syasuko.eckert@amd.com leak_power_subbank_closed_page = 32210234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.leakage + 32310234Syasuko.eckert@amd.com bank.mat.b_mux_predec->power.readOp.leakage + 32410234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + 32510234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + 32610234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.leakage + 32710234Syasuko.eckert@amd.com bank.mat.power_bit_mux_decoders.readOp.leakage + 32810234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + 32910234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + 33010234Syasuko.eckert@amd.com bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir; 33110152Satgutier@umich.edu 33210234Syasuko.eckert@amd.com leak_power_subbank_closed_page += 33310234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.gate_leakage + 33410234Syasuko.eckert@amd.com bank.mat.b_mux_predec->power.readOp.gate_leakage + 33510234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + 33610234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + 33710234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.gate_leakage + 33810234Syasuko.eckert@amd.com bank.mat.power_bit_mux_decoders.readOp.gate_leakage + 33910234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + 34010234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage) * dp.num_act_mats_hor_dir; //+ 34110234Syasuko.eckert@amd.com //bank.mat.leak_power_sense_amps_closed_page_state) * dp.num_act_mats_hor_dir; 34210152Satgutier@umich.edu 34310234Syasuko.eckert@amd.com leak_power_subbank_open_page = 34410234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.leakage + 34510234Syasuko.eckert@amd.com bank.mat.b_mux_predec->power.readOp.leakage + 34610234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_predec->power.readOp.leakage + 34710234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.leakage + 34810234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.leakage + 34910234Syasuko.eckert@amd.com bank.mat.power_bit_mux_decoders.readOp.leakage + 35010234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.leakage + 35110234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.leakage + 35210234Syasuko.eckert@amd.com bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir; 35310152Satgutier@umich.edu 35410234Syasuko.eckert@amd.com leak_power_subbank_open_page += 35510234Syasuko.eckert@amd.com (bank.mat.r_predec->power.readOp.gate_leakage + 35610234Syasuko.eckert@amd.com bank.mat.b_mux_predec->power.readOp.gate_leakage + 35710234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_1_predec->power.readOp.gate_leakage + 35810234Syasuko.eckert@amd.com bank.mat.sa_mux_lev_2_predec->power.readOp.gate_leakage + 35910234Syasuko.eckert@amd.com bank.mat.power_row_decoders.readOp.gate_leakage + 36010234Syasuko.eckert@amd.com bank.mat.power_bit_mux_decoders.readOp.gate_leakage + 36110234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_1_decoders.readOp.gate_leakage + 36210234Syasuko.eckert@amd.com bank.mat.power_sa_mux_lev_2_decoders.readOp.gate_leakage ) * dp.num_act_mats_hor_dir; 36310234Syasuko.eckert@amd.com //bank.mat.leak_power_sense_amps_open_page_state) * dp.num_act_mats_hor_dir; 36410152Satgutier@umich.edu 36510234Syasuko.eckert@amd.com leak_power_request_and_reply_networks = 36610234Syasuko.eckert@amd.com power_routing_to_bank.readOp.leakage + 36710234Syasuko.eckert@amd.com bank.htree_in_add->power.readOp.leakage + 36810234Syasuko.eckert@amd.com bank.htree_in_data->power.readOp.leakage + 36910234Syasuko.eckert@amd.com bank.htree_out_data->power.readOp.leakage; 37010152Satgutier@umich.edu 37110234Syasuko.eckert@amd.com leak_power_request_and_reply_networks += 37210234Syasuko.eckert@amd.com power_routing_to_bank.readOp.gate_leakage + 37310234Syasuko.eckert@amd.com bank.htree_in_add->power.readOp.gate_leakage + 37410234Syasuko.eckert@amd.com bank.htree_in_data->power.readOp.gate_leakage + 37510234Syasuko.eckert@amd.com bank.htree_out_data->power.readOp.gate_leakage; 37610152Satgutier@umich.edu 37710234Syasuko.eckert@amd.com if (dp.fully_assoc || dp.pure_cam) { 37810152Satgutier@umich.edu leak_power_request_and_reply_networks += htree_in_search->power.readOp.leakage + htree_out_search->power.readOp.leakage; 37910152Satgutier@umich.edu leak_power_request_and_reply_networks += htree_in_search->power.readOp.gate_leakage + htree_out_search->power.readOp.gate_leakage; 38010234Syasuko.eckert@amd.com } 38110152Satgutier@umich.edu 38210152Satgutier@umich.edu 38310234Syasuko.eckert@amd.com // if DRAM, add contribution of power spent in row predecoder drivers, 38410234Syasuko.eckert@amd.com // blocks and decoders to refresh power 38510234Syasuko.eckert@amd.com if (dp.is_dram) { 38610234Syasuko.eckert@amd.com refresh_power = (bank.mat.r_predec->power.readOp.dynamic * dp.num_act_mats_hor_dir + 38710234Syasuko.eckert@amd.com bank.mat.row_dec->power.readOp.dynamic) * dp.num_r_subarray * dp.num_subarrays; 38810234Syasuko.eckert@amd.com refresh_power += bank.mat.per_bitline_read_energy * dp.num_c_subarray * dp.num_r_subarray * dp.num_subarrays; 38910234Syasuko.eckert@amd.com refresh_power += bank.mat.power_bl_precharge_eq_drv.readOp.dynamic * dp.num_act_mats_hor_dir; 39010234Syasuko.eckert@amd.com refresh_power += bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; 39110234Syasuko.eckert@amd.com refresh_power /= dp.dram_refresh_period; 39210234Syasuko.eckert@amd.com } 39310152Satgutier@umich.edu 39410152Satgutier@umich.edu 39510234Syasuko.eckert@amd.com if (dp.is_tag == false) { 39610234Syasuko.eckert@amd.com power.readOp.dynamic = dyn_read_energy_from_closed_page; 39710234Syasuko.eckert@amd.com power.writeOp.dynamic = dyn_read_energy_from_closed_page 39810234Syasuko.eckert@amd.com - dyn_read_energy_remaining_words_in_burst 39910234Syasuko.eckert@amd.com - bank.mat.power_bitline.readOp.dynamic * dp.num_act_mats_hor_dir 40010234Syasuko.eckert@amd.com + bank.mat.power_bitline.writeOp.dynamic * dp.num_act_mats_hor_dir 40110234Syasuko.eckert@amd.com + (power_routing_to_bank.writeOp.dynamic - 40210234Syasuko.eckert@amd.com power_routing_to_bank.readOp.dynamic - 40310234Syasuko.eckert@amd.com bank.htree_out_data->power.readOp.dynamic + 40410234Syasuko.eckert@amd.com bank.htree_in_data->power.readOp.dynamic) * 40510234Syasuko.eckert@amd.com (MAX((g_ip->burst_len / g_ip->int_prefetch_w), 1) - 1); //FIXME 40610152Satgutier@umich.edu 40710234Syasuko.eckert@amd.com if (dp.is_dram == false) { 40810234Syasuko.eckert@amd.com power.writeOp.dynamic -= bank.mat.power_sa.readOp.dynamic * dp.num_act_mats_hor_dir; 40910234Syasuko.eckert@amd.com } 41010234Syasuko.eckert@amd.com } 41110234Syasuko.eckert@amd.com 41210234Syasuko.eckert@amd.com // if DRAM, add refresh power to total leakage 41310234Syasuko.eckert@amd.com if (dp.is_dram) { 41410234Syasuko.eckert@amd.com power.readOp.leakage += refresh_power; 41510234Syasuko.eckert@amd.com } 41610234Syasuko.eckert@amd.com 41710234Syasuko.eckert@amd.com // TODO: below should be avoided. 41810234Syasuko.eckert@amd.com /*if (dp.is_main_mem) 41910152Satgutier@umich.edu { 42010234Syasuko.eckert@amd.com power.readOp.leakage += MAIN_MEM_PER_CHIP_STANDBY_CURRENT_mA * 1e-3 * g_tp.peri_global.Vdd / g_ip->nbanks; 42110234Syasuko.eckert@amd.com }*/ 42210152Satgutier@umich.edu 42310234Syasuko.eckert@amd.com assert(power.readOp.dynamic > 0); 42410234Syasuko.eckert@amd.com assert(power.writeOp.dynamic > 0); 42510234Syasuko.eckert@amd.com assert(power.readOp.leakage > 0); 42610152Satgutier@umich.edu} 42710152Satgutier@umich.edu 428