technology.cc revision 10234
110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu#include "basic_circuit.h" 3510152Satgutier@umich.edu 3610152Satgutier@umich.edu#include "parameter.h" 3710152Satgutier@umich.edu 3810234Syasuko.eckert@amd.comdouble wire_resistance(double resistivity, double wire_width, 3910234Syasuko.eckert@amd.com double wire_thickness, 4010234Syasuko.eckert@amd.com double barrier_thickness, double dishing_thickness, 4110234Syasuko.eckert@amd.com double alpha_scatter) { 4210234Syasuko.eckert@amd.com double resistance; 4310234Syasuko.eckert@amd.com resistance = alpha_scatter * resistivity / 4410234Syasuko.eckert@amd.com ((wire_thickness - barrier_thickness - dishing_thickness) * 4510234Syasuko.eckert@amd.com (wire_width - 2 * barrier_thickness)); 4610234Syasuko.eckert@amd.com return(resistance); 4710152Satgutier@umich.edu} 4810152Satgutier@umich.edu 4910234Syasuko.eckert@amd.comdouble wire_capacitance(double wire_width, double wire_thickness, 5010234Syasuko.eckert@amd.com double wire_spacing, 5110234Syasuko.eckert@amd.com double ild_thickness, double miller_value, 5210234Syasuko.eckert@amd.com double horiz_dielectric_constant, 5310234Syasuko.eckert@amd.com double vert_dielectric_constant, double fringe_cap) { 5410234Syasuko.eckert@amd.com double vertical_cap, sidewall_cap, total_cap; 5510234Syasuko.eckert@amd.com vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * wire_width / ild_thickness; 5610234Syasuko.eckert@amd.com sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * horiz_dielectric_constant * wire_thickness / wire_spacing; 5710234Syasuko.eckert@amd.com total_cap = vertical_cap + sidewall_cap + fringe_cap; 5810234Syasuko.eckert@amd.com return(total_cap); 5910152Satgutier@umich.edu} 6010152Satgutier@umich.edu 6110152Satgutier@umich.edu 6210234Syasuko.eckert@amd.comvoid init_tech_params(double technology, bool is_tag) { 6310234Syasuko.eckert@amd.com int iter, tech, tech_lo, tech_hi; 6410234Syasuko.eckert@amd.com double curr_alpha, curr_vpp; 6510234Syasuko.eckert@amd.com double wire_width, wire_thickness, wire_spacing, 6610234Syasuko.eckert@amd.com fringe_cap, pmos_to_nmos_sizing_r; 6710152Satgutier@umich.edu// double aspect_ratio,ild_thickness, miller_value = 1.5, horiz_dielectric_constant, vert_dielectric_constant; 6810234Syasuko.eckert@amd.com double barrier_thickness, dishing_thickness, alpha_scatter; 6910234Syasuko.eckert@amd.com double curr_vdd_dram_cell, curr_v_th_dram_access_transistor, curr_I_on_dram_cell, curr_c_dram_cell; 7010152Satgutier@umich.edu 7110234Syasuko.eckert@amd.com uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type; 7210234Syasuko.eckert@amd.com uint32_t peri_global_tech_type = (is_tag) ? g_ip->tag_arr_peri_global_tech_type : g_ip->data_arr_peri_global_tech_type; 7310152Satgutier@umich.edu 7410234Syasuko.eckert@amd.com technology = technology * 1000.0; // in the unit of nm 7510152Satgutier@umich.edu 7610234Syasuko.eckert@amd.com // initialize parameters 7710234Syasuko.eckert@amd.com g_tp.reset(); 7810234Syasuko.eckert@amd.com double gmp_to_gmn_multiplier_periph_global = 0; 7910152Satgutier@umich.edu 8010234Syasuko.eckert@amd.com double curr_Wmemcella_dram, curr_Wmemcellpmos_dram, curr_Wmemcellnmos_dram, 8110234Syasuko.eckert@amd.com curr_area_cell_dram, curr_asp_ratio_cell_dram, curr_Wmemcella_sram, 8210234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram, curr_Wmemcellnmos_sram, curr_area_cell_sram, 8310234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram, curr_I_off_dram_cell_worst_case_length_temp; 8410234Syasuko.eckert@amd.com double curr_Wmemcella_cam, curr_Wmemcellpmos_cam, curr_Wmemcellnmos_cam, curr_area_cell_cam,//Sheng: CAM data 8510234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam; 8610234Syasuko.eckert@amd.com double SENSE_AMP_D, SENSE_AMP_P; // J 8710234Syasuko.eckert@amd.com double area_cell_dram = 0; 8810234Syasuko.eckert@amd.com double asp_ratio_cell_dram = 0; 8910234Syasuko.eckert@amd.com double area_cell_sram = 0; 9010234Syasuko.eckert@amd.com double asp_ratio_cell_sram = 0; 9110234Syasuko.eckert@amd.com double area_cell_cam = 0; 9210234Syasuko.eckert@amd.com double asp_ratio_cell_cam = 0; 9310234Syasuko.eckert@amd.com double mobility_eff_periph_global = 0; 9410234Syasuko.eckert@amd.com double Vdsat_periph_global = 0; 9510234Syasuko.eckert@amd.com double nmos_effective_resistance_multiplier; 9610234Syasuko.eckert@amd.com double width_dram_access_transistor; 9710152Satgutier@umich.edu 9810234Syasuko.eckert@amd.com double curr_logic_scaling_co_eff = 0;//This is based on the reported numbers of Intel Merom 65nm, Penryn45nm and IBM cell 90/65/45 date 9910234Syasuko.eckert@amd.com double curr_core_tx_density = 0;//this is density per um^2; 90, ...22nm based on Intel Penryn 10010234Syasuko.eckert@amd.com double curr_chip_layout_overhead = 0; 10110234Syasuko.eckert@amd.com double curr_macro_layout_overhead = 0; 10210234Syasuko.eckert@amd.com double curr_sckt_co_eff = 0; 10310152Satgutier@umich.edu 10410234Syasuko.eckert@amd.com if (technology < 181 && technology > 179) { 10510152Satgutier@umich.edu tech_lo = 180; 10610152Satgutier@umich.edu tech_hi = 180; 10710234Syasuko.eckert@amd.com } else if (technology < 91 && technology > 89) { 10810234Syasuko.eckert@amd.com tech_lo = 90; 10910234Syasuko.eckert@amd.com tech_hi = 90; 11010234Syasuko.eckert@amd.com } else if (technology < 66 && technology > 64) { 11110234Syasuko.eckert@amd.com tech_lo = 65; 11210234Syasuko.eckert@amd.com tech_hi = 65; 11310234Syasuko.eckert@amd.com } else if (technology < 46 && technology > 44) { 11410234Syasuko.eckert@amd.com tech_lo = 45; 11510234Syasuko.eckert@amd.com tech_hi = 45; 11610234Syasuko.eckert@amd.com } else if (technology < 33 && technology > 31) { 11710234Syasuko.eckert@amd.com tech_lo = 32; 11810234Syasuko.eckert@amd.com tech_hi = 32; 11910234Syasuko.eckert@amd.com } else if (technology < 23 && technology > 21) { 12010234Syasuko.eckert@amd.com tech_lo = 22; 12110234Syasuko.eckert@amd.com tech_hi = 22; 12210234Syasuko.eckert@amd.com if (ram_cell_tech_type == 3 ) { 12310234Syasuko.eckert@amd.com cout << "current version does not support eDRAM technologies at " 12410234Syasuko.eckert@amd.com << "22nm" << endl; 12510234Syasuko.eckert@amd.com exit(0); 12610234Syasuko.eckert@amd.com } 12710234Syasuko.eckert@amd.com } else if (technology < 180 && technology > 90) { 12810234Syasuko.eckert@amd.com tech_lo = 180; 12910234Syasuko.eckert@amd.com tech_hi = 90; 13010234Syasuko.eckert@amd.com } else if (technology < 90 && technology > 65) { 13110234Syasuko.eckert@amd.com tech_lo = 90; 13210234Syasuko.eckert@amd.com tech_hi = 65; 13310234Syasuko.eckert@amd.com } else if (technology < 65 && technology > 45) { 13410234Syasuko.eckert@amd.com tech_lo = 65; 13510234Syasuko.eckert@amd.com tech_hi = 45; 13610234Syasuko.eckert@amd.com } else if (technology < 45 && technology > 32) { 13710234Syasuko.eckert@amd.com tech_lo = 45; 13810234Syasuko.eckert@amd.com tech_hi = 32; 13910234Syasuko.eckert@amd.com } else if (technology < 32 && technology > 22) { 14010234Syasuko.eckert@amd.com tech_lo = 32; 14110234Syasuko.eckert@amd.com tech_hi = 22; 14210152Satgutier@umich.edu } 14310152Satgutier@umich.edu// else if (technology < 22 && technology > 16) 14410152Satgutier@umich.edu// { 14510152Satgutier@umich.edu// tech_lo = 22; 14610152Satgutier@umich.edu// tech_hi = 16; 14710152Satgutier@umich.edu// } 14810234Syasuko.eckert@amd.com else { 14910234Syasuko.eckert@amd.com cout << "Invalid technology nodes" << endl; 15010234Syasuko.eckert@amd.com exit(0); 15110152Satgutier@umich.edu } 15210152Satgutier@umich.edu 15310234Syasuko.eckert@amd.com double vdd[NUMBER_TECH_FLAVORS]; 15410234Syasuko.eckert@amd.com double Lphy[NUMBER_TECH_FLAVORS]; 15510234Syasuko.eckert@amd.com double Lelec[NUMBER_TECH_FLAVORS]; 15610234Syasuko.eckert@amd.com double t_ox[NUMBER_TECH_FLAVORS]; 15710234Syasuko.eckert@amd.com double v_th[NUMBER_TECH_FLAVORS]; 15810234Syasuko.eckert@amd.com double c_ox[NUMBER_TECH_FLAVORS]; 15910234Syasuko.eckert@amd.com double mobility_eff[NUMBER_TECH_FLAVORS]; 16010234Syasuko.eckert@amd.com double Vdsat[NUMBER_TECH_FLAVORS]; 16110234Syasuko.eckert@amd.com double c_g_ideal[NUMBER_TECH_FLAVORS]; 16210234Syasuko.eckert@amd.com double c_fringe[NUMBER_TECH_FLAVORS]; 16310234Syasuko.eckert@amd.com double c_junc[NUMBER_TECH_FLAVORS]; 16410234Syasuko.eckert@amd.com double I_on_n[NUMBER_TECH_FLAVORS]; 16510234Syasuko.eckert@amd.com double I_on_p[NUMBER_TECH_FLAVORS]; 16610234Syasuko.eckert@amd.com double Rnchannelon[NUMBER_TECH_FLAVORS]; 16710234Syasuko.eckert@amd.com double Rpchannelon[NUMBER_TECH_FLAVORS]; 16810234Syasuko.eckert@amd.com double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS]; 16910234Syasuko.eckert@amd.com double I_off_n[NUMBER_TECH_FLAVORS][101]; 17010234Syasuko.eckert@amd.com double I_g_on_n[NUMBER_TECH_FLAVORS][101]; 17110234Syasuko.eckert@amd.com double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS]; 17210234Syasuko.eckert@amd.com double long_channel_leakage_reduction[NUMBER_TECH_FLAVORS]; 17310152Satgutier@umich.edu 17410234Syasuko.eckert@amd.com for (iter = 0; iter <= 1; ++iter) { 17510234Syasuko.eckert@amd.com // linear interpolation 17610234Syasuko.eckert@amd.com if (iter == 0) { 17710234Syasuko.eckert@amd.com tech = tech_lo; 17810234Syasuko.eckert@amd.com if (tech_lo == tech_hi) { 17910234Syasuko.eckert@amd.com curr_alpha = 1; 18010234Syasuko.eckert@amd.com } else { 18110234Syasuko.eckert@amd.com curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); 18210234Syasuko.eckert@amd.com } 18310234Syasuko.eckert@amd.com } else { 18410234Syasuko.eckert@amd.com tech = tech_hi; 18510234Syasuko.eckert@amd.com if (tech_lo == tech_hi) { 18610234Syasuko.eckert@amd.com break; 18710234Syasuko.eckert@amd.com } else { 18810234Syasuko.eckert@amd.com curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); 18910234Syasuko.eckert@amd.com } 19010234Syasuko.eckert@amd.com } 19110152Satgutier@umich.edu 19210234Syasuko.eckert@amd.com if (tech == 180) { 19310234Syasuko.eckert@amd.com //180nm technology-node. Corresponds to year 1999 in ITRS 19410234Syasuko.eckert@amd.com //Only HP transistor was of interest that 180nm since leakage power was not a big issue. Performance was the king 19510234Syasuko.eckert@amd.com //MASTAR does not contain data for 0.18um process. The following parameters are projected based on ITRS 2000 update and IBM 0.18 Cu Spice input 19610234Syasuko.eckert@amd.com bool Aggre_proj = false; 19710234Syasuko.eckert@amd.com SENSE_AMP_D = .28e-9; // s 19810234Syasuko.eckert@amd.com SENSE_AMP_P = 14.7e-15; // J 19910234Syasuko.eckert@amd.com vdd[0] = 1.5; 20010234Syasuko.eckert@amd.com Lphy[0] = 0.12;//Lphy is the physical gate-length. micron 20110234Syasuko.eckert@amd.com Lelec[0] = 0.10;//Lelec is the electrical gate-length. micron 20210234Syasuko.eckert@amd.com t_ox[0] = 1.2e-3 * (Aggre_proj ? 1.9 / 1.2 : 2);//micron 20310234Syasuko.eckert@amd.com v_th[0] = Aggre_proj ? 0.36 : 0.4407;//V 20410234Syasuko.eckert@amd.com c_ox[0] = 1.79e-14 * (Aggre_proj ? 1.9 / 1.2 : 2);//F/micron2 20510234Syasuko.eckert@amd.com mobility_eff[0] = 302.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 20610234Syasuko.eckert@amd.com Vdsat[0] = 0.128 * 2; //V 20710234Syasuko.eckert@amd.com c_g_ideal[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 6.64e-16;//F/micron 20810234Syasuko.eckert@amd.com c_fringe[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 0.08e-15;//F/micron 20910234Syasuko.eckert@amd.com c_junc[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 1e-15;//F/micron2 21010234Syasuko.eckert@amd.com I_on_n[0] = 750e-6;//A/micron 21110234Syasuko.eckert@amd.com I_on_p[0] = 350e-6;//A/micron 21210234Syasuko.eckert@amd.com //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline 21310234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.54; 21410234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2.45; 21510234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.22; 21610234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 21710234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 21810234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1; 21910234Syasuko.eckert@amd.com I_off_n[0][0] = 7e-10;//A/micron 22010234Syasuko.eckert@amd.com I_off_n[0][10] = 8.26e-10; 22110234Syasuko.eckert@amd.com I_off_n[0][20] = 9.74e-10; 22210234Syasuko.eckert@amd.com I_off_n[0][30] = 1.15e-9; 22310234Syasuko.eckert@amd.com I_off_n[0][40] = 1.35e-9; 22410234Syasuko.eckert@amd.com I_off_n[0][50] = 1.60e-9; 22510234Syasuko.eckert@amd.com I_off_n[0][60] = 1.88e-9; 22610234Syasuko.eckert@amd.com I_off_n[0][70] = 2.29e-9; 22710234Syasuko.eckert@amd.com I_off_n[0][80] = 2.70e-9; 22810234Syasuko.eckert@amd.com I_off_n[0][90] = 3.19e-9; 22910234Syasuko.eckert@amd.com I_off_n[0][100] = 3.76e-9; 23010152Satgutier@umich.edu 23110234Syasuko.eckert@amd.com I_g_on_n[0][0] = 1.65e-10;//A/micron 23210234Syasuko.eckert@amd.com I_g_on_n[0][10] = 1.65e-10; 23310234Syasuko.eckert@amd.com I_g_on_n[0][20] = 1.65e-10; 23410234Syasuko.eckert@amd.com I_g_on_n[0][30] = 1.65e-10; 23510234Syasuko.eckert@amd.com I_g_on_n[0][40] = 1.65e-10; 23610234Syasuko.eckert@amd.com I_g_on_n[0][50] = 1.65e-10; 23710234Syasuko.eckert@amd.com I_g_on_n[0][60] = 1.65e-10; 23810234Syasuko.eckert@amd.com I_g_on_n[0][70] = 1.65e-10; 23910234Syasuko.eckert@amd.com I_g_on_n[0][80] = 1.65e-10; 24010234Syasuko.eckert@amd.com I_g_on_n[0][90] = 1.65e-10; 24110234Syasuko.eckert@amd.com I_g_on_n[0][100] = 1.65e-10; 24210152Satgutier@umich.edu 24310234Syasuko.eckert@amd.com //SRAM cell properties 24410234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 24510234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 24610234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 24710234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 24810234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 24910234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 25010234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 25110234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 25210234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 25310234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360 25410234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92;//2.5 25510234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 25610234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 1.5;//linear scaling from 90nm 25710234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 * 0.7 * 0.7 * 0.4; 25810234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.11; 25910234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.0;//die measurement results based on Niagara 1 and 2 26010234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.0;//EDA placement and routing tool rule of thumb 26110152Satgutier@umich.edu 26210234Syasuko.eckert@amd.com } 26310152Satgutier@umich.edu 26410234Syasuko.eckert@amd.com if (tech == 90) { 26510234Syasuko.eckert@amd.com SENSE_AMP_D = .28e-9; // s 26610234Syasuko.eckert@amd.com SENSE_AMP_P = 14.7e-15; // J 26710234Syasuko.eckert@amd.com //90nm technology-node. Corresponds to year 2004 in ITRS 26810234Syasuko.eckert@amd.com //ITRS HP device type 26910234Syasuko.eckert@amd.com vdd[0] = 1.2; 27010234Syasuko.eckert@amd.com Lphy[0] = 0.037;//Lphy is the physical gate-length. micron 27110234Syasuko.eckert@amd.com Lelec[0] = 0.0266;//Lelec is the electrical gate-length. micron 27210234Syasuko.eckert@amd.com t_ox[0] = 1.2e-3;//micron 27310234Syasuko.eckert@amd.com v_th[0] = 0.23707;//V 27410234Syasuko.eckert@amd.com c_ox[0] = 1.79e-14;//F/micron2 27510234Syasuko.eckert@amd.com mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 27610234Syasuko.eckert@amd.com Vdsat[0] = 0.128; //V 27710234Syasuko.eckert@amd.com c_g_ideal[0] = 6.64e-16;//F/micron 27810234Syasuko.eckert@amd.com c_fringe[0] = 0.08e-15;//F/micron 27910234Syasuko.eckert@amd.com c_junc[0] = 1e-15;//F/micron2 28010234Syasuko.eckert@amd.com I_on_n[0] = 1076.9e-6;//A/micron 28110234Syasuko.eckert@amd.com I_on_p[0] = 712.6e-6;//A/micron 28210234Syasuko.eckert@amd.com //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline 28310234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.54; 28410234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2.45; 28510234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.22; 28610234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 28710234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 28810234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1; 28910234Syasuko.eckert@amd.com I_off_n[0][0] = 3.24e-8;//A/micron 29010234Syasuko.eckert@amd.com I_off_n[0][10] = 4.01e-8; 29110234Syasuko.eckert@amd.com I_off_n[0][20] = 4.90e-8; 29210234Syasuko.eckert@amd.com I_off_n[0][30] = 5.92e-8; 29310234Syasuko.eckert@amd.com I_off_n[0][40] = 7.08e-8; 29410234Syasuko.eckert@amd.com I_off_n[0][50] = 8.38e-8; 29510234Syasuko.eckert@amd.com I_off_n[0][60] = 9.82e-8; 29610234Syasuko.eckert@amd.com I_off_n[0][70] = 1.14e-7; 29710234Syasuko.eckert@amd.com I_off_n[0][80] = 1.29e-7; 29810234Syasuko.eckert@amd.com I_off_n[0][90] = 1.43e-7; 29910234Syasuko.eckert@amd.com I_off_n[0][100] = 1.54e-7; 30010152Satgutier@umich.edu 30110234Syasuko.eckert@amd.com I_g_on_n[0][0] = 1.65e-8;//A/micron 30210234Syasuko.eckert@amd.com I_g_on_n[0][10] = 1.65e-8; 30310234Syasuko.eckert@amd.com I_g_on_n[0][20] = 1.65e-8; 30410234Syasuko.eckert@amd.com I_g_on_n[0][30] = 1.65e-8; 30510234Syasuko.eckert@amd.com I_g_on_n[0][40] = 1.65e-8; 30610234Syasuko.eckert@amd.com I_g_on_n[0][50] = 1.65e-8; 30710234Syasuko.eckert@amd.com I_g_on_n[0][60] = 1.65e-8; 30810234Syasuko.eckert@amd.com I_g_on_n[0][70] = 1.65e-8; 30910234Syasuko.eckert@amd.com I_g_on_n[0][80] = 1.65e-8; 31010234Syasuko.eckert@amd.com I_g_on_n[0][90] = 1.65e-8; 31110234Syasuko.eckert@amd.com I_g_on_n[0][100] = 1.65e-8; 31210152Satgutier@umich.edu 31310234Syasuko.eckert@amd.com //ITRS LSTP device type 31410234Syasuko.eckert@amd.com vdd[1] = 1.3; 31510234Syasuko.eckert@amd.com Lphy[1] = 0.075; 31610234Syasuko.eckert@amd.com Lelec[1] = 0.0486; 31710234Syasuko.eckert@amd.com t_ox[1] = 2.2e-3; 31810234Syasuko.eckert@amd.com v_th[1] = 0.48203; 31910234Syasuko.eckert@amd.com c_ox[1] = 1.22e-14; 32010234Syasuko.eckert@amd.com mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6); 32110234Syasuko.eckert@amd.com Vdsat[1] = 0.373; 32210234Syasuko.eckert@amd.com c_g_ideal[1] = 9.15e-16; 32310234Syasuko.eckert@amd.com c_fringe[1] = 0.08e-15; 32410234Syasuko.eckert@amd.com c_junc[1] = 1e-15; 32510234Syasuko.eckert@amd.com I_on_n[1] = 503.6e-6; 32610234Syasuko.eckert@amd.com I_on_p[1] = 235.1e-6; 32710234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.92; 32810234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[1] = 2.44; 32910234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[1] = 0.88; 33010234Syasuko.eckert@amd.com Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 33110234Syasuko.eckert@amd.com Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 33210234Syasuko.eckert@amd.com long_channel_leakage_reduction[1] = 1; 33310234Syasuko.eckert@amd.com I_off_n[1][0] = 2.81e-12; 33410234Syasuko.eckert@amd.com I_off_n[1][10] = 4.76e-12; 33510234Syasuko.eckert@amd.com I_off_n[1][20] = 7.82e-12; 33610234Syasuko.eckert@amd.com I_off_n[1][30] = 1.25e-11; 33710234Syasuko.eckert@amd.com I_off_n[1][40] = 1.94e-11; 33810234Syasuko.eckert@amd.com I_off_n[1][50] = 2.94e-11; 33910234Syasuko.eckert@amd.com I_off_n[1][60] = 4.36e-11; 34010234Syasuko.eckert@amd.com I_off_n[1][70] = 6.32e-11; 34110234Syasuko.eckert@amd.com I_off_n[1][80] = 8.95e-11; 34210234Syasuko.eckert@amd.com I_off_n[1][90] = 1.25e-10; 34310234Syasuko.eckert@amd.com I_off_n[1][100] = 1.7e-10; 34410152Satgutier@umich.edu 34510234Syasuko.eckert@amd.com I_g_on_n[1][0] = 3.87e-11;//A/micron 34610234Syasuko.eckert@amd.com I_g_on_n[1][10] = 3.87e-11; 34710234Syasuko.eckert@amd.com I_g_on_n[1][20] = 3.87e-11; 34810234Syasuko.eckert@amd.com I_g_on_n[1][30] = 3.87e-11; 34910234Syasuko.eckert@amd.com I_g_on_n[1][40] = 3.87e-11; 35010234Syasuko.eckert@amd.com I_g_on_n[1][50] = 3.87e-11; 35110234Syasuko.eckert@amd.com I_g_on_n[1][60] = 3.87e-11; 35210234Syasuko.eckert@amd.com I_g_on_n[1][70] = 3.87e-11; 35310234Syasuko.eckert@amd.com I_g_on_n[1][80] = 3.87e-11; 35410234Syasuko.eckert@amd.com I_g_on_n[1][90] = 3.87e-11; 35510234Syasuko.eckert@amd.com I_g_on_n[1][100] = 3.87e-11; 35610152Satgutier@umich.edu 35710234Syasuko.eckert@amd.com //ITRS LOP device type 35810234Syasuko.eckert@amd.com vdd[2] = 0.9; 35910234Syasuko.eckert@amd.com Lphy[2] = 0.053; 36010234Syasuko.eckert@amd.com Lelec[2] = 0.0354; 36110234Syasuko.eckert@amd.com t_ox[2] = 1.5e-3; 36210234Syasuko.eckert@amd.com v_th[2] = 0.30764; 36310234Syasuko.eckert@amd.com c_ox[2] = 1.59e-14; 36410234Syasuko.eckert@amd.com mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6); 36510234Syasuko.eckert@amd.com Vdsat[2] = 0.113; 36610234Syasuko.eckert@amd.com c_g_ideal[2] = 8.45e-16; 36710234Syasuko.eckert@amd.com c_fringe[2] = 0.08e-15; 36810234Syasuko.eckert@amd.com c_junc[2] = 1e-15; 36910234Syasuko.eckert@amd.com I_on_n[2] = 386.6e-6; 37010234Syasuko.eckert@amd.com I_on_p[2] = 209.7e-6; 37110234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.77; 37210234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[2] = 2.54; 37310234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[2] = 0.98; 37410234Syasuko.eckert@amd.com Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 37510234Syasuko.eckert@amd.com Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 37610234Syasuko.eckert@amd.com long_channel_leakage_reduction[2] = 1; 37710234Syasuko.eckert@amd.com I_off_n[2][0] = 2.14e-9; 37810234Syasuko.eckert@amd.com I_off_n[2][10] = 2.9e-9; 37910234Syasuko.eckert@amd.com I_off_n[2][20] = 3.87e-9; 38010234Syasuko.eckert@amd.com I_off_n[2][30] = 5.07e-9; 38110234Syasuko.eckert@amd.com I_off_n[2][40] = 6.54e-9; 38210234Syasuko.eckert@amd.com I_off_n[2][50] = 8.27e-8; 38310234Syasuko.eckert@amd.com I_off_n[2][60] = 1.02e-7; 38410234Syasuko.eckert@amd.com I_off_n[2][70] = 1.20e-7; 38510234Syasuko.eckert@amd.com I_off_n[2][80] = 1.36e-8; 38610234Syasuko.eckert@amd.com I_off_n[2][90] = 1.52e-8; 38710234Syasuko.eckert@amd.com I_off_n[2][100] = 1.73e-8; 38810152Satgutier@umich.edu 38910234Syasuko.eckert@amd.com I_g_on_n[2][0] = 4.31e-8;//A/micron 39010234Syasuko.eckert@amd.com I_g_on_n[2][10] = 4.31e-8; 39110234Syasuko.eckert@amd.com I_g_on_n[2][20] = 4.31e-8; 39210234Syasuko.eckert@amd.com I_g_on_n[2][30] = 4.31e-8; 39310234Syasuko.eckert@amd.com I_g_on_n[2][40] = 4.31e-8; 39410234Syasuko.eckert@amd.com I_g_on_n[2][50] = 4.31e-8; 39510234Syasuko.eckert@amd.com I_g_on_n[2][60] = 4.31e-8; 39610234Syasuko.eckert@amd.com I_g_on_n[2][70] = 4.31e-8; 39710234Syasuko.eckert@amd.com I_g_on_n[2][80] = 4.31e-8; 39810234Syasuko.eckert@amd.com I_g_on_n[2][90] = 4.31e-8; 39910234Syasuko.eckert@amd.com I_g_on_n[2][100] = 4.31e-8; 40010152Satgutier@umich.edu 40110234Syasuko.eckert@amd.com if (ram_cell_tech_type == lp_dram) { 40210234Syasuko.eckert@amd.com //LP-DRAM cell access transistor technology parameters 40310234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.2; 40410234Syasuko.eckert@amd.com Lphy[3] = 0.12; 40510234Syasuko.eckert@amd.com Lelec[3] = 0.0756; 40610234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 0.4545; 40710234Syasuko.eckert@amd.com width_dram_access_transistor = 0.14; 40810234Syasuko.eckert@amd.com curr_I_on_dram_cell = 45e-6; 40910234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12; 41010234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 41110234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 41210234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 41310234Syasuko.eckert@amd.com curr_area_cell_dram = 0.168; 41410234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.46; 41510234Syasuko.eckert@amd.com curr_c_dram_cell = 20e-15; 41610152Satgutier@umich.edu 41710234Syasuko.eckert@amd.com //LP-DRAM wordline transistor parameters 41810234Syasuko.eckert@amd.com curr_vpp = 1.6; 41910234Syasuko.eckert@amd.com t_ox[3] = 2.2e-3; 42010234Syasuko.eckert@amd.com v_th[3] = 0.4545; 42110234Syasuko.eckert@amd.com c_ox[3] = 1.22e-14; 42210234Syasuko.eckert@amd.com mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6); 42310234Syasuko.eckert@amd.com Vdsat[3] = 0.3; 42410234Syasuko.eckert@amd.com c_g_ideal[3] = 1.47e-15; 42510234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 42610234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 42710234Syasuko.eckert@amd.com I_on_n[3] = 321.6e-6; 42810234Syasuko.eckert@amd.com I_on_p[3] = 203.3e-6; 42910234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.65; 43010234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 1.95; 43110234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 43210234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 43310234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 43410234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 43510234Syasuko.eckert@amd.com I_off_n[3][0] = 1.42e-11; 43610234Syasuko.eckert@amd.com I_off_n[3][10] = 2.25e-11; 43710234Syasuko.eckert@amd.com I_off_n[3][20] = 3.46e-11; 43810234Syasuko.eckert@amd.com I_off_n[3][30] = 5.18e-11; 43910234Syasuko.eckert@amd.com I_off_n[3][40] = 7.58e-11; 44010234Syasuko.eckert@amd.com I_off_n[3][50] = 1.08e-10; 44110234Syasuko.eckert@amd.com I_off_n[3][60] = 1.51e-10; 44210234Syasuko.eckert@amd.com I_off_n[3][70] = 2.02e-10; 44310234Syasuko.eckert@amd.com I_off_n[3][80] = 2.57e-10; 44410234Syasuko.eckert@amd.com I_off_n[3][90] = 3.14e-10; 44510234Syasuko.eckert@amd.com I_off_n[3][100] = 3.85e-10; 44610234Syasuko.eckert@amd.com } else if (ram_cell_tech_type == comm_dram) { 44710234Syasuko.eckert@amd.com //COMM-DRAM cell access transistor technology parameters 44810234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.6; 44910234Syasuko.eckert@amd.com Lphy[3] = 0.09; 45010234Syasuko.eckert@amd.com Lelec[3] = 0.0576; 45110234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 1; 45210234Syasuko.eckert@amd.com width_dram_access_transistor = 0.09; 45310234Syasuko.eckert@amd.com curr_I_on_dram_cell = 20e-6; 45410234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 45510234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 45610234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 45710234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 45810234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.09 * 0.09; 45910234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.5; 46010234Syasuko.eckert@amd.com curr_c_dram_cell = 30e-15; 46110152Satgutier@umich.edu 46210234Syasuko.eckert@amd.com //COMM-DRAM wordline transistor parameters 46310234Syasuko.eckert@amd.com curr_vpp = 3.7; 46410234Syasuko.eckert@amd.com t_ox[3] = 5.5e-3; 46510234Syasuko.eckert@amd.com v_th[3] = 1.0; 46610234Syasuko.eckert@amd.com c_ox[3] = 5.65e-15; 46710234Syasuko.eckert@amd.com mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6); 46810234Syasuko.eckert@amd.com Vdsat[3] = 0.32; 46910234Syasuko.eckert@amd.com c_g_ideal[3] = 5.08e-16; 47010234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 47110234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 47210234Syasuko.eckert@amd.com I_on_n[3] = 1094.3e-6; 47310234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 47410234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.62; 47510234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 2.05; 47610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 47710234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 47810234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 47910234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 48010234Syasuko.eckert@amd.com I_off_n[3][0] = 5.80e-15; 48110234Syasuko.eckert@amd.com I_off_n[3][10] = 1.21e-14; 48210234Syasuko.eckert@amd.com I_off_n[3][20] = 2.42e-14; 48310234Syasuko.eckert@amd.com I_off_n[3][30] = 4.65e-14; 48410234Syasuko.eckert@amd.com I_off_n[3][40] = 8.60e-14; 48510234Syasuko.eckert@amd.com I_off_n[3][50] = 1.54e-13; 48610234Syasuko.eckert@amd.com I_off_n[3][60] = 2.66e-13; 48710234Syasuko.eckert@amd.com I_off_n[3][70] = 4.45e-13; 48810234Syasuko.eckert@amd.com I_off_n[3][80] = 7.17e-13; 48910234Syasuko.eckert@amd.com I_off_n[3][90] = 1.11e-12; 49010234Syasuko.eckert@amd.com I_off_n[3][100] = 1.67e-12; 49110234Syasuko.eckert@amd.com } 49210152Satgutier@umich.edu 49310234Syasuko.eckert@amd.com //SRAM cell properties 49410234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 49510234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 49610234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 49710234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 49810234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 49910234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 50010234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 50110234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 50210234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 50310234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360 50410234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92;//2.5 50510234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 50610234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 1; 50710234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 * 0.7 * 0.7; 50810234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1539; 50910234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 51010234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 51110152Satgutier@umich.edu 51210152Satgutier@umich.edu 51310234Syasuko.eckert@amd.com } 51410152Satgutier@umich.edu 51510234Syasuko.eckert@amd.com if (tech == 65) { 51610234Syasuko.eckert@amd.com //65nm technology-node. Corresponds to year 2007 in ITRS 51710234Syasuko.eckert@amd.com //ITRS HP device type 51810234Syasuko.eckert@amd.com SENSE_AMP_D = .2e-9; // s 51910234Syasuko.eckert@amd.com SENSE_AMP_P = 5.7e-15; // J 52010234Syasuko.eckert@amd.com vdd[0] = 1.1; 52110234Syasuko.eckert@amd.com Lphy[0] = 0.025; 52210234Syasuko.eckert@amd.com Lelec[0] = 0.019; 52310234Syasuko.eckert@amd.com t_ox[0] = 1.1e-3; 52410234Syasuko.eckert@amd.com v_th[0] = .19491; 52510234Syasuko.eckert@amd.com c_ox[0] = 1.88e-14; 52610234Syasuko.eckert@amd.com mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6); 52710234Syasuko.eckert@amd.com Vdsat[0] = 7.71e-2; 52810234Syasuko.eckert@amd.com c_g_ideal[0] = 4.69e-16; 52910234Syasuko.eckert@amd.com c_fringe[0] = 0.077e-15; 53010234Syasuko.eckert@amd.com c_junc[0] = 1e-15; 53110234Syasuko.eckert@amd.com I_on_n[0] = 1197.2e-6; 53210234Syasuko.eckert@amd.com I_on_p[0] = 870.8e-6; 53310234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.50; 53410234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2.41; 53510234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.38; 53610234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0]; 53710234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; 53810234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1 / 3.74; 53910234Syasuko.eckert@amd.com //Using MASTAR, @380K, increase Lgate until Ion reduces to 90% or Lgate increase by 10%, whichever comes first 54010234Syasuko.eckert@amd.com //Ioff(Lgate normal)/Ioff(Lgate long)= 3.74. 54110234Syasuko.eckert@amd.com I_off_n[0][0] = 1.96e-7; 54210234Syasuko.eckert@amd.com I_off_n[0][10] = 2.29e-7; 54310234Syasuko.eckert@amd.com I_off_n[0][20] = 2.66e-7; 54410234Syasuko.eckert@amd.com I_off_n[0][30] = 3.05e-7; 54510234Syasuko.eckert@amd.com I_off_n[0][40] = 3.49e-7; 54610234Syasuko.eckert@amd.com I_off_n[0][50] = 3.95e-7; 54710234Syasuko.eckert@amd.com I_off_n[0][60] = 4.45e-7; 54810234Syasuko.eckert@amd.com I_off_n[0][70] = 4.97e-7; 54910234Syasuko.eckert@amd.com I_off_n[0][80] = 5.48e-7; 55010234Syasuko.eckert@amd.com I_off_n[0][90] = 5.94e-7; 55110234Syasuko.eckert@amd.com I_off_n[0][100] = 6.3e-7; 55210234Syasuko.eckert@amd.com I_g_on_n[0][0] = 4.09e-8;//A/micron 55310234Syasuko.eckert@amd.com I_g_on_n[0][10] = 4.09e-8; 55410234Syasuko.eckert@amd.com I_g_on_n[0][20] = 4.09e-8; 55510234Syasuko.eckert@amd.com I_g_on_n[0][30] = 4.09e-8; 55610234Syasuko.eckert@amd.com I_g_on_n[0][40] = 4.09e-8; 55710234Syasuko.eckert@amd.com I_g_on_n[0][50] = 4.09e-8; 55810234Syasuko.eckert@amd.com I_g_on_n[0][60] = 4.09e-8; 55910234Syasuko.eckert@amd.com I_g_on_n[0][70] = 4.09e-8; 56010234Syasuko.eckert@amd.com I_g_on_n[0][80] = 4.09e-8; 56110234Syasuko.eckert@amd.com I_g_on_n[0][90] = 4.09e-8; 56210234Syasuko.eckert@amd.com I_g_on_n[0][100] = 4.09e-8; 56310152Satgutier@umich.edu 56410234Syasuko.eckert@amd.com //ITRS LSTP device type 56510234Syasuko.eckert@amd.com vdd[1] = 1.2; 56610234Syasuko.eckert@amd.com Lphy[1] = 0.045; 56710234Syasuko.eckert@amd.com Lelec[1] = 0.0298; 56810234Syasuko.eckert@amd.com t_ox[1] = 1.9e-3; 56910234Syasuko.eckert@amd.com v_th[1] = 0.52354; 57010234Syasuko.eckert@amd.com c_ox[1] = 1.36e-14; 57110234Syasuko.eckert@amd.com mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6); 57210234Syasuko.eckert@amd.com Vdsat[1] = 0.128; 57310234Syasuko.eckert@amd.com c_g_ideal[1] = 6.14e-16; 57410234Syasuko.eckert@amd.com c_fringe[1] = 0.08e-15; 57510234Syasuko.eckert@amd.com c_junc[1] = 1e-15; 57610234Syasuko.eckert@amd.com I_on_n[1] = 519.2e-6; 57710234Syasuko.eckert@amd.com I_on_p[1] = 266e-6; 57810234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.96; 57910234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[1] = 2.23; 58010234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[1] = 0.99; 58110234Syasuko.eckert@amd.com Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 58210234Syasuko.eckert@amd.com Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 58310234Syasuko.eckert@amd.com long_channel_leakage_reduction[1] = 1 / 2.82; 58410234Syasuko.eckert@amd.com I_off_n[1][0] = 9.12e-12; 58510234Syasuko.eckert@amd.com I_off_n[1][10] = 1.49e-11; 58610234Syasuko.eckert@amd.com I_off_n[1][20] = 2.36e-11; 58710234Syasuko.eckert@amd.com I_off_n[1][30] = 3.64e-11; 58810234Syasuko.eckert@amd.com I_off_n[1][40] = 5.48e-11; 58910234Syasuko.eckert@amd.com I_off_n[1][50] = 8.05e-11; 59010234Syasuko.eckert@amd.com I_off_n[1][60] = 1.15e-10; 59110234Syasuko.eckert@amd.com I_off_n[1][70] = 1.59e-10; 59210234Syasuko.eckert@amd.com I_off_n[1][80] = 2.1e-10; 59310234Syasuko.eckert@amd.com I_off_n[1][90] = 2.62e-10; 59410234Syasuko.eckert@amd.com I_off_n[1][100] = 3.21e-10; 59510152Satgutier@umich.edu 59610234Syasuko.eckert@amd.com I_g_on_n[1][0] = 1.09e-10;//A/micron 59710234Syasuko.eckert@amd.com I_g_on_n[1][10] = 1.09e-10; 59810234Syasuko.eckert@amd.com I_g_on_n[1][20] = 1.09e-10; 59910234Syasuko.eckert@amd.com I_g_on_n[1][30] = 1.09e-10; 60010234Syasuko.eckert@amd.com I_g_on_n[1][40] = 1.09e-10; 60110234Syasuko.eckert@amd.com I_g_on_n[1][50] = 1.09e-10; 60210234Syasuko.eckert@amd.com I_g_on_n[1][60] = 1.09e-10; 60310234Syasuko.eckert@amd.com I_g_on_n[1][70] = 1.09e-10; 60410234Syasuko.eckert@amd.com I_g_on_n[1][80] = 1.09e-10; 60510234Syasuko.eckert@amd.com I_g_on_n[1][90] = 1.09e-10; 60610234Syasuko.eckert@amd.com I_g_on_n[1][100] = 1.09e-10; 60710152Satgutier@umich.edu 60810234Syasuko.eckert@amd.com //ITRS LOP device type 60910234Syasuko.eckert@amd.com vdd[2] = 0.8; 61010234Syasuko.eckert@amd.com Lphy[2] = 0.032; 61110234Syasuko.eckert@amd.com Lelec[2] = 0.0216; 61210234Syasuko.eckert@amd.com t_ox[2] = 1.2e-3; 61310234Syasuko.eckert@amd.com v_th[2] = 0.28512; 61410234Syasuko.eckert@amd.com c_ox[2] = 1.87e-14; 61510234Syasuko.eckert@amd.com mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6); 61610234Syasuko.eckert@amd.com Vdsat[2] = 0.292; 61710234Syasuko.eckert@amd.com c_g_ideal[2] = 6e-16; 61810234Syasuko.eckert@amd.com c_fringe[2] = 0.08e-15; 61910234Syasuko.eckert@amd.com c_junc[2] = 1e-15; 62010234Syasuko.eckert@amd.com I_on_n[2] = 573.1e-6; 62110234Syasuko.eckert@amd.com I_on_p[2] = 340.6e-6; 62210234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.82; 62310234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[2] = 2.28; 62410234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[2] = 1.11; 62510234Syasuko.eckert@amd.com Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 62610234Syasuko.eckert@amd.com Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 62710234Syasuko.eckert@amd.com long_channel_leakage_reduction[2] = 1 / 2.05; 62810234Syasuko.eckert@amd.com I_off_n[2][0] = 4.9e-9; 62910234Syasuko.eckert@amd.com I_off_n[2][10] = 6.49e-9; 63010234Syasuko.eckert@amd.com I_off_n[2][20] = 8.45e-9; 63110234Syasuko.eckert@amd.com I_off_n[2][30] = 1.08e-8; 63210234Syasuko.eckert@amd.com I_off_n[2][40] = 1.37e-8; 63310234Syasuko.eckert@amd.com I_off_n[2][50] = 1.71e-8; 63410234Syasuko.eckert@amd.com I_off_n[2][60] = 2.09e-8; 63510234Syasuko.eckert@amd.com I_off_n[2][70] = 2.48e-8; 63610234Syasuko.eckert@amd.com I_off_n[2][80] = 2.84e-8; 63710234Syasuko.eckert@amd.com I_off_n[2][90] = 3.13e-8; 63810234Syasuko.eckert@amd.com I_off_n[2][100] = 3.42e-8; 63910152Satgutier@umich.edu 64010234Syasuko.eckert@amd.com I_g_on_n[2][0] = 9.61e-9;//A/micron 64110234Syasuko.eckert@amd.com I_g_on_n[2][10] = 9.61e-9; 64210234Syasuko.eckert@amd.com I_g_on_n[2][20] = 9.61e-9; 64310234Syasuko.eckert@amd.com I_g_on_n[2][30] = 9.61e-9; 64410234Syasuko.eckert@amd.com I_g_on_n[2][40] = 9.61e-9; 64510234Syasuko.eckert@amd.com I_g_on_n[2][50] = 9.61e-9; 64610234Syasuko.eckert@amd.com I_g_on_n[2][60] = 9.61e-9; 64710234Syasuko.eckert@amd.com I_g_on_n[2][70] = 9.61e-9; 64810234Syasuko.eckert@amd.com I_g_on_n[2][80] = 9.61e-9; 64910234Syasuko.eckert@amd.com I_g_on_n[2][90] = 9.61e-9; 65010234Syasuko.eckert@amd.com I_g_on_n[2][100] = 9.61e-9; 65110152Satgutier@umich.edu 65210234Syasuko.eckert@amd.com if (ram_cell_tech_type == lp_dram) { 65310234Syasuko.eckert@amd.com //LP-DRAM cell access transistor technology parameters 65410234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.2; 65510234Syasuko.eckert@amd.com Lphy[3] = 0.12; 65610234Syasuko.eckert@amd.com Lelec[3] = 0.0756; 65710234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 0.43806; 65810234Syasuko.eckert@amd.com width_dram_access_transistor = 0.09; 65910234Syasuko.eckert@amd.com curr_I_on_dram_cell = 36e-6; 66010234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12; 66110234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 66210234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 66310234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 66410234Syasuko.eckert@amd.com curr_area_cell_dram = 0.11; 66510234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.46; 66610234Syasuko.eckert@amd.com curr_c_dram_cell = 20e-15; 66710152Satgutier@umich.edu 66810234Syasuko.eckert@amd.com //LP-DRAM wordline transistor parameters 66910234Syasuko.eckert@amd.com curr_vpp = 1.6; 67010234Syasuko.eckert@amd.com t_ox[3] = 2.2e-3; 67110234Syasuko.eckert@amd.com v_th[3] = 0.43806; 67210234Syasuko.eckert@amd.com c_ox[3] = 1.22e-14; 67310234Syasuko.eckert@amd.com mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6); 67410234Syasuko.eckert@amd.com Vdsat[3] = 0.43806; 67510234Syasuko.eckert@amd.com c_g_ideal[3] = 1.46e-15; 67610234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 67710234Syasuko.eckert@amd.com c_junc[3] = 1e-15 ; 67810234Syasuko.eckert@amd.com I_on_n[3] = 399.8e-6; 67910234Syasuko.eckert@amd.com I_on_p[3] = 243.4e-6; 68010234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.65; 68110234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 2.05; 68210234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 68310234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 68410234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 68510234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 68610234Syasuko.eckert@amd.com I_off_n[3][0] = 2.23e-11; 68710234Syasuko.eckert@amd.com I_off_n[3][10] = 3.46e-11; 68810234Syasuko.eckert@amd.com I_off_n[3][20] = 5.24e-11; 68910234Syasuko.eckert@amd.com I_off_n[3][30] = 7.75e-11; 69010234Syasuko.eckert@amd.com I_off_n[3][40] = 1.12e-10; 69110234Syasuko.eckert@amd.com I_off_n[3][50] = 1.58e-10; 69210234Syasuko.eckert@amd.com I_off_n[3][60] = 2.18e-10; 69310234Syasuko.eckert@amd.com I_off_n[3][70] = 2.88e-10; 69410234Syasuko.eckert@amd.com I_off_n[3][80] = 3.63e-10; 69510234Syasuko.eckert@amd.com I_off_n[3][90] = 4.41e-10; 69610234Syasuko.eckert@amd.com I_off_n[3][100] = 5.36e-10; 69710234Syasuko.eckert@amd.com } else if (ram_cell_tech_type == comm_dram) { 69810234Syasuko.eckert@amd.com //COMM-DRAM cell access transistor technology parameters 69910234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.3; 70010234Syasuko.eckert@amd.com Lphy[3] = 0.065; 70110234Syasuko.eckert@amd.com Lelec[3] = 0.0426; 70210234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 1; 70310234Syasuko.eckert@amd.com width_dram_access_transistor = 0.065; 70410234Syasuko.eckert@amd.com curr_I_on_dram_cell = 20e-6; 70510234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 70610234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 70710234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 70810234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 70910234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.065 * 0.065; 71010234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.5; 71110234Syasuko.eckert@amd.com curr_c_dram_cell = 30e-15; 71210152Satgutier@umich.edu 71310234Syasuko.eckert@amd.com //COMM-DRAM wordline transistor parameters 71410234Syasuko.eckert@amd.com curr_vpp = 3.3; 71510234Syasuko.eckert@amd.com t_ox[3] = 5e-3; 71610234Syasuko.eckert@amd.com v_th[3] = 1.0; 71710234Syasuko.eckert@amd.com c_ox[3] = 6.16e-15; 71810234Syasuko.eckert@amd.com mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6); 71910234Syasuko.eckert@amd.com Vdsat[3] = 0.385; 72010234Syasuko.eckert@amd.com c_g_ideal[3] = 4e-16; 72110234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 72210234Syasuko.eckert@amd.com c_junc[3] = 1e-15 ; 72310234Syasuko.eckert@amd.com I_on_n[3] = 1031e-6; 72410234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 72510234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.69; 72610234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 2.39; 72710234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 72810234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 72910234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 73010234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 73110234Syasuko.eckert@amd.com I_off_n[3][0] = 1.80e-14; 73210234Syasuko.eckert@amd.com I_off_n[3][10] = 3.64e-14; 73310234Syasuko.eckert@amd.com I_off_n[3][20] = 7.03e-14; 73410234Syasuko.eckert@amd.com I_off_n[3][30] = 1.31e-13; 73510234Syasuko.eckert@amd.com I_off_n[3][40] = 2.35e-13; 73610234Syasuko.eckert@amd.com I_off_n[3][50] = 4.09e-13; 73710234Syasuko.eckert@amd.com I_off_n[3][60] = 6.89e-13; 73810234Syasuko.eckert@amd.com I_off_n[3][70] = 1.13e-12; 73910234Syasuko.eckert@amd.com I_off_n[3][80] = 1.78e-12; 74010234Syasuko.eckert@amd.com I_off_n[3][90] = 2.71e-12; 74110234Syasuko.eckert@amd.com I_off_n[3][100] = 3.99e-12; 74210234Syasuko.eckert@amd.com } 74310152Satgutier@umich.edu 74410234Syasuko.eckert@amd.com //SRAM cell properties 74510234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 74610234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 74710234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 74810234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 74910234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 75010234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 75110234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 75210234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 75310234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 75410234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 75510234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92; 75610234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 75710234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 0.7; //Rather than scale proportionally to square of feature size, only scale linearly according to IBM cell processor 75810234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 * 0.7; 75910234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1359; 76010234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 76110234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 76210234Syasuko.eckert@amd.com } 76310152Satgutier@umich.edu 76410234Syasuko.eckert@amd.com if (tech == 45) { 76510234Syasuko.eckert@amd.com //45nm technology-node. Corresponds to year 2010 in ITRS 76610234Syasuko.eckert@amd.com //ITRS HP device type 76710234Syasuko.eckert@amd.com SENSE_AMP_D = .04e-9; // s 76810234Syasuko.eckert@amd.com SENSE_AMP_P = 2.7e-15; // J 76910234Syasuko.eckert@amd.com vdd[0] = 1.0; 77010234Syasuko.eckert@amd.com Lphy[0] = 0.018; 77110234Syasuko.eckert@amd.com Lelec[0] = 0.01345; 77210234Syasuko.eckert@amd.com t_ox[0] = 0.65e-3; 77310234Syasuko.eckert@amd.com v_th[0] = .18035; 77410234Syasuko.eckert@amd.com c_ox[0] = 3.77e-14; 77510234Syasuko.eckert@amd.com mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6); 77610234Syasuko.eckert@amd.com Vdsat[0] = 9.38E-2; 77710234Syasuko.eckert@amd.com c_g_ideal[0] = 6.78e-16; 77810234Syasuko.eckert@amd.com c_fringe[0] = 0.05e-15; 77910234Syasuko.eckert@amd.com c_junc[0] = 1e-15; 78010234Syasuko.eckert@amd.com I_on_n[0] = 2046.6e-6; 78110234Syasuko.eckert@amd.com //There are certain problems with the ITRS PMOS numbers in MASTAR for 45nm. So we are using 65nm values of 78210234Syasuko.eckert@amd.com //n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier for 45nm 78310234Syasuko.eckert@amd.com I_on_p[0] = I_on_n[0] / 2;//This value is fixed arbitrarily but I_on_p is not being used in CACTI 78410234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.51; 78510234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2.41; 78610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.38; 78710234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0]; 78810234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; 78910234Syasuko.eckert@amd.com //Using MASTAR, @380K, increase Lgate until Ion reduces to 90%, 79010234Syasuko.eckert@amd.com //Ioff(Lgate normal)/Ioff(Lgate long)= 3.74 79110234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1 / 3.546; 79210234Syasuko.eckert@amd.com I_off_n[0][0] = 2.8e-7; 79310234Syasuko.eckert@amd.com I_off_n[0][10] = 3.28e-7; 79410234Syasuko.eckert@amd.com I_off_n[0][20] = 3.81e-7; 79510234Syasuko.eckert@amd.com I_off_n[0][30] = 4.39e-7; 79610234Syasuko.eckert@amd.com I_off_n[0][40] = 5.02e-7; 79710234Syasuko.eckert@amd.com I_off_n[0][50] = 5.69e-7; 79810234Syasuko.eckert@amd.com I_off_n[0][60] = 6.42e-7; 79910234Syasuko.eckert@amd.com I_off_n[0][70] = 7.2e-7; 80010234Syasuko.eckert@amd.com I_off_n[0][80] = 8.03e-7; 80110234Syasuko.eckert@amd.com I_off_n[0][90] = 8.91e-7; 80210234Syasuko.eckert@amd.com I_off_n[0][100] = 9.84e-7; 80310152Satgutier@umich.edu 80410234Syasuko.eckert@amd.com I_g_on_n[0][0] = 3.59e-8;//A/micron 80510234Syasuko.eckert@amd.com I_g_on_n[0][10] = 3.59e-8; 80610234Syasuko.eckert@amd.com I_g_on_n[0][20] = 3.59e-8; 80710234Syasuko.eckert@amd.com I_g_on_n[0][30] = 3.59e-8; 80810234Syasuko.eckert@amd.com I_g_on_n[0][40] = 3.59e-8; 80910234Syasuko.eckert@amd.com I_g_on_n[0][50] = 3.59e-8; 81010234Syasuko.eckert@amd.com I_g_on_n[0][60] = 3.59e-8; 81110234Syasuko.eckert@amd.com I_g_on_n[0][70] = 3.59e-8; 81210234Syasuko.eckert@amd.com I_g_on_n[0][80] = 3.59e-8; 81310234Syasuko.eckert@amd.com I_g_on_n[0][90] = 3.59e-8; 81410234Syasuko.eckert@amd.com I_g_on_n[0][100] = 3.59e-8; 81510152Satgutier@umich.edu 81610234Syasuko.eckert@amd.com //ITRS LSTP device type 81710234Syasuko.eckert@amd.com vdd[1] = 1.1; 81810234Syasuko.eckert@amd.com Lphy[1] = 0.028; 81910234Syasuko.eckert@amd.com Lelec[1] = 0.0212; 82010234Syasuko.eckert@amd.com t_ox[1] = 1.4e-3; 82110234Syasuko.eckert@amd.com v_th[1] = 0.50245; 82210234Syasuko.eckert@amd.com c_ox[1] = 2.01e-14; 82310234Syasuko.eckert@amd.com mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6); 82410234Syasuko.eckert@amd.com Vdsat[1] = 9.12e-2; 82510234Syasuko.eckert@amd.com c_g_ideal[1] = 5.18e-16; 82610234Syasuko.eckert@amd.com c_fringe[1] = 0.08e-15; 82710234Syasuko.eckert@amd.com c_junc[1] = 1e-15; 82810234Syasuko.eckert@amd.com I_on_n[1] = 666.2e-6; 82910234Syasuko.eckert@amd.com I_on_p[1] = I_on_n[1] / 2; 83010234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.99; 83110234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[1] = 2.23; 83210234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[1] = 0.99; 83310234Syasuko.eckert@amd.com Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 83410234Syasuko.eckert@amd.com Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 83510234Syasuko.eckert@amd.com long_channel_leakage_reduction[1] = 1 / 2.08; 83610234Syasuko.eckert@amd.com I_off_n[1][0] = 1.01e-11; 83710234Syasuko.eckert@amd.com I_off_n[1][10] = 1.65e-11; 83810234Syasuko.eckert@amd.com I_off_n[1][20] = 2.62e-11; 83910234Syasuko.eckert@amd.com I_off_n[1][30] = 4.06e-11; 84010234Syasuko.eckert@amd.com I_off_n[1][40] = 6.12e-11; 84110234Syasuko.eckert@amd.com I_off_n[1][50] = 9.02e-11; 84210234Syasuko.eckert@amd.com I_off_n[1][60] = 1.3e-10; 84310234Syasuko.eckert@amd.com I_off_n[1][70] = 1.83e-10; 84410234Syasuko.eckert@amd.com I_off_n[1][80] = 2.51e-10; 84510234Syasuko.eckert@amd.com I_off_n[1][90] = 3.29e-10; 84610234Syasuko.eckert@amd.com I_off_n[1][100] = 4.1e-10; 84710152Satgutier@umich.edu 84810234Syasuko.eckert@amd.com I_g_on_n[1][0] = 9.47e-12;//A/micron 84910234Syasuko.eckert@amd.com I_g_on_n[1][10] = 9.47e-12; 85010234Syasuko.eckert@amd.com I_g_on_n[1][20] = 9.47e-12; 85110234Syasuko.eckert@amd.com I_g_on_n[1][30] = 9.47e-12; 85210234Syasuko.eckert@amd.com I_g_on_n[1][40] = 9.47e-12; 85310234Syasuko.eckert@amd.com I_g_on_n[1][50] = 9.47e-12; 85410234Syasuko.eckert@amd.com I_g_on_n[1][60] = 9.47e-12; 85510234Syasuko.eckert@amd.com I_g_on_n[1][70] = 9.47e-12; 85610234Syasuko.eckert@amd.com I_g_on_n[1][80] = 9.47e-12; 85710234Syasuko.eckert@amd.com I_g_on_n[1][90] = 9.47e-12; 85810234Syasuko.eckert@amd.com I_g_on_n[1][100] = 9.47e-12; 85910152Satgutier@umich.edu 86010234Syasuko.eckert@amd.com //ITRS LOP device type 86110234Syasuko.eckert@amd.com vdd[2] = 0.7; 86210234Syasuko.eckert@amd.com Lphy[2] = 0.022; 86310234Syasuko.eckert@amd.com Lelec[2] = 0.016; 86410234Syasuko.eckert@amd.com t_ox[2] = 0.9e-3; 86510234Syasuko.eckert@amd.com v_th[2] = 0.22599; 86610234Syasuko.eckert@amd.com c_ox[2] = 2.82e-14;//F/micron2 86710234Syasuko.eckert@amd.com mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6); 86810234Syasuko.eckert@amd.com Vdsat[2] = 5.71e-2; 86910234Syasuko.eckert@amd.com c_g_ideal[2] = 6.2e-16; 87010234Syasuko.eckert@amd.com c_fringe[2] = 0.073e-15; 87110234Syasuko.eckert@amd.com c_junc[2] = 1e-15; 87210234Syasuko.eckert@amd.com I_on_n[2] = 748.9e-6; 87310234Syasuko.eckert@amd.com I_on_p[2] = I_on_n[2] / 2; 87410234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.76; 87510234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[2] = 2.28; 87610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[2] = 1.11; 87710234Syasuko.eckert@amd.com Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 87810234Syasuko.eckert@amd.com Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 87910234Syasuko.eckert@amd.com long_channel_leakage_reduction[2] = 1 / 1.92; 88010234Syasuko.eckert@amd.com I_off_n[2][0] = 4.03e-9; 88110234Syasuko.eckert@amd.com I_off_n[2][10] = 5.02e-9; 88210234Syasuko.eckert@amd.com I_off_n[2][20] = 6.18e-9; 88310234Syasuko.eckert@amd.com I_off_n[2][30] = 7.51e-9; 88410234Syasuko.eckert@amd.com I_off_n[2][40] = 9.04e-9; 88510234Syasuko.eckert@amd.com I_off_n[2][50] = 1.08e-8; 88610234Syasuko.eckert@amd.com I_off_n[2][60] = 1.27e-8; 88710234Syasuko.eckert@amd.com I_off_n[2][70] = 1.47e-8; 88810234Syasuko.eckert@amd.com I_off_n[2][80] = 1.66e-8; 88910234Syasuko.eckert@amd.com I_off_n[2][90] = 1.84e-8; 89010234Syasuko.eckert@amd.com I_off_n[2][100] = 2.03e-8; 89110152Satgutier@umich.edu 89210234Syasuko.eckert@amd.com I_g_on_n[2][0] = 3.24e-8;//A/micron 89310234Syasuko.eckert@amd.com I_g_on_n[2][10] = 4.01e-8; 89410234Syasuko.eckert@amd.com I_g_on_n[2][20] = 4.90e-8; 89510234Syasuko.eckert@amd.com I_g_on_n[2][30] = 5.92e-8; 89610234Syasuko.eckert@amd.com I_g_on_n[2][40] = 7.08e-8; 89710234Syasuko.eckert@amd.com I_g_on_n[2][50] = 8.38e-8; 89810234Syasuko.eckert@amd.com I_g_on_n[2][60] = 9.82e-8; 89910234Syasuko.eckert@amd.com I_g_on_n[2][70] = 1.14e-7; 90010234Syasuko.eckert@amd.com I_g_on_n[2][80] = 1.29e-7; 90110234Syasuko.eckert@amd.com I_g_on_n[2][90] = 1.43e-7; 90210234Syasuko.eckert@amd.com I_g_on_n[2][100] = 1.54e-7; 90310152Satgutier@umich.edu 90410234Syasuko.eckert@amd.com if (ram_cell_tech_type == lp_dram) { 90510234Syasuko.eckert@amd.com //LP-DRAM cell access transistor technology parameters 90610234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.1; 90710234Syasuko.eckert@amd.com Lphy[3] = 0.078; 90810234Syasuko.eckert@amd.com Lelec[3] = 0.0504;// Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 90910234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 0.44559; 91010234Syasuko.eckert@amd.com width_dram_access_transistor = 0.079; 91110234Syasuko.eckert@amd.com curr_I_on_dram_cell = 36e-6;//A 91210234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12; 91310234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 91410234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 91510234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 91610234Syasuko.eckert@amd.com curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; 91710234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.46; 91810234Syasuko.eckert@amd.com curr_c_dram_cell = 20e-15; 91910152Satgutier@umich.edu 92010234Syasuko.eckert@amd.com //LP-DRAM wordline transistor parameters 92110234Syasuko.eckert@amd.com curr_vpp = 1.5; 92210234Syasuko.eckert@amd.com t_ox[3] = 2.1e-3; 92310234Syasuko.eckert@amd.com v_th[3] = 0.44559; 92410234Syasuko.eckert@amd.com c_ox[3] = 1.41e-14; 92510234Syasuko.eckert@amd.com mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6); 92610234Syasuko.eckert@amd.com Vdsat[3] = 0.181; 92710234Syasuko.eckert@amd.com c_g_ideal[3] = 1.10e-15; 92810234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 92910234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 93010234Syasuko.eckert@amd.com I_on_n[3] = 456e-6; 93110234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 93210234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.65; 93310234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 2.05; 93410234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 93510234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 93610234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 93710234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 93810234Syasuko.eckert@amd.com I_off_n[3][0] = 2.54e-11; 93910234Syasuko.eckert@amd.com I_off_n[3][10] = 3.94e-11; 94010234Syasuko.eckert@amd.com I_off_n[3][20] = 5.95e-11; 94110234Syasuko.eckert@amd.com I_off_n[3][30] = 8.79e-11; 94210234Syasuko.eckert@amd.com I_off_n[3][40] = 1.27e-10; 94310234Syasuko.eckert@amd.com I_off_n[3][50] = 1.79e-10; 94410234Syasuko.eckert@amd.com I_off_n[3][60] = 2.47e-10; 94510234Syasuko.eckert@amd.com I_off_n[3][70] = 3.31e-10; 94610234Syasuko.eckert@amd.com I_off_n[3][80] = 4.26e-10; 94710234Syasuko.eckert@amd.com I_off_n[3][90] = 5.27e-10; 94810234Syasuko.eckert@amd.com I_off_n[3][100] = 6.46e-10; 94910234Syasuko.eckert@amd.com } else if (ram_cell_tech_type == comm_dram) { 95010234Syasuko.eckert@amd.com //COMM-DRAM cell access transistor technology parameters 95110234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.1; 95210234Syasuko.eckert@amd.com Lphy[3] = 0.045; 95310234Syasuko.eckert@amd.com Lelec[3] = 0.0298; 95410234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 1; 95510234Syasuko.eckert@amd.com width_dram_access_transistor = 0.045; 95610234Syasuko.eckert@amd.com curr_I_on_dram_cell = 20e-6;//A 95710234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 95810234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 95910234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 96010234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 96110234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.045 * 0.045; 96210234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.5; 96310234Syasuko.eckert@amd.com curr_c_dram_cell = 30e-15; 96410152Satgutier@umich.edu 96510234Syasuko.eckert@amd.com //COMM-DRAM wordline transistor parameters 96610234Syasuko.eckert@amd.com curr_vpp = 2.7; 96710234Syasuko.eckert@amd.com t_ox[3] = 4e-3; 96810234Syasuko.eckert@amd.com v_th[3] = 1.0; 96910234Syasuko.eckert@amd.com c_ox[3] = 7.98e-15; 97010234Syasuko.eckert@amd.com mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6); 97110234Syasuko.eckert@amd.com Vdsat[3] = 0.147; 97210234Syasuko.eckert@amd.com c_g_ideal[3] = 3.59e-16; 97310234Syasuko.eckert@amd.com c_fringe[3] = 0.08e-15; 97410234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 97510234Syasuko.eckert@amd.com I_on_n[3] = 999.4e-6; 97610234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 97710234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.69; 97810234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 1.95; 97910234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 98010234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 98110234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 98210234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 98310234Syasuko.eckert@amd.com I_off_n[3][0] = 1.31e-14; 98410234Syasuko.eckert@amd.com I_off_n[3][10] = 2.68e-14; 98510234Syasuko.eckert@amd.com I_off_n[3][20] = 5.25e-14; 98610234Syasuko.eckert@amd.com I_off_n[3][30] = 9.88e-14; 98710234Syasuko.eckert@amd.com I_off_n[3][40] = 1.79e-13; 98810234Syasuko.eckert@amd.com I_off_n[3][50] = 3.15e-13; 98910234Syasuko.eckert@amd.com I_off_n[3][60] = 5.36e-13; 99010234Syasuko.eckert@amd.com I_off_n[3][70] = 8.86e-13; 99110234Syasuko.eckert@amd.com I_off_n[3][80] = 1.42e-12; 99210234Syasuko.eckert@amd.com I_off_n[3][90] = 2.20e-12; 99310234Syasuko.eckert@amd.com I_off_n[3][100] = 3.29e-12; 99410234Syasuko.eckert@amd.com } 99510152Satgutier@umich.edu 99610152Satgutier@umich.edu 99710234Syasuko.eckert@amd.com //SRAM cell properties 99810234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 99910234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 100010234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 100110234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 100210234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 100310234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 100410234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 100510234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 100610234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 100710234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 100810234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92; 100910234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 101010234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 0.7 * 0.7; 101110234Syasuko.eckert@amd.com curr_core_tx_density = 1.25; 101210234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1387; 101310234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 101410234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 101510234Syasuko.eckert@amd.com } 101610152Satgutier@umich.edu 101710234Syasuko.eckert@amd.com if (tech == 32) { 101810234Syasuko.eckert@amd.com SENSE_AMP_D = .03e-9; // s 101910234Syasuko.eckert@amd.com SENSE_AMP_P = 2.16e-15; // J 102010234Syasuko.eckert@amd.com //For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is 32 nm 102110234Syasuko.eckert@amd.com //technology i.e. FEATURESIZE = 0.032). Using the SOI process numbers for 102210234Syasuko.eckert@amd.com //HP and LSTP. 102310234Syasuko.eckert@amd.com vdd[0] = 0.9; 102410234Syasuko.eckert@amd.com Lphy[0] = 0.013; 102510234Syasuko.eckert@amd.com Lelec[0] = 0.01013; 102610234Syasuko.eckert@amd.com t_ox[0] = 0.5e-3; 102710234Syasuko.eckert@amd.com v_th[0] = 0.21835; 102810234Syasuko.eckert@amd.com c_ox[0] = 4.11e-14; 102910234Syasuko.eckert@amd.com mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6); 103010234Syasuko.eckert@amd.com Vdsat[0] = 5.09E-2; 103110234Syasuko.eckert@amd.com c_g_ideal[0] = 5.34e-16; 103210234Syasuko.eckert@amd.com c_fringe[0] = 0.04e-15; 103310234Syasuko.eckert@amd.com c_junc[0] = 1e-15; 103410234Syasuko.eckert@amd.com I_on_n[0] = 2211.7e-6; 103510234Syasuko.eckert@amd.com I_on_p[0] = I_on_n[0] / 2; 103610234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.49; 103710234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2.41; 103810234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.38; 103910234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 104010234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 104110234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1 / 3.706; 104210234Syasuko.eckert@amd.com //Using MASTAR, @300K (380K does not work in MASTAR), increase Lgate until Ion reduces to 95% or Lgate increase by 5% (DG device can only increase by 5%), 104310234Syasuko.eckert@amd.com //whichever comes first 104410234Syasuko.eckert@amd.com I_off_n[0][0] = 1.52e-7; 104510234Syasuko.eckert@amd.com I_off_n[0][10] = 1.55e-7; 104610234Syasuko.eckert@amd.com I_off_n[0][20] = 1.59e-7; 104710234Syasuko.eckert@amd.com I_off_n[0][30] = 1.68e-7; 104810234Syasuko.eckert@amd.com I_off_n[0][40] = 1.90e-7; 104910234Syasuko.eckert@amd.com I_off_n[0][50] = 2.69e-7; 105010234Syasuko.eckert@amd.com I_off_n[0][60] = 5.32e-7; 105110234Syasuko.eckert@amd.com I_off_n[0][70] = 1.02e-6; 105210234Syasuko.eckert@amd.com I_off_n[0][80] = 1.62e-6; 105310234Syasuko.eckert@amd.com I_off_n[0][90] = 2.73e-6; 105410234Syasuko.eckert@amd.com I_off_n[0][100] = 6.1e-6; 105510152Satgutier@umich.edu 105610234Syasuko.eckert@amd.com I_g_on_n[0][0] = 6.55e-8;//A/micron 105710234Syasuko.eckert@amd.com I_g_on_n[0][10] = 6.55e-8; 105810234Syasuko.eckert@amd.com I_g_on_n[0][20] = 6.55e-8; 105910234Syasuko.eckert@amd.com I_g_on_n[0][30] = 6.55e-8; 106010234Syasuko.eckert@amd.com I_g_on_n[0][40] = 6.55e-8; 106110234Syasuko.eckert@amd.com I_g_on_n[0][50] = 6.55e-8; 106210234Syasuko.eckert@amd.com I_g_on_n[0][60] = 6.55e-8; 106310234Syasuko.eckert@amd.com I_g_on_n[0][70] = 6.55e-8; 106410234Syasuko.eckert@amd.com I_g_on_n[0][80] = 6.55e-8; 106510234Syasuko.eckert@amd.com I_g_on_n[0][90] = 6.55e-8; 106610234Syasuko.eckert@amd.com I_g_on_n[0][100] = 6.55e-8; 106710152Satgutier@umich.edu 106810234Syasuko.eckert@amd.com //LSTP device type 106910234Syasuko.eckert@amd.com vdd[1] = 1; 107010234Syasuko.eckert@amd.com Lphy[1] = 0.020; 107110234Syasuko.eckert@amd.com Lelec[1] = 0.0173; 107210234Syasuko.eckert@amd.com t_ox[1] = 1.2e-3; 107310234Syasuko.eckert@amd.com v_th[1] = 0.513; 107410234Syasuko.eckert@amd.com c_ox[1] = 2.29e-14; 107510234Syasuko.eckert@amd.com mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6); 107610234Syasuko.eckert@amd.com Vdsat[1] = 8.64e-2; 107710234Syasuko.eckert@amd.com c_g_ideal[1] = 4.58e-16; 107810234Syasuko.eckert@amd.com c_fringe[1] = 0.053e-15; 107910234Syasuko.eckert@amd.com c_junc[1] = 1e-15; 108010234Syasuko.eckert@amd.com I_on_n[1] = 683.6e-6; 108110234Syasuko.eckert@amd.com I_on_p[1] = I_on_n[1] / 2; 108210234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.99; 108310234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[1] = 2.23; 108410234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[1] = 0.99; 108510234Syasuko.eckert@amd.com Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 108610234Syasuko.eckert@amd.com Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 108710234Syasuko.eckert@amd.com long_channel_leakage_reduction[1] = 1 / 1.93; 108810234Syasuko.eckert@amd.com I_off_n[1][0] = 2.06e-11; 108910234Syasuko.eckert@amd.com I_off_n[1][10] = 3.30e-11; 109010234Syasuko.eckert@amd.com I_off_n[1][20] = 5.15e-11; 109110234Syasuko.eckert@amd.com I_off_n[1][30] = 7.83e-11; 109210234Syasuko.eckert@amd.com I_off_n[1][40] = 1.16e-10; 109310234Syasuko.eckert@amd.com I_off_n[1][50] = 1.69e-10; 109410234Syasuko.eckert@amd.com I_off_n[1][60] = 2.40e-10; 109510234Syasuko.eckert@amd.com I_off_n[1][70] = 3.34e-10; 109610234Syasuko.eckert@amd.com I_off_n[1][80] = 4.54e-10; 109710234Syasuko.eckert@amd.com I_off_n[1][90] = 5.96e-10; 109810234Syasuko.eckert@amd.com I_off_n[1][100] = 7.44e-10; 109910152Satgutier@umich.edu 110010234Syasuko.eckert@amd.com I_g_on_n[1][0] = 3.73e-11;//A/micron 110110234Syasuko.eckert@amd.com I_g_on_n[1][10] = 3.73e-11; 110210234Syasuko.eckert@amd.com I_g_on_n[1][20] = 3.73e-11; 110310234Syasuko.eckert@amd.com I_g_on_n[1][30] = 3.73e-11; 110410234Syasuko.eckert@amd.com I_g_on_n[1][40] = 3.73e-11; 110510234Syasuko.eckert@amd.com I_g_on_n[1][50] = 3.73e-11; 110610234Syasuko.eckert@amd.com I_g_on_n[1][60] = 3.73e-11; 110710234Syasuko.eckert@amd.com I_g_on_n[1][70] = 3.73e-11; 110810234Syasuko.eckert@amd.com I_g_on_n[1][80] = 3.73e-11; 110910234Syasuko.eckert@amd.com I_g_on_n[1][90] = 3.73e-11; 111010234Syasuko.eckert@amd.com I_g_on_n[1][100] = 3.73e-11; 111110152Satgutier@umich.edu 111210234Syasuko.eckert@amd.com //LOP device type 111310234Syasuko.eckert@amd.com vdd[2] = 0.6; 111410234Syasuko.eckert@amd.com Lphy[2] = 0.016; 111510234Syasuko.eckert@amd.com Lelec[2] = 0.01232; 111610234Syasuko.eckert@amd.com t_ox[2] = 0.9e-3; 111710234Syasuko.eckert@amd.com v_th[2] = 0.24227; 111810234Syasuko.eckert@amd.com c_ox[2] = 2.84e-14; 111910234Syasuko.eckert@amd.com mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6); 112010234Syasuko.eckert@amd.com Vdsat[2] = 4.64e-2; 112110234Syasuko.eckert@amd.com c_g_ideal[2] = 4.54e-16; 112210234Syasuko.eckert@amd.com c_fringe[2] = 0.057e-15; 112310234Syasuko.eckert@amd.com c_junc[2] = 1e-15; 112410234Syasuko.eckert@amd.com I_on_n[2] = 827.8e-6; 112510234Syasuko.eckert@amd.com I_on_p[2] = I_on_n[2] / 2; 112610234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.73; 112710234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[2] = 2.28; 112810234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[2] = 1.11; 112910234Syasuko.eckert@amd.com Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 113010234Syasuko.eckert@amd.com Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 113110234Syasuko.eckert@amd.com long_channel_leakage_reduction[2] = 1 / 1.89; 113210234Syasuko.eckert@amd.com I_off_n[2][0] = 5.94e-8; 113310234Syasuko.eckert@amd.com I_off_n[2][10] = 7.23e-8; 113410234Syasuko.eckert@amd.com I_off_n[2][20] = 8.7e-8; 113510234Syasuko.eckert@amd.com I_off_n[2][30] = 1.04e-7; 113610234Syasuko.eckert@amd.com I_off_n[2][40] = 1.22e-7; 113710234Syasuko.eckert@amd.com I_off_n[2][50] = 1.43e-7; 113810234Syasuko.eckert@amd.com I_off_n[2][60] = 1.65e-7; 113910234Syasuko.eckert@amd.com I_off_n[2][70] = 1.90e-7; 114010234Syasuko.eckert@amd.com I_off_n[2][80] = 2.15e-7; 114110234Syasuko.eckert@amd.com I_off_n[2][90] = 2.39e-7; 114210234Syasuko.eckert@amd.com I_off_n[2][100] = 2.63e-7; 114310152Satgutier@umich.edu 114410234Syasuko.eckert@amd.com I_g_on_n[2][0] = 2.93e-9;//A/micron 114510234Syasuko.eckert@amd.com I_g_on_n[2][10] = 2.93e-9; 114610234Syasuko.eckert@amd.com I_g_on_n[2][20] = 2.93e-9; 114710234Syasuko.eckert@amd.com I_g_on_n[2][30] = 2.93e-9; 114810234Syasuko.eckert@amd.com I_g_on_n[2][40] = 2.93e-9; 114910234Syasuko.eckert@amd.com I_g_on_n[2][50] = 2.93e-9; 115010234Syasuko.eckert@amd.com I_g_on_n[2][60] = 2.93e-9; 115110234Syasuko.eckert@amd.com I_g_on_n[2][70] = 2.93e-9; 115210234Syasuko.eckert@amd.com I_g_on_n[2][80] = 2.93e-9; 115310234Syasuko.eckert@amd.com I_g_on_n[2][90] = 2.93e-9; 115410234Syasuko.eckert@amd.com I_g_on_n[2][100] = 2.93e-9; 115510152Satgutier@umich.edu 115610234Syasuko.eckert@amd.com if (ram_cell_tech_type == lp_dram) { 115710234Syasuko.eckert@amd.com //LP-DRAM cell access transistor technology parameters 115810234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.0; 115910234Syasuko.eckert@amd.com Lphy[3] = 0.056; 116010234Syasuko.eckert@amd.com Lelec[3] = 0.0419;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 116110234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 0.44129; 116210234Syasuko.eckert@amd.com width_dram_access_transistor = 0.056; 116310234Syasuko.eckert@amd.com curr_I_on_dram_cell = 36e-6; 116410234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12; 116510234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 116610234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 116710234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 116810234Syasuko.eckert@amd.com curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; 116910234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.46; 117010234Syasuko.eckert@amd.com curr_c_dram_cell = 20e-15; 117110152Satgutier@umich.edu 117210234Syasuko.eckert@amd.com //LP-DRAM wordline transistor parameters 117310234Syasuko.eckert@amd.com curr_vpp = 1.5; 117410234Syasuko.eckert@amd.com t_ox[3] = 2e-3; 117510234Syasuko.eckert@amd.com v_th[3] = 0.44467; 117610234Syasuko.eckert@amd.com c_ox[3] = 1.48e-14; 117710234Syasuko.eckert@amd.com mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6); 117810234Syasuko.eckert@amd.com Vdsat[3] = 0.174; 117910234Syasuko.eckert@amd.com c_g_ideal[3] = 7.45e-16; 118010234Syasuko.eckert@amd.com c_fringe[3] = 0.053e-15; 118110234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 118210234Syasuko.eckert@amd.com I_on_n[3] = 1055.4e-6; 118310234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 118410234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.65; 118510234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 2.05; 118610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 118710234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 118810234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 118910234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 119010234Syasuko.eckert@amd.com I_off_n[3][0] = 3.57e-11; 119110234Syasuko.eckert@amd.com I_off_n[3][10] = 5.51e-11; 119210234Syasuko.eckert@amd.com I_off_n[3][20] = 8.27e-11; 119310234Syasuko.eckert@amd.com I_off_n[3][30] = 1.21e-10; 119410234Syasuko.eckert@amd.com I_off_n[3][40] = 1.74e-10; 119510234Syasuko.eckert@amd.com I_off_n[3][50] = 2.45e-10; 119610234Syasuko.eckert@amd.com I_off_n[3][60] = 3.38e-10; 119710234Syasuko.eckert@amd.com I_off_n[3][70] = 4.53e-10; 119810234Syasuko.eckert@amd.com I_off_n[3][80] = 5.87e-10; 119910234Syasuko.eckert@amd.com I_off_n[3][90] = 7.29e-10; 120010234Syasuko.eckert@amd.com I_off_n[3][100] = 8.87e-10; 120110234Syasuko.eckert@amd.com } else if (ram_cell_tech_type == comm_dram) { 120210234Syasuko.eckert@amd.com //COMM-DRAM cell access transistor technology parameters 120310234Syasuko.eckert@amd.com curr_vdd_dram_cell = 1.0; 120410234Syasuko.eckert@amd.com Lphy[3] = 0.032; 120510234Syasuko.eckert@amd.com Lelec[3] = 0.0205;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 120610234Syasuko.eckert@amd.com curr_v_th_dram_access_transistor = 1; 120710234Syasuko.eckert@amd.com width_dram_access_transistor = 0.032; 120810234Syasuko.eckert@amd.com curr_I_on_dram_cell = 20e-6; 120910234Syasuko.eckert@amd.com curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 121010234Syasuko.eckert@amd.com curr_Wmemcella_dram = width_dram_access_transistor; 121110234Syasuko.eckert@amd.com curr_Wmemcellpmos_dram = 0; 121210234Syasuko.eckert@amd.com curr_Wmemcellnmos_dram = 0; 121310234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.032 * 0.032; 121410234Syasuko.eckert@amd.com curr_asp_ratio_cell_dram = 1.5; 121510234Syasuko.eckert@amd.com curr_c_dram_cell = 30e-15; 121610152Satgutier@umich.edu 121710234Syasuko.eckert@amd.com //COMM-DRAM wordline transistor parameters 121810234Syasuko.eckert@amd.com curr_vpp = 2.6; 121910234Syasuko.eckert@amd.com t_ox[3] = 4e-3; 122010234Syasuko.eckert@amd.com v_th[3] = 1.0; 122110234Syasuko.eckert@amd.com c_ox[3] = 7.99e-15; 122210234Syasuko.eckert@amd.com mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6); 122310234Syasuko.eckert@amd.com Vdsat[3] = 0.129; 122410234Syasuko.eckert@amd.com c_g_ideal[3] = 2.56e-16; 122510234Syasuko.eckert@amd.com c_fringe[3] = 0.053e-15; 122610234Syasuko.eckert@amd.com c_junc[3] = 1e-15; 122710234Syasuko.eckert@amd.com I_on_n[3] = 1024.5e-6; 122810234Syasuko.eckert@amd.com I_on_p[3] = I_on_n[3] / 2; 122910234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.69; 123010234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[3] = 1.95; 123110234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[3] = 0.90; 123210234Syasuko.eckert@amd.com Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 123310234Syasuko.eckert@amd.com Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 123410234Syasuko.eckert@amd.com long_channel_leakage_reduction[3] = 1; 123510234Syasuko.eckert@amd.com I_off_n[3][0] = 3.63e-14; 123610234Syasuko.eckert@amd.com I_off_n[3][10] = 7.18e-14; 123710234Syasuko.eckert@amd.com I_off_n[3][20] = 1.36e-13; 123810234Syasuko.eckert@amd.com I_off_n[3][30] = 2.49e-13; 123910234Syasuko.eckert@amd.com I_off_n[3][40] = 4.41e-13; 124010234Syasuko.eckert@amd.com I_off_n[3][50] = 7.55e-13; 124110234Syasuko.eckert@amd.com I_off_n[3][60] = 1.26e-12; 124210234Syasuko.eckert@amd.com I_off_n[3][70] = 2.03e-12; 124310234Syasuko.eckert@amd.com I_off_n[3][80] = 3.19e-12; 124410234Syasuko.eckert@amd.com I_off_n[3][90] = 4.87e-12; 124510234Syasuko.eckert@amd.com I_off_n[3][100] = 7.16e-12; 124610234Syasuko.eckert@amd.com } 124710152Satgutier@umich.edu 124810234Syasuko.eckert@amd.com //SRAM cell properties 124910234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 125010234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 125110234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 125210234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 125310234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 125410234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 125510234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 125610234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 125710234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 125810234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 125910234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92; 126010234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 126110234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7; 126210234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 / 0.7; 126310234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1111; 126410234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 126510234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 126610234Syasuko.eckert@amd.com } 126710152Satgutier@umich.edu 126810234Syasuko.eckert@amd.com if (tech == 22) { 126910234Syasuko.eckert@amd.com SENSE_AMP_D = .03e-9; // s 127010234Syasuko.eckert@amd.com SENSE_AMP_P = 2.16e-15; // J 127110234Syasuko.eckert@amd.com //For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is 22 nm 127210234Syasuko.eckert@amd.com //technology i.e. FEATURESIZE = 0.022). Using the DG process numbers for HP. 127310234Syasuko.eckert@amd.com //22 nm HP 127410234Syasuko.eckert@amd.com vdd[0] = 0.8; 127510234Syasuko.eckert@amd.com Lphy[0] = 0.009;//Lphy is the physical gate-length. 127610234Syasuko.eckert@amd.com Lelec[0] = 0.00468;//Lelec is the electrical gate-length. 127710234Syasuko.eckert@amd.com t_ox[0] = 0.55e-3;//micron 127810234Syasuko.eckert@amd.com v_th[0] = 0.1395;//V 127910234Syasuko.eckert@amd.com c_ox[0] = 3.63e-14;//F/micron2 128010234Syasuko.eckert@amd.com mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 128110234Syasuko.eckert@amd.com Vdsat[0] = 2.33e-2; //V/micron 128210234Syasuko.eckert@amd.com c_g_ideal[0] = 3.27e-16;//F/micron 128310234Syasuko.eckert@amd.com c_fringe[0] = 0.06e-15;//F/micron 128410234Syasuko.eckert@amd.com c_junc[0] = 0;//F/micron2 128510234Syasuko.eckert@amd.com I_on_n[0] = 2626.4e-6;//A/micron 128610234Syasuko.eckert@amd.com I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used. 128710234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.45; 128810234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in 128910234Syasuko.eckert@amd.com //"Dynamic" tab of Device workspace. 129010234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value. 129110234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 129210234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 129310234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1 / 3.274; 129410234Syasuko.eckert@amd.com //From 22nm, leakage current are directly from ITRS report rather 129510234Syasuko.eckert@amd.com //than MASTAR, since MASTAR has serious bugs there. 129610234Syasuko.eckert@amd.com I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2; 129710234Syasuko.eckert@amd.com I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2; 129810234Syasuko.eckert@amd.com I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2; 129910234Syasuko.eckert@amd.com I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2; 130010234Syasuko.eckert@amd.com I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2; 130110234Syasuko.eckert@amd.com I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2; 130210234Syasuko.eckert@amd.com I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2; 130310234Syasuko.eckert@amd.com I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2; 130410234Syasuko.eckert@amd.com I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2; 130510234Syasuko.eckert@amd.com I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2; 130610234Syasuko.eckert@amd.com I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2; 130710234Syasuko.eckert@amd.com //for 22nm DG HP 130810234Syasuko.eckert@amd.com I_g_on_n[0][0] = 1.81e-9;//A/micron 130910234Syasuko.eckert@amd.com I_g_on_n[0][10] = 1.81e-9; 131010234Syasuko.eckert@amd.com I_g_on_n[0][20] = 1.81e-9; 131110234Syasuko.eckert@amd.com I_g_on_n[0][30] = 1.81e-9; 131210234Syasuko.eckert@amd.com I_g_on_n[0][40] = 1.81e-9; 131310234Syasuko.eckert@amd.com I_g_on_n[0][50] = 1.81e-9; 131410234Syasuko.eckert@amd.com I_g_on_n[0][60] = 1.81e-9; 131510234Syasuko.eckert@amd.com I_g_on_n[0][70] = 1.81e-9; 131610234Syasuko.eckert@amd.com I_g_on_n[0][80] = 1.81e-9; 131710234Syasuko.eckert@amd.com I_g_on_n[0][90] = 1.81e-9; 131810234Syasuko.eckert@amd.com I_g_on_n[0][100] = 1.81e-9; 131910152Satgutier@umich.edu 132010234Syasuko.eckert@amd.com //22 nm LSTP DG 132110234Syasuko.eckert@amd.com vdd[1] = 0.8; 132210234Syasuko.eckert@amd.com Lphy[1] = 0.014; 132310234Syasuko.eckert@amd.com Lelec[1] = 0.008;//Lelec is the electrical gate-length. 132410234Syasuko.eckert@amd.com t_ox[1] = 1.1e-3;//micron 132510234Syasuko.eckert@amd.com v_th[1] = 0.40126;//V 132610234Syasuko.eckert@amd.com c_ox[1] = 2.30e-14;//F/micron2 132710234Syasuko.eckert@amd.com mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 132810234Syasuko.eckert@amd.com Vdsat[1] = 6.64e-2; //V/micron 132910234Syasuko.eckert@amd.com c_g_ideal[1] = 3.22e-16;//F/micron 133010234Syasuko.eckert@amd.com c_fringe[1] = 0.08e-15; 133110234Syasuko.eckert@amd.com c_junc[1] = 0;//F/micron2 133210234Syasuko.eckert@amd.com I_on_n[1] = 727.6e-6;//A/micron 133310234Syasuko.eckert@amd.com I_on_p[1] = I_on_n[1] / 2; 133410234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.99; 133510234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[1] = 2; 133610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[1] = 0.99; 133710234Syasuko.eckert@amd.com Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];//ohm-micron 133810234Syasuko.eckert@amd.com Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron 133910234Syasuko.eckert@amd.com long_channel_leakage_reduction[1] = 1 / 1.89; 134010234Syasuko.eckert@amd.com I_off_n[1][0] = 2.43e-11; 134110234Syasuko.eckert@amd.com I_off_n[1][10] = 4.85e-11; 134210234Syasuko.eckert@amd.com I_off_n[1][20] = 9.68e-11; 134310234Syasuko.eckert@amd.com I_off_n[1][30] = 1.94e-10; 134410234Syasuko.eckert@amd.com I_off_n[1][40] = 3.87e-10; 134510234Syasuko.eckert@amd.com I_off_n[1][50] = 7.73e-10; 134610234Syasuko.eckert@amd.com I_off_n[1][60] = 3.55e-10; 134710234Syasuko.eckert@amd.com I_off_n[1][70] = 3.09e-9; 134810234Syasuko.eckert@amd.com I_off_n[1][80] = 6.19e-9; 134910234Syasuko.eckert@amd.com I_off_n[1][90] = 1.24e-8; 135010234Syasuko.eckert@amd.com I_off_n[1][100] = 2.48e-8; 135110152Satgutier@umich.edu 135210234Syasuko.eckert@amd.com I_g_on_n[1][0] = 4.51e-10;//A/micron 135310234Syasuko.eckert@amd.com I_g_on_n[1][10] = 4.51e-10; 135410234Syasuko.eckert@amd.com I_g_on_n[1][20] = 4.51e-10; 135510234Syasuko.eckert@amd.com I_g_on_n[1][30] = 4.51e-10; 135610234Syasuko.eckert@amd.com I_g_on_n[1][40] = 4.51e-10; 135710234Syasuko.eckert@amd.com I_g_on_n[1][50] = 4.51e-10; 135810234Syasuko.eckert@amd.com I_g_on_n[1][60] = 4.51e-10; 135910234Syasuko.eckert@amd.com I_g_on_n[1][70] = 4.51e-10; 136010234Syasuko.eckert@amd.com I_g_on_n[1][80] = 4.51e-10; 136110234Syasuko.eckert@amd.com I_g_on_n[1][90] = 4.51e-10; 136210234Syasuko.eckert@amd.com I_g_on_n[1][100] = 4.51e-10; 136310152Satgutier@umich.edu 136410234Syasuko.eckert@amd.com //22 nm LOP 136510234Syasuko.eckert@amd.com vdd[2] = 0.6; 136610234Syasuko.eckert@amd.com Lphy[2] = 0.011; 136710234Syasuko.eckert@amd.com Lelec[2] = 0.00604;//Lelec is the electrical gate-length. 136810234Syasuko.eckert@amd.com t_ox[2] = 0.8e-3;//micron 136910234Syasuko.eckert@amd.com v_th[2] = 0.2315;//V 137010234Syasuko.eckert@amd.com c_ox[2] = 2.87e-14;//F/micron2 137110234Syasuko.eckert@amd.com mobility_eff[2] = 698.37 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 137210234Syasuko.eckert@amd.com Vdsat[2] = 1.81e-2; //V/micron 137310234Syasuko.eckert@amd.com c_g_ideal[2] = 3.16e-16;//F/micron 137410234Syasuko.eckert@amd.com c_fringe[2] = 0.08e-15; 137510234Syasuko.eckert@amd.com c_junc[2] = 0;//F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab 137610234Syasuko.eckert@amd.com I_on_n[2] = 916.1e-6;//A/micron 137710234Syasuko.eckert@amd.com I_on_p[2] = I_on_n[2] / 2; 137810234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.73; 137910234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[2] = 2; 138010234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[2] = 1.11; 138110234Syasuko.eckert@amd.com Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];//ohm-micron 138210234Syasuko.eckert@amd.com Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];//ohm-micron 138310234Syasuko.eckert@amd.com long_channel_leakage_reduction[2] = 1 / 2.38; 138410152Satgutier@umich.edu 138510234Syasuko.eckert@amd.com I_off_n[2][0] = 1.31e-8; 138610234Syasuko.eckert@amd.com I_off_n[2][10] = 2.60e-8; 138710234Syasuko.eckert@amd.com I_off_n[2][20] = 5.14e-8; 138810234Syasuko.eckert@amd.com I_off_n[2][30] = 1.02e-7; 138910234Syasuko.eckert@amd.com I_off_n[2][40] = 2.02e-7; 139010234Syasuko.eckert@amd.com I_off_n[2][50] = 3.99e-7; 139110234Syasuko.eckert@amd.com I_off_n[2][60] = 7.91e-7; 139210234Syasuko.eckert@amd.com I_off_n[2][70] = 1.09e-6; 139310234Syasuko.eckert@amd.com I_off_n[2][80] = 2.09e-6; 139410234Syasuko.eckert@amd.com I_off_n[2][90] = 4.04e-6; 139510234Syasuko.eckert@amd.com I_off_n[2][100] = 4.48e-6; 139610152Satgutier@umich.edu 139710234Syasuko.eckert@amd.com I_g_on_n[2][0] = 2.74e-9;//A/micron 139810234Syasuko.eckert@amd.com I_g_on_n[2][10] = 2.74e-9; 139910234Syasuko.eckert@amd.com I_g_on_n[2][20] = 2.74e-9; 140010234Syasuko.eckert@amd.com I_g_on_n[2][30] = 2.74e-9; 140110234Syasuko.eckert@amd.com I_g_on_n[2][40] = 2.74e-9; 140210234Syasuko.eckert@amd.com I_g_on_n[2][50] = 2.74e-9; 140310234Syasuko.eckert@amd.com I_g_on_n[2][60] = 2.74e-9; 140410234Syasuko.eckert@amd.com I_g_on_n[2][70] = 2.74e-9; 140510234Syasuko.eckert@amd.com I_g_on_n[2][80] = 2.74e-9; 140610234Syasuko.eckert@amd.com I_g_on_n[2][90] = 2.74e-9; 140710234Syasuko.eckert@amd.com I_g_on_n[2][100] = 2.74e-9; 140810152Satgutier@umich.edu 140910152Satgutier@umich.edu 141010152Satgutier@umich.edu 141110234Syasuko.eckert@amd.com if (ram_cell_tech_type == 3) {} else if (ram_cell_tech_type == 4) { 141210234Syasuko.eckert@amd.com //22 nm commodity DRAM cell access transistor technology parameters. 141310152Satgutier@umich.edu //parameters 141410152Satgutier@umich.edu curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In 141510152Satgutier@umich.edu //2005 ITRS, the value was about twice the value in 2007 ITRS 141610152Satgutier@umich.edu Lphy[3] = 0.022;//micron 141710152Satgutier@umich.edu Lelec[3] = 0.0181;//micron. 141810152Satgutier@umich.edu curr_v_th_dram_access_transistor = 1;//V 141910152Satgutier@umich.edu width_dram_access_transistor = 0.022;//micron 142010152Satgutier@umich.edu curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always 142110152Satgutier@umich.edu //kept constant. In reality this could perhaps be lower 142210152Satgutier@umich.edu curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A 142310152Satgutier@umich.edu curr_Wmemcella_dram = width_dram_access_transistor; 142410152Satgutier@umich.edu curr_Wmemcellpmos_dram = 0; 142510152Satgutier@umich.edu curr_Wmemcellnmos_dram = 0; 142610234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.022 * 0.022;//micron2. 142710152Satgutier@umich.edu curr_asp_ratio_cell_dram = 0.667; 142810152Satgutier@umich.edu curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus 142910152Satgutier@umich.edu //kept constant. 143010152Satgutier@umich.edu 143110234Syasuko.eckert@amd.com //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR. 143210152Satgutier@umich.edu curr_vpp = 2.3;//vpp. V 143310152Satgutier@umich.edu t_ox[3] = 3.5e-3;//micron 143410152Satgutier@umich.edu v_th[3] = 1.0;//V 143510152Satgutier@umich.edu c_ox[3] = 9.06e-15;//F/micron2 143610152Satgutier@umich.edu mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs 143710152Satgutier@umich.edu Vdsat[3] = 0.0972; //V/micron 143810152Satgutier@umich.edu c_g_ideal[3] = 1.99e-16;//F/micron 143910152Satgutier@umich.edu c_fringe[3] = 0.053e-15;//F/micron 144010152Satgutier@umich.edu c_junc[3] = 1e-15;//F/micron2 144110152Satgutier@umich.edu I_on_n[3] = 910.5e-6;//A/micron 144210152Satgutier@umich.edu I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used. 144310152Satgutier@umich.edu nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm. 144410152Satgutier@umich.edu // 144510152Satgutier@umich.edu n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm 144610152Satgutier@umich.edu gmp_to_gmn_multiplier[3] = 0.90; 144710152Satgutier@umich.edu Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron 144810152Satgutier@umich.edu Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron 144910152Satgutier@umich.edu long_channel_leakage_reduction[3] = 1; 145010152Satgutier@umich.edu I_off_n[3][0] = 1.1e-13; //A/micron 145110152Satgutier@umich.edu I_off_n[3][10] = 2.11e-13; 145210152Satgutier@umich.edu I_off_n[3][20] = 3.88e-13; 145310152Satgutier@umich.edu I_off_n[3][30] = 6.9e-13; 145410152Satgutier@umich.edu I_off_n[3][40] = 1.19e-12; 145510152Satgutier@umich.edu I_off_n[3][50] = 1.98e-12; 145610152Satgutier@umich.edu I_off_n[3][60] = 3.22e-12; 145710152Satgutier@umich.edu I_off_n[3][70] = 5.09e-12; 145810152Satgutier@umich.edu I_off_n[3][80] = 7.85e-12; 145910152Satgutier@umich.edu I_off_n[3][90] = 1.18e-11; 146010152Satgutier@umich.edu I_off_n[3][100] = 1.72e-11; 146110152Satgutier@umich.edu 146210234Syasuko.eckert@amd.com } else { 146310234Syasuko.eckert@amd.com //some error handler 146410234Syasuko.eckert@amd.com } 146510234Syasuko.eckert@amd.com 146610234Syasuko.eckert@amd.com //SRAM cell properties 146710234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 146810234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 146910234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 147010234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 147110234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 147210234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 147310234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 147410234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 147510234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 147610234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 147710234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92; 147810234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 147910234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7; 148010234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 / 0.7 / 0.7; 148110234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1296; 148210234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 148310234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 148410152Satgutier@umich.edu } 148510152Satgutier@umich.edu 148610234Syasuko.eckert@amd.com if (tech == 16) { 148710234Syasuko.eckert@amd.com //For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is 16 nm 148810234Syasuko.eckert@amd.com //technology i.e. FEATURESIZE = 0.016). Using the DG process numbers for HP. 148910234Syasuko.eckert@amd.com //16 nm HP 149010234Syasuko.eckert@amd.com vdd[0] = 0.7; 149110234Syasuko.eckert@amd.com Lphy[0] = 0.006;//Lphy is the physical gate-length. 149210234Syasuko.eckert@amd.com Lelec[0] = 0.00315;//Lelec is the electrical gate-length. 149310234Syasuko.eckert@amd.com t_ox[0] = 0.5e-3;//micron 149410234Syasuko.eckert@amd.com v_th[0] = 0.1489;//V 149510234Syasuko.eckert@amd.com c_ox[0] = 3.83e-14;//F/micron2 Cox_elec in MASTAR 149610234Syasuko.eckert@amd.com mobility_eff[0] = 476.15 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 149710234Syasuko.eckert@amd.com Vdsat[0] = 1.42e-2; //V/micron calculated in spreadsheet 149810234Syasuko.eckert@amd.com c_g_ideal[0] = 2.30e-16;//F/micron 149910234Syasuko.eckert@amd.com c_fringe[0] = 0.06e-15;//F/micron MASTAR inputdynamic/3 150010234Syasuko.eckert@amd.com c_junc[0] = 0;//F/micron2 MASTAR result dynamic 150110234Syasuko.eckert@amd.com I_on_n[0] = 2768.4e-6;//A/micron 150210234Syasuko.eckert@amd.com I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used. 150310234Syasuko.eckert@amd.com nmos_effective_resistance_multiplier = 1.48;//nmos_effective_resistance_multiplier is the ratio of Ieff to Idsat where Ieff is the effective NMOS current and Idsat is the saturation current. 150410234Syasuko.eckert@amd.com n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in 150510234Syasuko.eckert@amd.com //"Dynamic" tab of Device workspace. 150610234Syasuko.eckert@amd.com gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value. 150710234Syasuko.eckert@amd.com Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 150810234Syasuko.eckert@amd.com Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 150910234Syasuko.eckert@amd.com long_channel_leakage_reduction[0] = 1 / 2.655; 151010234Syasuko.eckert@amd.com I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * 1.07; 151110234Syasuko.eckert@amd.com I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * 1.07; 151210234Syasuko.eckert@amd.com I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * 1.07; 151310234Syasuko.eckert@amd.com I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * 1.07; 151410234Syasuko.eckert@amd.com I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * 1.07; 151510234Syasuko.eckert@amd.com I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * 1.07; 151610234Syasuko.eckert@amd.com I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * 1.07; 151710234Syasuko.eckert@amd.com I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * 1.07; 151810234Syasuko.eckert@amd.com I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * 1.07; 151910234Syasuko.eckert@amd.com I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * 1.07; 152010234Syasuko.eckert@amd.com I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * 1.07; 152110234Syasuko.eckert@amd.com //for 16nm DG HP 152210234Syasuko.eckert@amd.com I_g_on_n[0][0] = 1.07e-9;//A/micron 152310234Syasuko.eckert@amd.com I_g_on_n[0][10] = 1.07e-9; 152410234Syasuko.eckert@amd.com I_g_on_n[0][20] = 1.07e-9; 152510234Syasuko.eckert@amd.com I_g_on_n[0][30] = 1.07e-9; 152610234Syasuko.eckert@amd.com I_g_on_n[0][40] = 1.07e-9; 152710234Syasuko.eckert@amd.com I_g_on_n[0][50] = 1.07e-9; 152810234Syasuko.eckert@amd.com I_g_on_n[0][60] = 1.07e-9; 152910234Syasuko.eckert@amd.com I_g_on_n[0][70] = 1.07e-9; 153010234Syasuko.eckert@amd.com I_g_on_n[0][80] = 1.07e-9; 153110234Syasuko.eckert@amd.com I_g_on_n[0][90] = 1.07e-9; 153210234Syasuko.eckert@amd.com I_g_on_n[0][100] = 1.07e-9; 153310152Satgutier@umich.edu 153410234Syasuko.eckert@amd.com if (ram_cell_tech_type == 3) {} else if (ram_cell_tech_type == 4) { 153510234Syasuko.eckert@amd.com //22 nm commodity DRAM cell access transistor technology parameters. 153610152Satgutier@umich.edu //parameters 153710152Satgutier@umich.edu curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In 153810152Satgutier@umich.edu //2005 ITRS, the value was about twice the value in 2007 ITRS 153910152Satgutier@umich.edu Lphy[3] = 0.022;//micron 154010152Satgutier@umich.edu Lelec[3] = 0.0181;//micron. 154110152Satgutier@umich.edu curr_v_th_dram_access_transistor = 1;//V 154210152Satgutier@umich.edu width_dram_access_transistor = 0.022;//micron 154310152Satgutier@umich.edu curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always 154410152Satgutier@umich.edu //kept constant. In reality this could perhaps be lower 154510152Satgutier@umich.edu curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A 154610152Satgutier@umich.edu curr_Wmemcella_dram = width_dram_access_transistor; 154710152Satgutier@umich.edu curr_Wmemcellpmos_dram = 0; 154810152Satgutier@umich.edu curr_Wmemcellnmos_dram = 0; 154910234Syasuko.eckert@amd.com curr_area_cell_dram = 6 * 0.022 * 0.022;//micron2. 155010152Satgutier@umich.edu curr_asp_ratio_cell_dram = 0.667; 155110152Satgutier@umich.edu curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus 155210152Satgutier@umich.edu //kept constant. 155310152Satgutier@umich.edu 155410234Syasuko.eckert@amd.com //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR. 155510152Satgutier@umich.edu curr_vpp = 2.3;//vpp. V 155610152Satgutier@umich.edu t_ox[3] = 3.5e-3;//micron 155710152Satgutier@umich.edu v_th[3] = 1.0;//V 155810152Satgutier@umich.edu c_ox[3] = 9.06e-15;//F/micron2 155910152Satgutier@umich.edu mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs 156010152Satgutier@umich.edu Vdsat[3] = 0.0972; //V/micron 156110152Satgutier@umich.edu c_g_ideal[3] = 1.99e-16;//F/micron 156210152Satgutier@umich.edu c_fringe[3] = 0.053e-15;//F/micron 156310152Satgutier@umich.edu c_junc[3] = 1e-15;//F/micron2 156410152Satgutier@umich.edu I_on_n[3] = 910.5e-6;//A/micron 156510152Satgutier@umich.edu I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used. 156610152Satgutier@umich.edu nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm. 156710152Satgutier@umich.edu // 156810152Satgutier@umich.edu n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm 156910152Satgutier@umich.edu gmp_to_gmn_multiplier[3] = 0.90; 157010152Satgutier@umich.edu Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron 157110152Satgutier@umich.edu Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron 157210152Satgutier@umich.edu long_channel_leakage_reduction[3] = 1; 157310152Satgutier@umich.edu I_off_n[3][0] = 1.1e-13; //A/micron 157410152Satgutier@umich.edu I_off_n[3][10] = 2.11e-13; 157510152Satgutier@umich.edu I_off_n[3][20] = 3.88e-13; 157610152Satgutier@umich.edu I_off_n[3][30] = 6.9e-13; 157710152Satgutier@umich.edu I_off_n[3][40] = 1.19e-12; 157810152Satgutier@umich.edu I_off_n[3][50] = 1.98e-12; 157910152Satgutier@umich.edu I_off_n[3][60] = 3.22e-12; 158010152Satgutier@umich.edu I_off_n[3][70] = 5.09e-12; 158110152Satgutier@umich.edu I_off_n[3][80] = 7.85e-12; 158210152Satgutier@umich.edu I_off_n[3][90] = 1.18e-11; 158310152Satgutier@umich.edu I_off_n[3][100] = 1.72e-11; 158410152Satgutier@umich.edu 158510234Syasuko.eckert@amd.com } else { 158610234Syasuko.eckert@amd.com //some error handler 158710234Syasuko.eckert@amd.com } 158810234Syasuko.eckert@amd.com 158910234Syasuko.eckert@amd.com //SRAM cell properties 159010234Syasuko.eckert@amd.com curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 159110234Syasuko.eckert@amd.com curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 159210234Syasuko.eckert@amd.com curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 159310234Syasuko.eckert@amd.com curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 159410234Syasuko.eckert@amd.com curr_asp_ratio_cell_sram = 1.46; 159510234Syasuko.eckert@amd.com //CAM cell properties //TODO: data need to be revisited 159610234Syasuko.eckert@amd.com curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 159710234Syasuko.eckert@amd.com curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 159810234Syasuko.eckert@amd.com curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 159910234Syasuko.eckert@amd.com curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 160010234Syasuko.eckert@amd.com curr_asp_ratio_cell_cam = 2.92; 160110234Syasuko.eckert@amd.com //Empirical undifferetiated core/FU coefficient 160210234Syasuko.eckert@amd.com curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7 * 0.7; 160310234Syasuko.eckert@amd.com curr_core_tx_density = 1.25 / 0.7 / 0.7 / 0.7; 160410234Syasuko.eckert@amd.com curr_sckt_co_eff = 1.1296; 160510234Syasuko.eckert@amd.com curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 160610234Syasuko.eckert@amd.com curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 160710152Satgutier@umich.edu } 160810152Satgutier@umich.edu 160910234Syasuko.eckert@amd.com 161010234Syasuko.eckert@amd.com g_tp.peri_global.Vdd += curr_alpha * vdd[peri_global_tech_type]; 161110234Syasuko.eckert@amd.com g_tp.peri_global.t_ox += curr_alpha * t_ox[peri_global_tech_type]; 161210234Syasuko.eckert@amd.com g_tp.peri_global.Vth += curr_alpha * v_th[peri_global_tech_type]; 161310234Syasuko.eckert@amd.com g_tp.peri_global.C_ox += curr_alpha * c_ox[peri_global_tech_type]; 161410234Syasuko.eckert@amd.com g_tp.peri_global.C_g_ideal += curr_alpha * c_g_ideal[peri_global_tech_type]; 161510234Syasuko.eckert@amd.com g_tp.peri_global.C_fringe += curr_alpha * c_fringe[peri_global_tech_type]; 161610234Syasuko.eckert@amd.com g_tp.peri_global.C_junc += curr_alpha * c_junc[peri_global_tech_type]; 161710234Syasuko.eckert@amd.com g_tp.peri_global.C_junc_sidewall = 0.25e-15; // F/micron 161810234Syasuko.eckert@amd.com g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type]; 161910234Syasuko.eckert@amd.com g_tp.peri_global.l_elec += curr_alpha * Lelec[peri_global_tech_type]; 162010234Syasuko.eckert@amd.com g_tp.peri_global.I_on_n += curr_alpha * I_on_n[peri_global_tech_type]; 162110234Syasuko.eckert@amd.com g_tp.peri_global.R_nch_on += curr_alpha * Rnchannelon[peri_global_tech_type]; 162210234Syasuko.eckert@amd.com g_tp.peri_global.R_pch_on += curr_alpha * Rpchannelon[peri_global_tech_type]; 162310234Syasuko.eckert@amd.com g_tp.peri_global.n_to_p_eff_curr_drv_ratio 162410234Syasuko.eckert@amd.com += curr_alpha * n_to_p_eff_curr_drv_ratio[peri_global_tech_type]; 162510234Syasuko.eckert@amd.com g_tp.peri_global.long_channel_leakage_reduction 162610234Syasuko.eckert@amd.com += curr_alpha * long_channel_leakage_reduction[peri_global_tech_type]; 162710234Syasuko.eckert@amd.com g_tp.peri_global.I_off_n += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300]; 162810234Syasuko.eckert@amd.com g_tp.peri_global.I_off_p += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300]; 162910234Syasuko.eckert@amd.com g_tp.peri_global.I_g_on_n += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; 163010234Syasuko.eckert@amd.com g_tp.peri_global.I_g_on_p += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; 163110234Syasuko.eckert@amd.com gmp_to_gmn_multiplier_periph_global += curr_alpha * gmp_to_gmn_multiplier[peri_global_tech_type]; 163210234Syasuko.eckert@amd.com 163310234Syasuko.eckert@amd.com g_tp.sram_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type]; 163410234Syasuko.eckert@amd.com g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; 163510234Syasuko.eckert@amd.com g_tp.sram_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; 163610234Syasuko.eckert@amd.com g_tp.sram_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; 163710234Syasuko.eckert@amd.com g_tp.sram_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; 163810234Syasuko.eckert@amd.com g_tp.sram_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; 163910234Syasuko.eckert@amd.com g_tp.sram_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; 164010234Syasuko.eckert@amd.com g_tp.sram_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; 164110234Syasuko.eckert@amd.com g_tp.sram_cell.C_junc_sidewall = 0.25e-15; // F/micron 164210234Syasuko.eckert@amd.com g_tp.sram_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; 164310234Syasuko.eckert@amd.com g_tp.sram_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; 164410234Syasuko.eckert@amd.com g_tp.sram_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; 164510234Syasuko.eckert@amd.com g_tp.sram_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; 164610234Syasuko.eckert@amd.com g_tp.sram_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; 164710234Syasuko.eckert@amd.com g_tp.sram_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 164810234Syasuko.eckert@amd.com g_tp.sram_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 164910234Syasuko.eckert@amd.com g_tp.sram_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 165010234Syasuko.eckert@amd.com g_tp.sram_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 165110234Syasuko.eckert@amd.com 165210234Syasuko.eckert@amd.com g_tp.dram_cell_Vdd += curr_alpha * curr_vdd_dram_cell; 165310234Syasuko.eckert@amd.com g_tp.dram_acc.Vth += curr_alpha * curr_v_th_dram_access_transistor; 165410234Syasuko.eckert@amd.com g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; 165510234Syasuko.eckert@amd.com g_tp.dram_acc.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; 165610234Syasuko.eckert@amd.com g_tp.dram_acc.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; 165710234Syasuko.eckert@amd.com g_tp.dram_acc.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; 165810234Syasuko.eckert@amd.com g_tp.dram_acc.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; 165910234Syasuko.eckert@amd.com g_tp.dram_acc.C_junc_sidewall = 0.25e-15; // F/micron 166010234Syasuko.eckert@amd.com g_tp.dram_cell_I_on += curr_alpha * curr_I_on_dram_cell; 166110234Syasuko.eckert@amd.com g_tp.dram_cell_I_off_worst_case_len_temp += curr_alpha * curr_I_off_dram_cell_worst_case_length_temp; 166210234Syasuko.eckert@amd.com g_tp.dram_acc.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; 166310234Syasuko.eckert@amd.com g_tp.dram_cell_C += curr_alpha * curr_c_dram_cell; 166410234Syasuko.eckert@amd.com g_tp.vpp += curr_alpha * curr_vpp; 166510234Syasuko.eckert@amd.com g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; 166610234Syasuko.eckert@amd.com g_tp.dram_wl.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; 166710234Syasuko.eckert@amd.com g_tp.dram_wl.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; 166810234Syasuko.eckert@amd.com g_tp.dram_wl.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; 166910234Syasuko.eckert@amd.com g_tp.dram_wl.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; 167010234Syasuko.eckert@amd.com g_tp.dram_wl.C_junc_sidewall = 0.25e-15; // F/micron 167110234Syasuko.eckert@amd.com g_tp.dram_wl.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; 167210234Syasuko.eckert@amd.com g_tp.dram_wl.R_nch_on += curr_alpha * Rnchannelon[dram_cell_tech_flavor]; 167310234Syasuko.eckert@amd.com g_tp.dram_wl.R_pch_on += curr_alpha * Rpchannelon[dram_cell_tech_flavor]; 167410234Syasuko.eckert@amd.com g_tp.dram_wl.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[dram_cell_tech_flavor]; 167510234Syasuko.eckert@amd.com g_tp.dram_wl.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[dram_cell_tech_flavor]; 167610234Syasuko.eckert@amd.com g_tp.dram_wl.I_off_n += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; 167710234Syasuko.eckert@amd.com g_tp.dram_wl.I_off_p += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; 167810234Syasuko.eckert@amd.com 167910234Syasuko.eckert@amd.com g_tp.cam_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type]; 168010234Syasuko.eckert@amd.com g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; 168110234Syasuko.eckert@amd.com g_tp.cam_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; 168210234Syasuko.eckert@amd.com g_tp.cam_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; 168310234Syasuko.eckert@amd.com g_tp.cam_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; 168410234Syasuko.eckert@amd.com g_tp.cam_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; 168510234Syasuko.eckert@amd.com g_tp.cam_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; 168610234Syasuko.eckert@amd.com g_tp.cam_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; 168710234Syasuko.eckert@amd.com g_tp.cam_cell.C_junc_sidewall = 0.25e-15; // F/micron 168810234Syasuko.eckert@amd.com g_tp.cam_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; 168910234Syasuko.eckert@amd.com g_tp.cam_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; 169010234Syasuko.eckert@amd.com g_tp.cam_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; 169110234Syasuko.eckert@amd.com g_tp.cam_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; 169210234Syasuko.eckert@amd.com g_tp.cam_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; 169310234Syasuko.eckert@amd.com g_tp.cam_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 169410234Syasuko.eckert@amd.com g_tp.cam_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 169510234Syasuko.eckert@amd.com g_tp.cam_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 169610234Syasuko.eckert@amd.com g_tp.cam_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 169710234Syasuko.eckert@amd.com 169810234Syasuko.eckert@amd.com g_tp.dram.cell_a_w += curr_alpha * curr_Wmemcella_dram; 169910234Syasuko.eckert@amd.com g_tp.dram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_dram; 170010234Syasuko.eckert@amd.com g_tp.dram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_dram; 170110234Syasuko.eckert@amd.com area_cell_dram += curr_alpha * curr_area_cell_dram; 170210234Syasuko.eckert@amd.com asp_ratio_cell_dram += curr_alpha * curr_asp_ratio_cell_dram; 170310234Syasuko.eckert@amd.com 170410234Syasuko.eckert@amd.com g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram; 170510234Syasuko.eckert@amd.com g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram; 170610234Syasuko.eckert@amd.com g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram; 170710234Syasuko.eckert@amd.com area_cell_sram += curr_alpha * curr_area_cell_sram; 170810234Syasuko.eckert@amd.com asp_ratio_cell_sram += curr_alpha * curr_asp_ratio_cell_sram; 170910234Syasuko.eckert@amd.com 171010234Syasuko.eckert@amd.com g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam;//sheng 171110234Syasuko.eckert@amd.com g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam; 171210234Syasuko.eckert@amd.com g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam; 171310234Syasuko.eckert@amd.com area_cell_cam += curr_alpha * curr_area_cell_cam; 171410234Syasuko.eckert@amd.com asp_ratio_cell_cam += curr_alpha * curr_asp_ratio_cell_cam; 171510234Syasuko.eckert@amd.com 171610234Syasuko.eckert@amd.com //Sense amplifier latch Gm calculation 171710234Syasuko.eckert@amd.com mobility_eff_periph_global += curr_alpha * mobility_eff[peri_global_tech_type]; 171810234Syasuko.eckert@amd.com Vdsat_periph_global += curr_alpha * Vdsat[peri_global_tech_type]; 171910234Syasuko.eckert@amd.com 172010152Satgutier@umich.edu //Empirical undifferetiated core/FU coefficient 172110234Syasuko.eckert@amd.com g_tp.scaling_factor.logic_scaling_co_eff += curr_alpha * curr_logic_scaling_co_eff; 172210234Syasuko.eckert@amd.com g_tp.scaling_factor.core_tx_density += curr_alpha * curr_core_tx_density; 172310234Syasuko.eckert@amd.com g_tp.chip_layout_overhead += curr_alpha * curr_chip_layout_overhead; 172410234Syasuko.eckert@amd.com g_tp.macro_layout_overhead += curr_alpha * curr_macro_layout_overhead; 172510234Syasuko.eckert@amd.com g_tp.sckt_co_eff += curr_alpha * curr_sckt_co_eff; 172610234Syasuko.eckert@amd.com } 172710234Syasuko.eckert@amd.com 172810234Syasuko.eckert@amd.com 172910234Syasuko.eckert@amd.com //Currently we are not modeling the resistance/capacitance of poly anywhere. 173010234Syasuko.eckert@amd.com //Continuous function (or date have been processed) does not need linear interpolation 173110234Syasuko.eckert@amd.com g_tp.w_comp_inv_p1 = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process 173210234Syasuko.eckert@amd.com g_tp.w_comp_inv_n1 = 7.5 * g_ip->F_sz_um;//this was 6 micron for the 0.8 micron process 173310234Syasuko.eckert@amd.com g_tp.w_comp_inv_p2 = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process 173410234Syasuko.eckert@amd.com g_tp.w_comp_inv_n2 = 15 * g_ip->F_sz_um;//this was 12 micron for the 0.8 micron process 173510234Syasuko.eckert@amd.com g_tp.w_comp_inv_p3 = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process 173610234Syasuko.eckert@amd.com g_tp.w_comp_inv_n3 = 30 * g_ip->F_sz_um;//this was 24 micron for the 0.8 micron process 173710234Syasuko.eckert@amd.com g_tp.w_eval_inv_p = 100 * g_ip->F_sz_um;//this was 80 micron for the 0.8 micron process 173810234Syasuko.eckert@amd.com g_tp.w_eval_inv_n = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process 173910234Syasuko.eckert@amd.com g_tp.w_comp_n = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process 174010234Syasuko.eckert@amd.com g_tp.w_comp_p = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process 174110234Syasuko.eckert@amd.com 174210234Syasuko.eckert@amd.com g_tp.MIN_GAP_BET_P_AND_N_DIFFS = 5 * g_ip->F_sz_um; 174310234Syasuko.eckert@amd.com g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS = 1.5 * g_ip->F_sz_um; 174410234Syasuko.eckert@amd.com g_tp.HPOWERRAIL = 2 * g_ip->F_sz_um; 174510234Syasuko.eckert@amd.com g_tp.cell_h_def = 50 * g_ip->F_sz_um; 174610234Syasuko.eckert@amd.com g_tp.w_poly_contact = g_ip->F_sz_um; 174710234Syasuko.eckert@amd.com g_tp.spacing_poly_to_contact = g_ip->F_sz_um; 174810234Syasuko.eckert@amd.com g_tp.spacing_poly_to_poly = 1.5 * g_ip->F_sz_um; 174910234Syasuko.eckert@amd.com g_tp.ram_wl_stitching_overhead_ = 7.5 * g_ip->F_sz_um; 175010234Syasuko.eckert@amd.com 175110234Syasuko.eckert@amd.com g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2; 175210234Syasuko.eckert@amd.com g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um; 175310234Syasuko.eckert@amd.com //was 10 micron for the 0.8 micron process 175410234Syasuko.eckert@amd.com g_tp.w_iso = 12.5 * g_ip->F_sz_um; 175510234Syasuko.eckert@amd.com // sense amplifier N-trans; was 3 micron for the 0.8 micron process 175610234Syasuko.eckert@amd.com g_tp.w_sense_n = 3.75 * g_ip->F_sz_um; 175710234Syasuko.eckert@amd.com // sense amplifier P-trans; was 6 micron for the 0.8 micron process 175810234Syasuko.eckert@amd.com g_tp.w_sense_p = 7.5 * g_ip->F_sz_um; 175910234Syasuko.eckert@amd.com // Sense enable transistor of the sense amplifier; was 4 micron for the 176010234Syasuko.eckert@amd.com //0.8 micron process 176110234Syasuko.eckert@amd.com g_tp.w_sense_en = 5 * g_ip->F_sz_um; 176210234Syasuko.eckert@amd.com g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_; 176310234Syasuko.eckert@amd.com g_tp.w_nmos_sa_mux= 6 * g_tp.min_w_nmos_; 176410234Syasuko.eckert@amd.com 176510234Syasuko.eckert@amd.com if (ram_cell_tech_type == comm_dram) { 176610234Syasuko.eckert@amd.com g_tp.max_w_nmos_dec = 8 * g_ip->F_sz_um; 176710234Syasuko.eckert@amd.com g_tp.h_dec = 8; // in the unit of memory cell height 176810234Syasuko.eckert@amd.com } else { 176910234Syasuko.eckert@amd.com g_tp.max_w_nmos_dec = g_tp.max_w_nmos_; 177010234Syasuko.eckert@amd.com g_tp.h_dec = 4; // in the unit of memory cell height 177110234Syasuko.eckert@amd.com } 177210234Syasuko.eckert@amd.com 177310234Syasuko.eckert@amd.com g_tp.peri_global.C_overlap = 0.2 * g_tp.peri_global.C_g_ideal; 177410234Syasuko.eckert@amd.com g_tp.sram_cell.C_overlap = 0.2 * g_tp.sram_cell.C_g_ideal; 177510234Syasuko.eckert@amd.com g_tp.cam_cell.C_overlap = 0.2 * g_tp.cam_cell.C_g_ideal; 177610234Syasuko.eckert@amd.com 177710234Syasuko.eckert@amd.com g_tp.dram_acc.C_overlap = 0.2 * g_tp.dram_acc.C_g_ideal; 177810234Syasuko.eckert@amd.com g_tp.dram_acc.R_nch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_n; 177910234Syasuko.eckert@amd.com //g_tp.dram_acc.R_pch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_p; 178010234Syasuko.eckert@amd.com 178110234Syasuko.eckert@amd.com g_tp.dram_wl.C_overlap = 0.2 * g_tp.dram_wl.C_g_ideal; 178210234Syasuko.eckert@amd.com 178310234Syasuko.eckert@amd.com double gmn_sense_amp_latch = (mobility_eff_periph_global / 2) * g_tp.peri_global.C_ox * (g_tp.w_sense_n / g_tp.peri_global.l_elec) * Vdsat_periph_global; 178410234Syasuko.eckert@amd.com double gmp_sense_amp_latch = gmp_to_gmn_multiplier_periph_global * gmn_sense_amp_latch; 178510234Syasuko.eckert@amd.com g_tp.gm_sense_amp_latch = gmn_sense_amp_latch + gmp_sense_amp_latch; 178610234Syasuko.eckert@amd.com 178710234Syasuko.eckert@amd.com g_tp.dram.b_w = sqrt(area_cell_dram / (asp_ratio_cell_dram)); 178810234Syasuko.eckert@amd.com g_tp.dram.b_h = asp_ratio_cell_dram * g_tp.dram.b_w; 178910234Syasuko.eckert@amd.com g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram)); 179010234Syasuko.eckert@amd.com g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w; 179110234Syasuko.eckert@amd.com g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam));//Sheng 179210234Syasuko.eckert@amd.com g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w; 179310234Syasuko.eckert@amd.com 179410234Syasuko.eckert@amd.com g_tp.dram.Vbitpre = g_tp.dram_cell_Vdd; 179510234Syasuko.eckert@amd.com g_tp.sram.Vbitpre = vdd[ram_cell_tech_type]; 179610234Syasuko.eckert@amd.com g_tp.cam.Vbitpre = vdd[ram_cell_tech_type];//Sheng 179710234Syasuko.eckert@amd.com pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); 179810234Syasuko.eckert@amd.com g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; 179910234Syasuko.eckert@amd.com g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; 180010234Syasuko.eckert@amd.com 180110234Syasuko.eckert@amd.com 180210234Syasuko.eckert@amd.com double wire_pitch [NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180310234Syasuko.eckert@amd.com wire_r_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180410234Syasuko.eckert@amd.com wire_c_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180510234Syasuko.eckert@amd.com horiz_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180610234Syasuko.eckert@amd.com vert_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180710234Syasuko.eckert@amd.com aspect_ratio[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180810234Syasuko.eckert@amd.com miller_value[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 180910234Syasuko.eckert@amd.com ild_thickness[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES]; 181010234Syasuko.eckert@amd.com 181110234Syasuko.eckert@amd.com for (iter = 0; iter <= 1; ++iter) { 181210234Syasuko.eckert@amd.com // linear interpolation 181310234Syasuko.eckert@amd.com if (iter == 0) { 181410234Syasuko.eckert@amd.com tech = tech_lo; 181510234Syasuko.eckert@amd.com if (tech_lo == tech_hi) { 181610234Syasuko.eckert@amd.com curr_alpha = 1; 181710234Syasuko.eckert@amd.com } else { 181810234Syasuko.eckert@amd.com curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); 181910234Syasuko.eckert@amd.com } 182010234Syasuko.eckert@amd.com } else { 182110234Syasuko.eckert@amd.com tech = tech_hi; 182210234Syasuko.eckert@amd.com if (tech_lo == tech_hi) { 182310234Syasuko.eckert@amd.com break; 182410234Syasuko.eckert@amd.com } else { 182510234Syasuko.eckert@amd.com curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); 182610234Syasuko.eckert@amd.com } 182710152Satgutier@umich.edu } 182810152Satgutier@umich.edu 182910234Syasuko.eckert@amd.com if (tech == 180) { 183010234Syasuko.eckert@amd.com //Aggressive projections 183110234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron 183210234Syasuko.eckert@amd.com aspect_ratio[0][0] = 2.0; 183310234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; //micron 183410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width;//micron 183510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width;//micron 183610234Syasuko.eckert@amd.com barrier_thickness = 0.017;//micron 183710234Syasuko.eckert@amd.com dishing_thickness = 0;//micron 183810234Syasuko.eckert@amd.com alpha_scatter = 1; 183910234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width, 184010234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron 184110234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.75;//micron 184210234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 184310234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 2.709; 184410234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 184510234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; //F/micron 184610234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 184710234Syasuko.eckert@amd.com ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], 184810234Syasuko.eckert@amd.com vert_dielectric_constant[0][0], 184910234Syasuko.eckert@amd.com fringe_cap);//F/micron. 185010152Satgutier@umich.edu 185110234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um; 185210234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 185310234Syasuko.eckert@amd.com aspect_ratio[0][1] = 2.4; 185410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 185510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 185610234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width, 185710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 185810234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.75;//micron 185910234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 186010234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 2.709; 186110234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 186210234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; //F/micron 186310234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 186410234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 186510234Syasuko.eckert@amd.com vert_dielectric_constant[0][1], 186610234Syasuko.eckert@amd.com fringe_cap); 186710152Satgutier@umich.edu 186810234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um; 186910234Syasuko.eckert@amd.com aspect_ratio[0][2] = 2.2; 187010234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 187110234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 187210234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 187310234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width, 187410234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 187510234Syasuko.eckert@amd.com ild_thickness[0][2] = 1.5; 187610234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 187710234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 2.709; 187810234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 187910234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 188010234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 188110234Syasuko.eckert@amd.com fringe_cap); 188210152Satgutier@umich.edu 188310234Syasuko.eckert@amd.com //Conservative projections 188410234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 188510234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 188610234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 188710234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 188810234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 188910234Syasuko.eckert@amd.com barrier_thickness = 0.017; 189010234Syasuko.eckert@amd.com dishing_thickness = 0; 189110234Syasuko.eckert@amd.com alpha_scatter = 1; 189210234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 189310234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 189410234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.75; 189510234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 189610234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 3.038; 189710234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 189810234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 189910234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 190010234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], 190110234Syasuko.eckert@amd.com vert_dielectric_constant[1][0], 190210234Syasuko.eckert@amd.com fringe_cap); 190310152Satgutier@umich.edu 190410234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 190510234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 190610234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 190710234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 190810234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 190910234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 191010234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 191110234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.75; 191210234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 191310234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 3.038; 191410234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 191510234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 191610234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], 191710234Syasuko.eckert@amd.com vert_dielectric_constant[1][1], 191810234Syasuko.eckert@amd.com fringe_cap); 191910152Satgutier@umich.edu 192010152Satgutier@umich.edu wire_pitch[1][2] = 8 * g_ip->F_sz_um; 192110152Satgutier@umich.edu aspect_ratio[1][2] = 2.2; 192210152Satgutier@umich.edu wire_width = wire_pitch[1][2] / 2; 192310152Satgutier@umich.edu wire_thickness = aspect_ratio[1][2] * wire_width; 192410152Satgutier@umich.edu wire_spacing = wire_pitch[1][2] - wire_width; 192510152Satgutier@umich.edu dishing_thickness = 0.1 * wire_thickness; 192610152Satgutier@umich.edu wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 192710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 192810234Syasuko.eckert@amd.com ild_thickness[1][2] = 1.98; 192910234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 193010234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 3.038; 193110234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 193210152Satgutier@umich.edu wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 193310234Syasuko.eckert@amd.com ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 193410234Syasuko.eckert@amd.com fringe_cap); 193510152Satgutier@umich.edu //Nominal projections for commodity DRAM wordline/bitline 193610234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.18; 193710234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.18); 193810234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.18; 193910234Syasuko.eckert@amd.com } else if (tech == 90) { 194010234Syasuko.eckert@amd.com //Aggressive projections 194110234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron 194210234Syasuko.eckert@amd.com aspect_ratio[0][0] = 2.4; 194310234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; //micron 194410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width;//micron 194510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width;//micron 194610234Syasuko.eckert@amd.com barrier_thickness = 0.01;//micron 194710234Syasuko.eckert@amd.com dishing_thickness = 0;//micron 194810234Syasuko.eckert@amd.com alpha_scatter = 1; 194910234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width, 195010234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron 195110234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.48;//micron 195210234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 195310234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 2.709; 195410234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 195510234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; //F/micron 195610234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 195710234Syasuko.eckert@amd.com ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], 195810234Syasuko.eckert@amd.com vert_dielectric_constant[0][0], 195910234Syasuko.eckert@amd.com fringe_cap);//F/micron. 196010152Satgutier@umich.edu 196110234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um; 196210234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 196310234Syasuko.eckert@amd.com aspect_ratio[0][1] = 2.4; 196410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 196510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 196610234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width, 196710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 196810234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.48;//micron 196910234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 197010234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 2.709; 197110234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 197210234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 197310234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 197410234Syasuko.eckert@amd.com vert_dielectric_constant[0][1], 197510234Syasuko.eckert@amd.com fringe_cap); 197610152Satgutier@umich.edu 197710234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um; 197810234Syasuko.eckert@amd.com aspect_ratio[0][2] = 2.7; 197910234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 198010234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 198110234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 198210234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width, 198310234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 198410234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.96; 198510234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 198610234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 2.709; 198710234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 198810234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 198910234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 199010234Syasuko.eckert@amd.com fringe_cap); 199110152Satgutier@umich.edu 199210234Syasuko.eckert@amd.com //Conservative projections 199310234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 199410234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 199510234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 199610234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 199710234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 199810234Syasuko.eckert@amd.com barrier_thickness = 0.008; 199910234Syasuko.eckert@amd.com dishing_thickness = 0; 200010234Syasuko.eckert@amd.com alpha_scatter = 1; 200110234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 200210234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 200310234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.48; 200410234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 200510234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 3.038; 200610234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 200710234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 200810234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 200910234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], 201010234Syasuko.eckert@amd.com vert_dielectric_constant[1][0], 201110234Syasuko.eckert@amd.com fringe_cap); 201210152Satgutier@umich.edu 201310234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 201410234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 201510234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 201610234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 201710234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 201810234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 201910234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 202010234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.48; 202110234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 202210234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 3.038; 202310234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 202410234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 202510234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], 202610234Syasuko.eckert@amd.com vert_dielectric_constant[1][1], 202710234Syasuko.eckert@amd.com fringe_cap); 202810152Satgutier@umich.edu 202910234Syasuko.eckert@amd.com wire_pitch[1][2] = 8 * g_ip->F_sz_um; 203010234Syasuko.eckert@amd.com aspect_ratio[1][2] = 2.2; 203110234Syasuko.eckert@amd.com wire_width = wire_pitch[1][2] / 2; 203210234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][2] * wire_width; 203310234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][2] - wire_width; 203410234Syasuko.eckert@amd.com dishing_thickness = 0.1 * wire_thickness; 203510234Syasuko.eckert@amd.com wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 203610234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 203710234Syasuko.eckert@amd.com ild_thickness[1][2] = 1.1; 203810234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 203910234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 3.038; 204010234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 204110234Syasuko.eckert@amd.com wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 204210234Syasuko.eckert@amd.com ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 204310234Syasuko.eckert@amd.com fringe_cap); 204410234Syasuko.eckert@amd.com //Nominal projections for commodity DRAM wordline/bitline 204510234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.09; 204610234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.09); 204710234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.09; 204810234Syasuko.eckert@amd.com } else if (tech == 65) { 204910234Syasuko.eckert@amd.com //Aggressive projections 205010234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 205110234Syasuko.eckert@amd.com aspect_ratio[0][0] = 2.7; 205210234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; 205310234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width; 205410234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width; 205510234Syasuko.eckert@amd.com barrier_thickness = 0; 205610234Syasuko.eckert@amd.com dishing_thickness = 0; 205710234Syasuko.eckert@amd.com alpha_scatter = 1; 205810234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 205910234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 206010234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.405; 206110234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 206210234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 2.303; 206310234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 206410234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 206510234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 206610234Syasuko.eckert@amd.com ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] , 206710234Syasuko.eckert@amd.com fringe_cap); 206810152Satgutier@umich.edu 206910234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um; 207010234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 207110234Syasuko.eckert@amd.com aspect_ratio[0][1] = 2.7; 207210234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 207310234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 207410234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 207510234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 207610234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.405; 207710234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 207810234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 2.303; 207910234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 208010234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 208110234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 208210234Syasuko.eckert@amd.com vert_dielectric_constant[0][1], 208310234Syasuko.eckert@amd.com fringe_cap); 208410152Satgutier@umich.edu 208510234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um; 208610234Syasuko.eckert@amd.com aspect_ratio[0][2] = 2.8; 208710234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 208810234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 208910234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 209010234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 209110234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 209210234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.81; 209310234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 209410234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 2.303; 209510234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 209610234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 209710234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 209810234Syasuko.eckert@amd.com fringe_cap); 209910234Syasuko.eckert@amd.com 210010234Syasuko.eckert@amd.com //Conservative projections 210110234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 210210234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 210310234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 210410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 210510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 210610234Syasuko.eckert@amd.com barrier_thickness = 0.006; 210710234Syasuko.eckert@amd.com dishing_thickness = 0; 210810234Syasuko.eckert@amd.com alpha_scatter = 1; 210910234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 211010234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 211110234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.405; 211210234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 211310234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 2.734; 211410234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 211510234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 211610234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 211710234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 211810234Syasuko.eckert@amd.com fringe_cap); 211910234Syasuko.eckert@amd.com 212010234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 212110234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 212210234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 212310234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 212410234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 212510234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 212610234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 212710234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.405; 212810234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 212910234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 2.734; 213010234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 213110152Satgutier@umich.edu wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 213210234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 213310234Syasuko.eckert@amd.com fringe_cap); 213410152Satgutier@umich.edu 213510152Satgutier@umich.edu wire_pitch[1][2] = 8 * g_ip->F_sz_um; 213610152Satgutier@umich.edu aspect_ratio[1][2] = 2.2; 213710152Satgutier@umich.edu wire_width = wire_pitch[1][2] / 2; 213810152Satgutier@umich.edu wire_thickness = aspect_ratio[1][2] * wire_width; 213910152Satgutier@umich.edu wire_spacing = wire_pitch[1][2] - wire_width; 214010152Satgutier@umich.edu dishing_thickness = 0.1 * wire_thickness; 214110152Satgutier@umich.edu wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 214210234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 214310234Syasuko.eckert@amd.com ild_thickness[1][2] = 0.77; 214410234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 214510234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 2.734; 214610234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 214710234Syasuko.eckert@amd.com wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 214810234Syasuko.eckert@amd.com ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 214910234Syasuko.eckert@amd.com fringe_cap); 215010234Syasuko.eckert@amd.com //Nominal projections for commodity DRAM wordline/bitline 215110234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.065; 215210234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 52.5e-15 / (256 * 2 * 0.065); 215310234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.065; 215410234Syasuko.eckert@amd.com } else if (tech == 45) { 215510234Syasuko.eckert@amd.com //Aggressive projections. 215610234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 215710234Syasuko.eckert@amd.com aspect_ratio[0][0] = 3.0; 215810234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; 215910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width; 216010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width; 216110234Syasuko.eckert@amd.com barrier_thickness = 0; 216210234Syasuko.eckert@amd.com dishing_thickness = 0; 216310234Syasuko.eckert@amd.com alpha_scatter = 1; 216410234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 216510234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 216610234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.315; 216710234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 216810234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 1.958; 216910234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 217010234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 217110234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 217210234Syasuko.eckert@amd.com ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] , 217310234Syasuko.eckert@amd.com fringe_cap); 217410234Syasuko.eckert@amd.com 217510234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um; 217610234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 217710234Syasuko.eckert@amd.com aspect_ratio[0][1] = 3.0; 217810234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 217910234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 218010234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 218110234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 218210234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.315; 218310234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 218410234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 1.958; 218510234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 218610234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 218710234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 218810234Syasuko.eckert@amd.com fringe_cap); 218910234Syasuko.eckert@amd.com 219010234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um; 219110234Syasuko.eckert@amd.com aspect_ratio[0][2] = 3.0; 219210234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 219310234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 219410234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 219510234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 219610234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 219710234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.63; 219810234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 219910234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 1.958; 220010234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 220110234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 220210234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 220310234Syasuko.eckert@amd.com fringe_cap); 220410234Syasuko.eckert@amd.com 220510234Syasuko.eckert@amd.com //Conservative projections 220610234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 220710234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 220810234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 220910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 221010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 221110234Syasuko.eckert@amd.com barrier_thickness = 0.004; 221210234Syasuko.eckert@amd.com dishing_thickness = 0; 221310234Syasuko.eckert@amd.com alpha_scatter = 1; 221410234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 221510234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 221610234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.315; 221710234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 221810234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 2.46; 221910234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 222010234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 222110234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 222210234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 222310234Syasuko.eckert@amd.com fringe_cap); 222410234Syasuko.eckert@amd.com 222510234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 222610234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 222710234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 222810234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 222910234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 223010234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 223110234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 223210234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.315; 223310234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 223410234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 2.46; 223510234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 223610234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 223710234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 223810234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 223910234Syasuko.eckert@amd.com fringe_cap); 224010234Syasuko.eckert@amd.com 224110234Syasuko.eckert@amd.com wire_pitch[1][2] = 8 * g_ip->F_sz_um; 224210234Syasuko.eckert@amd.com aspect_ratio[1][2] = 2.2; 224310234Syasuko.eckert@amd.com wire_width = wire_pitch[1][2] / 2; 224410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][2] * wire_width; 224510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][2] - wire_width; 224610234Syasuko.eckert@amd.com dishing_thickness = 0.1 * wire_thickness; 224710234Syasuko.eckert@amd.com wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 224810234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 224910234Syasuko.eckert@amd.com ild_thickness[1][2] = 0.55; 225010234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 225110234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 2.46; 225210234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 225310234Syasuko.eckert@amd.com wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 225410234Syasuko.eckert@amd.com ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 225510234Syasuko.eckert@amd.com fringe_cap); 225610234Syasuko.eckert@amd.com //Nominal projections for commodity DRAM wordline/bitline 225710234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.045; 225810234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 37.5e-15 / (256 * 2 * 0.045); 225910234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.045; 226010234Syasuko.eckert@amd.com } else if (tech == 32) { 226110234Syasuko.eckert@amd.com //Aggressive projections. 226210234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 226310234Syasuko.eckert@amd.com aspect_ratio[0][0] = 3.0; 226410234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; 226510234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width; 226610234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width; 226710234Syasuko.eckert@amd.com barrier_thickness = 0; 226810234Syasuko.eckert@amd.com dishing_thickness = 0; 226910234Syasuko.eckert@amd.com alpha_scatter = 1; 227010234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 227110234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 227210234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.21; 227310234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 227410234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 1.664; 227510234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 227610234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 227710234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 227810234Syasuko.eckert@amd.com ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 227910234Syasuko.eckert@amd.com fringe_cap); 228010234Syasuko.eckert@amd.com 228110234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um; 228210234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 228310234Syasuko.eckert@amd.com aspect_ratio[0][1] = 3.0; 228410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 228510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 228610234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 228710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 228810234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.21; 228910234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 229010234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 1.664; 229110234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 229210234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 229310234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 229410234Syasuko.eckert@amd.com fringe_cap); 229510234Syasuko.eckert@amd.com 229610234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um; 229710234Syasuko.eckert@amd.com aspect_ratio[0][2] = 3.0; 229810234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 229910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 230010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 230110234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 230210234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 230310234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.42; 230410234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 230510234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 1.664; 230610234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 230710234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 230810234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 230910234Syasuko.eckert@amd.com fringe_cap); 231010234Syasuko.eckert@amd.com 231110234Syasuko.eckert@amd.com //Conservative projections 231210234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 231310234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 231410234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 231510234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 231610234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 231710234Syasuko.eckert@amd.com barrier_thickness = 0.003; 231810234Syasuko.eckert@amd.com dishing_thickness = 0; 231910234Syasuko.eckert@amd.com alpha_scatter = 1; 232010234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 232110234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 232210234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.21; 232310234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 232410234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 2.214; 232510234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 232610234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 232710234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 232810234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 232910234Syasuko.eckert@amd.com fringe_cap); 233010234Syasuko.eckert@amd.com 233110234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 233210234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 233310234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 233410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 233510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 233610234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 233710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 233810234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.21; 233910234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 234010234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 2.214; 234110234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 234210234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 234310234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 234410234Syasuko.eckert@amd.com fringe_cap); 234510234Syasuko.eckert@amd.com 234610234Syasuko.eckert@amd.com wire_pitch[1][2] = 8 * g_ip->F_sz_um; 234710234Syasuko.eckert@amd.com aspect_ratio[1][2] = 2.2; 234810234Syasuko.eckert@amd.com wire_width = wire_pitch[1][2] / 2; 234910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][2] * wire_width; 235010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][2] - wire_width; 235110234Syasuko.eckert@amd.com dishing_thickness = 0.1 * wire_thickness; 235210234Syasuko.eckert@amd.com wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 235310234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 235410234Syasuko.eckert@amd.com ild_thickness[1][2] = 0.385; 235510234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 235610234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 2.214; 235710234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 235810234Syasuko.eckert@amd.com wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 235910234Syasuko.eckert@amd.com ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 236010234Syasuko.eckert@amd.com fringe_cap); 236110234Syasuko.eckert@amd.com //Nominal projections for commodity DRAM wordline/bitline 236210234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.032;//micron 236310234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.032);//F/micron 236410234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.032;//ohm/micron 236510234Syasuko.eckert@amd.com } else if (tech == 22) { 236610234Syasuko.eckert@amd.com //Aggressive projections. 236710234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local 236810234Syasuko.eckert@amd.com aspect_ratio[0][0] = 3.0; 236910234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; 237010234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width; 237110234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width; 237210234Syasuko.eckert@amd.com barrier_thickness = 0; 237310234Syasuko.eckert@amd.com dishing_thickness = 0; 237410234Syasuko.eckert@amd.com alpha_scatter = 1; 237510234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 237610234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 237710234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.15; 237810234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 237910234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 1.414; 238010234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 238110234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 238210234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 238310234Syasuko.eckert@amd.com ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 238410234Syasuko.eckert@amd.com fringe_cap); 238510234Syasuko.eckert@amd.com 238610234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global 238710234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 238810234Syasuko.eckert@amd.com aspect_ratio[0][1] = 3.0; 238910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 239010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 239110234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 239210234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 239310234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.15; 239410234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 239510234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 1.414; 239610234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 239710234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 239810234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 239910234Syasuko.eckert@amd.com fringe_cap); 240010234Syasuko.eckert@amd.com 240110234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global 240210234Syasuko.eckert@amd.com aspect_ratio[0][2] = 3.0; 240310234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 240410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 240510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 240610234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 240710234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 240810234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.3; 240910234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 241010234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 1.414; 241110234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 241210234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 241310234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 241410234Syasuko.eckert@amd.com fringe_cap); 241510234Syasuko.eckert@amd.com 241610234Syasuko.eckert@amd.com //Conservative projections 241710234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 241810234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 241910234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 242010234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 242110234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 242210234Syasuko.eckert@amd.com barrier_thickness = 0.003; 242310234Syasuko.eckert@amd.com dishing_thickness = 0; 242410234Syasuko.eckert@amd.com alpha_scatter = 1.05; 242510234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 242610234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 242710234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.15; 242810234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 242910234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 2.104; 243010234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 243110234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 243210234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 243310234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 243410234Syasuko.eckert@amd.com fringe_cap); 243510234Syasuko.eckert@amd.com 243610234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 243710234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 243810234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 243910234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 244010234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 244110234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 244210234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 244310234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.15; 244410234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 244510234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 2.104; 244610234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 244710234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 244810234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 244910234Syasuko.eckert@amd.com fringe_cap); 245010234Syasuko.eckert@amd.com 245110234Syasuko.eckert@amd.com wire_pitch[1][2] = 8 * g_ip->F_sz_um; 245210234Syasuko.eckert@amd.com aspect_ratio[1][2] = 2.2; 245310234Syasuko.eckert@amd.com wire_width = wire_pitch[1][2] / 2; 245410234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][2] * wire_width; 245510234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][2] - wire_width; 245610234Syasuko.eckert@amd.com dishing_thickness = 0.1 * wire_thickness; 245710234Syasuko.eckert@amd.com wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 245810234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 245910234Syasuko.eckert@amd.com ild_thickness[1][2] = 0.275; 246010234Syasuko.eckert@amd.com miller_value[1][2] = 1.5; 246110234Syasuko.eckert@amd.com horiz_dielectric_constant[1][2] = 2.104; 246210234Syasuko.eckert@amd.com vert_dielectric_constant[1][2] = 3.9; 246310234Syasuko.eckert@amd.com wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 246410234Syasuko.eckert@amd.com ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 246510234Syasuko.eckert@amd.com fringe_cap); 246610234Syasuko.eckert@amd.com //Nominal projections for commodity DRAM wordline/bitline 246710234Syasuko.eckert@amd.com wire_pitch[1][3] = 2 * 0.022;//micron 246810234Syasuko.eckert@amd.com wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.022);//F/micron 246910234Syasuko.eckert@amd.com wire_r_per_micron[1][3] = 12 / 0.022;//ohm/micron 247010234Syasuko.eckert@amd.com } 247110234Syasuko.eckert@amd.com 247210234Syasuko.eckert@amd.com else if (tech == 16) { 247310234Syasuko.eckert@amd.com //Aggressive projections. 247410234Syasuko.eckert@amd.com wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local 247510234Syasuko.eckert@amd.com aspect_ratio[0][0] = 3.0; 247610234Syasuko.eckert@amd.com wire_width = wire_pitch[0][0] / 2; 247710234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][0] * wire_width; 247810234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][0] - wire_width; 247910234Syasuko.eckert@amd.com barrier_thickness = 0; 248010234Syasuko.eckert@amd.com dishing_thickness = 0; 248110234Syasuko.eckert@amd.com alpha_scatter = 1; 248210234Syasuko.eckert@amd.com wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 248310234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 248410234Syasuko.eckert@amd.com ild_thickness[0][0] = 0.108; 248510234Syasuko.eckert@amd.com miller_value[0][0] = 1.5; 248610234Syasuko.eckert@amd.com horiz_dielectric_constant[0][0] = 1.202; 248710234Syasuko.eckert@amd.com vert_dielectric_constant[0][0] = 3.9; 248810234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 248910234Syasuko.eckert@amd.com wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 249010234Syasuko.eckert@amd.com ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 249110234Syasuko.eckert@amd.com fringe_cap); 249210234Syasuko.eckert@amd.com 249310234Syasuko.eckert@amd.com wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global 249410234Syasuko.eckert@amd.com aspect_ratio[0][1] = 3.0; 249510234Syasuko.eckert@amd.com wire_width = wire_pitch[0][1] / 2; 249610234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][1] * wire_width; 249710234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][1] - wire_width; 249810234Syasuko.eckert@amd.com wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 249910234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 250010234Syasuko.eckert@amd.com ild_thickness[0][1] = 0.108; 250110234Syasuko.eckert@amd.com miller_value[0][1] = 1.5; 250210234Syasuko.eckert@amd.com horiz_dielectric_constant[0][1] = 1.202; 250310234Syasuko.eckert@amd.com vert_dielectric_constant[0][1] = 3.9; 250410234Syasuko.eckert@amd.com wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 250510234Syasuko.eckert@amd.com ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 250610234Syasuko.eckert@amd.com fringe_cap); 250710234Syasuko.eckert@amd.com 250810234Syasuko.eckert@amd.com wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global 250910234Syasuko.eckert@amd.com aspect_ratio[0][2] = 3.0; 251010234Syasuko.eckert@amd.com wire_width = wire_pitch[0][2] / 2; 251110234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[0][2] * wire_width; 251210234Syasuko.eckert@amd.com wire_spacing = wire_pitch[0][2] - wire_width; 251310234Syasuko.eckert@amd.com wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 251410234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 251510234Syasuko.eckert@amd.com ild_thickness[0][2] = 0.216; 251610234Syasuko.eckert@amd.com miller_value[0][2] = 1.5; 251710234Syasuko.eckert@amd.com horiz_dielectric_constant[0][2] = 1.202; 251810234Syasuko.eckert@amd.com vert_dielectric_constant[0][2] = 3.9; 251910234Syasuko.eckert@amd.com wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 252010234Syasuko.eckert@amd.com ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 252110234Syasuko.eckert@amd.com fringe_cap); 252210234Syasuko.eckert@amd.com 252310234Syasuko.eckert@amd.com //Conservative projections 252410234Syasuko.eckert@amd.com wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 252510234Syasuko.eckert@amd.com aspect_ratio[1][0] = 2.0; 252610234Syasuko.eckert@amd.com wire_width = wire_pitch[1][0] / 2; 252710234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][0] * wire_width; 252810234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][0] - wire_width; 252910234Syasuko.eckert@amd.com barrier_thickness = 0.002; 253010234Syasuko.eckert@amd.com dishing_thickness = 0; 253110234Syasuko.eckert@amd.com alpha_scatter = 1.05; 253210234Syasuko.eckert@amd.com wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 253310234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 253410234Syasuko.eckert@amd.com ild_thickness[1][0] = 0.108; 253510234Syasuko.eckert@amd.com miller_value[1][0] = 1.5; 253610234Syasuko.eckert@amd.com horiz_dielectric_constant[1][0] = 1.998; 253710234Syasuko.eckert@amd.com vert_dielectric_constant[1][0] = 3.9; 253810234Syasuko.eckert@amd.com fringe_cap = 0.115e-15; 253910234Syasuko.eckert@amd.com wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 254010234Syasuko.eckert@amd.com ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 254110234Syasuko.eckert@amd.com fringe_cap); 254210234Syasuko.eckert@amd.com 254310234Syasuko.eckert@amd.com wire_pitch[1][1] = 4 * g_ip->F_sz_um; 254410234Syasuko.eckert@amd.com wire_width = wire_pitch[1][1] / 2; 254510234Syasuko.eckert@amd.com aspect_ratio[1][1] = 2.0; 254610234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][1] * wire_width; 254710234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][1] - wire_width; 254810234Syasuko.eckert@amd.com wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 254910234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 255010234Syasuko.eckert@amd.com ild_thickness[1][1] = 0.108; 255110234Syasuko.eckert@amd.com miller_value[1][1] = 1.5; 255210234Syasuko.eckert@amd.com horiz_dielectric_constant[1][1] = 1.998; 255310234Syasuko.eckert@amd.com vert_dielectric_constant[1][1] = 3.9; 255410234Syasuko.eckert@amd.com wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 255510234Syasuko.eckert@amd.com ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 255610234Syasuko.eckert@amd.com fringe_cap); 255710234Syasuko.eckert@amd.com 255810234Syasuko.eckert@amd.com wire_pitch[1][2] = 8 * g_ip->F_sz_um; 255910234Syasuko.eckert@amd.com aspect_ratio[1][2] = 2.2; 256010234Syasuko.eckert@amd.com wire_width = wire_pitch[1][2] / 2; 256110234Syasuko.eckert@amd.com wire_thickness = aspect_ratio[1][2] * wire_width; 256210234Syasuko.eckert@amd.com wire_spacing = wire_pitch[1][2] - wire_width; 256310234Syasuko.eckert@amd.com dishing_thickness = 0.1 * wire_thickness; 256410234Syasuko.eckert@amd.com wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 256510234Syasuko.eckert@amd.com wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 256610152Satgutier@umich.edu ild_thickness[1][2] = 0.198; 256710152Satgutier@umich.edu miller_value[1][2] = 1.5; 256810152Satgutier@umich.edu horiz_dielectric_constant[1][2] = 1.998; 256910152Satgutier@umich.edu vert_dielectric_constant[1][2] = 3.9; 257010152Satgutier@umich.edu wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 257110234Syasuko.eckert@amd.com ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 257210234Syasuko.eckert@amd.com fringe_cap); 257310152Satgutier@umich.edu //Nominal projections for commodity DRAM wordline/bitline 257410152Satgutier@umich.edu wire_pitch[1][3] = 2 * 0.016;//micron 257510152Satgutier@umich.edu wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.016);//F/micron 257610152Satgutier@umich.edu wire_r_per_micron[1][3] = 12 / 0.016;//ohm/micron 257710234Syasuko.eckert@amd.com } 257810234Syasuko.eckert@amd.com g_tp.wire_local.pitch += curr_alpha * 257910234Syasuko.eckert@amd.com wire_pitch[g_ip->ic_proj_type] 258010234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 258110234Syasuko.eckert@amd.com g_tp.wire_local.R_per_um += curr_alpha * 258210234Syasuko.eckert@amd.com wire_r_per_micron[g_ip->ic_proj_type] 258310234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 258410234Syasuko.eckert@amd.com g_tp.wire_local.C_per_um += curr_alpha * 258510234Syasuko.eckert@amd.com wire_c_per_micron[g_ip->ic_proj_type] 258610234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 258710234Syasuko.eckert@amd.com g_tp.wire_local.aspect_ratio += curr_alpha * 258810234Syasuko.eckert@amd.com aspect_ratio[g_ip->ic_proj_type] 258910234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 259010234Syasuko.eckert@amd.com g_tp.wire_local.ild_thickness += curr_alpha * 259110234Syasuko.eckert@amd.com ild_thickness[g_ip->ic_proj_type] 259210234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 259310234Syasuko.eckert@amd.com g_tp.wire_local.miller_value += curr_alpha * 259410234Syasuko.eckert@amd.com miller_value[g_ip->ic_proj_type] 259510234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 259610234Syasuko.eckert@amd.com g_tp.wire_local.horiz_dielectric_constant += curr_alpha * 259710234Syasuko.eckert@amd.com horiz_dielectric_constant[g_ip->ic_proj_type] 259810234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 259910234Syasuko.eckert@amd.com g_tp.wire_local.vert_dielectric_constant += curr_alpha * 260010234Syasuko.eckert@amd.com vert_dielectric_constant[g_ip->ic_proj_type] 260110234Syasuko.eckert@amd.com [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 260210152Satgutier@umich.edu 260310234Syasuko.eckert@amd.com g_tp.wire_inside_mat.pitch += curr_alpha * 260410234Syasuko.eckert@amd.com wire_pitch[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 260510234Syasuko.eckert@amd.com g_tp.wire_inside_mat.R_per_um += curr_alpha * 260610234Syasuko.eckert@amd.com wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 260710234Syasuko.eckert@amd.com g_tp.wire_inside_mat.C_per_um += curr_alpha * 260810234Syasuko.eckert@amd.com wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 260910234Syasuko.eckert@amd.com g_tp.wire_inside_mat.aspect_ratio += curr_alpha * 261010234Syasuko.eckert@amd.com aspect_ratio[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 261110234Syasuko.eckert@amd.com g_tp.wire_inside_mat.ild_thickness += curr_alpha * 261210234Syasuko.eckert@amd.com ild_thickness[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 261310234Syasuko.eckert@amd.com g_tp.wire_inside_mat.miller_value += curr_alpha * 261410234Syasuko.eckert@amd.com miller_value[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 261510234Syasuko.eckert@amd.com g_tp.wire_inside_mat.horiz_dielectric_constant += curr_alpha * 261610234Syasuko.eckert@amd.com horiz_dielectric_constant[g_ip->ic_proj_type] 261710234Syasuko.eckert@amd.com [g_ip->wire_is_mat_type]; 261810234Syasuko.eckert@amd.com g_tp.wire_inside_mat.vert_dielectric_constant += curr_alpha * 261910234Syasuko.eckert@amd.com vert_dielectric_constant [g_ip->ic_proj_type] 262010234Syasuko.eckert@amd.com [g_ip->wire_is_mat_type]; 262110152Satgutier@umich.edu 262210234Syasuko.eckert@amd.com g_tp.wire_outside_mat.pitch += curr_alpha * 262310234Syasuko.eckert@amd.com wire_pitch[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 262410234Syasuko.eckert@amd.com g_tp.wire_outside_mat.R_per_um += curr_alpha * 262510234Syasuko.eckert@amd.com wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 262610234Syasuko.eckert@amd.com g_tp.wire_outside_mat.C_per_um += curr_alpha * 262710234Syasuko.eckert@amd.com wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 262810234Syasuko.eckert@amd.com g_tp.wire_outside_mat.aspect_ratio += curr_alpha * 262910234Syasuko.eckert@amd.com aspect_ratio[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 263010234Syasuko.eckert@amd.com g_tp.wire_outside_mat.ild_thickness += curr_alpha * 263110234Syasuko.eckert@amd.com ild_thickness[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 263210234Syasuko.eckert@amd.com g_tp.wire_outside_mat.miller_value += curr_alpha * 263310234Syasuko.eckert@amd.com miller_value[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 263410234Syasuko.eckert@amd.com g_tp.wire_outside_mat.horiz_dielectric_constant += curr_alpha * 263510234Syasuko.eckert@amd.com horiz_dielectric_constant[g_ip->ic_proj_type] 263610234Syasuko.eckert@amd.com [g_ip->wire_os_mat_type]; 263710234Syasuko.eckert@amd.com g_tp.wire_outside_mat.vert_dielectric_constant += curr_alpha * 263810234Syasuko.eckert@amd.com vert_dielectric_constant [g_ip->ic_proj_type] 263910234Syasuko.eckert@amd.com [g_ip->wire_os_mat_type]; 264010152Satgutier@umich.edu 264110234Syasuko.eckert@amd.com g_tp.unit_len_wire_del = g_tp.wire_inside_mat.R_per_um * 264210234Syasuko.eckert@amd.com g_tp.wire_inside_mat.C_per_um / 2; 264310152Satgutier@umich.edu 264410234Syasuko.eckert@amd.com g_tp.sense_delay += curr_alpha * SENSE_AMP_D; 264510234Syasuko.eckert@amd.com g_tp.sense_dy_power += curr_alpha * SENSE_AMP_P; 264610152Satgutier@umich.edu 264710234Syasuko.eckert@amd.com } 264810234Syasuko.eckert@amd.com g_tp.fringe_cap = fringe_cap; 264910152Satgutier@umich.edu 265010234Syasuko.eckert@amd.com double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1); 265110234Syasuko.eckert@amd.com double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(); 265210234Syasuko.eckert@amd.com double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0); 265310234Syasuko.eckert@amd.com double tf = rd * c_load; 265410234Syasuko.eckert@amd.com g_tp.kinv = horowitz(0, tf, 0.5, 0.5, RISE); 265510234Syasuko.eckert@amd.com double KLOAD = 1; 265610234Syasuko.eckert@amd.com c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 265710234Syasuko.eckert@amd.com drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, g_tp.cell_h_def) + 265810234Syasuko.eckert@amd.com gate_C(g_tp.min_w_nmos_ * 4 * (1 + p_to_n_sizing_r), 0.0)); 265910234Syasuko.eckert@amd.com tf = rd * c_load; 266010234Syasuko.eckert@amd.com g_tp.FO4 = horowitz(0, tf, 0.5, 0.5, RISE); 266110152Satgutier@umich.edu} 266210152Satgutier@umich.edu 2663