router.cc revision 10152
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31
32
33
34#include "router.h"
35
36Router::Router(
37    double flit_size_,
38    double vc_buf, /* vc size = vc_buffer_size * flit_size */
39    double vc_c,
40    TechnologyParameter::DeviceType *dt,
41    double I_,
42    double O_,
43    double M_
44    ):flit_size(flit_size_),
45      deviceType(dt),
46      I(I_),
47      O(O_),
48      M(M_)
49{
50  vc_buffer_size = vc_buf;
51  vc_count = vc_c;
52  min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio*g_tp.min_w_nmos_;
53  double technology = g_ip->F_sz_um;
54
55  Vdd = dt->Vdd;
56
57  /*Crossbar parameters. Transmisson gate is employed for connector*/
58  NTtr = 10*technology*1e-6/2; /*Transmission gate's nmos tr. length*/
59  PTtr = 20*technology*1e-6/2; /* pmos tr. length*/
60  wt = 15*technology*1e-6/2; /*track width*/
61  ht = 15*technology*1e-6/2; /*track height*/
62//  I = 5; /*Number of crossbar input ports*/
63//  O = 5; /*Number of crossbar output ports*/
64  NTi = 12.5*technology*1e-6/2;
65  PTi = 25*technology*1e-6/2;
66
67  NTid = 60*technology*1e-6/2; //m
68  PTid = 120*technology*1e-6/2; // m
69  NTod = 60*technology*1e-6/2; // m
70  PTod = 120*technology*1e-6/2; // m
71
72  calc_router_parameters();
73}
74
75Router::~Router(){}
76
77
78double //wire cap with triple spacing
79Router::Cw3(double length) {
80  Wire wc(g_ip->wt, length, 1, 3, 3);
81  return (wc.wire_cap(length));
82}
83
84/*Function to calculate the gate capacitance*/
85double
86Router::gate_cap(double w) {
87  return (double) gate_C (w*1e6 /*u*/, 0);
88}
89
90/*Function to calculate the diffusion capacitance*/
91double
92Router::diff_cap(double w, int type /*0 for n-mos and 1 for p-mos*/,
93    double s /*number of stacking transistors*/) {
94  return (double) drain_C_(w*1e6 /*u*/, type, (int) s, 1, g_tp.cell_h_def);
95}
96
97
98/*crossbar related functions */
99
100// Model for simple transmission gate
101double
102Router::transmission_buf_inpcap() {
103  return diff_cap(NTtr, 0, 1)+diff_cap(PTtr, 1, 1);
104}
105
106double
107Router::transmission_buf_outcap() {
108  return diff_cap(NTtr, 0, 1)+diff_cap(PTtr, 1, 1);
109}
110
111double
112Router::transmission_buf_ctrcap() {
113  return gate_cap(NTtr)+gate_cap(PTtr);
114}
115
116double
117Router::crossbar_inpline() {
118  return (Cw3(O*flit_size*wt) + O*transmission_buf_inpcap() + gate_cap(NTid) +
119      gate_cap(PTid) + diff_cap(NTid, 0, 1) + diff_cap(PTid, 1, 1));
120}
121
122double
123Router::crossbar_outline() {
124  return (Cw3(I*flit_size*ht) + I*transmission_buf_outcap() + gate_cap(NTod) +
125      gate_cap(PTod) + diff_cap(NTod, 0, 1) + diff_cap(PTod, 1, 1));
126}
127
128double
129Router::crossbar_ctrline() {
130  return (Cw3(0.5*O*flit_size*wt) + flit_size*transmission_buf_ctrcap() +
131      diff_cap(NTi, 0, 1) + diff_cap(PTi, 1, 1) +
132      gate_cap(NTi) + gate_cap(PTi));
133}
134
135double
136Router::tr_crossbar_power() {
137  return (crossbar_inpline()*Vdd*Vdd*flit_size/2 +
138      crossbar_outline()*Vdd*Vdd*flit_size/2)*2;
139}
140
141void Router::buffer_stats()
142{
143  DynamicParameter dyn_p;
144  dyn_p.is_tag      = false;
145  dyn_p.pure_cam    = false;
146  dyn_p.fully_assoc = false;
147  dyn_p.pure_ram    = true;
148  dyn_p.is_dram     = false;
149  dyn_p.is_main_mem = false;
150  dyn_p.num_subarrays = 1;
151  dyn_p.num_mats = 1;
152  dyn_p.Ndbl = 1;
153  dyn_p.Ndwl = 1;
154  dyn_p.Nspd = 1;
155  dyn_p.deg_bl_muxing = 1;
156  dyn_p.deg_senseamp_muxing_non_associativity = 1;
157  dyn_p.Ndsam_lev_1 = 1;
158  dyn_p.Ndsam_lev_2 = 1;
159  dyn_p.Ndcm = 1;
160  dyn_p.number_addr_bits_mat = 8;
161  dyn_p.number_way_select_signals_mat = 1;
162  dyn_p.number_subbanks_decode = 0;
163  dyn_p.num_act_mats_hor_dir = 1;
164  dyn_p.V_b_sense = Vdd; // FIXME check power calc.
165  dyn_p.ram_cell_tech_type = 0;
166  dyn_p.num_r_subarray = (int) vc_buffer_size;
167  dyn_p.num_c_subarray = (int) flit_size * (int) vc_count;
168  dyn_p.num_mats_h_dir = 1;
169  dyn_p.num_mats_v_dir = 1;
170  dyn_p.num_do_b_subbank = (int)flit_size;
171  dyn_p.num_di_b_subbank = (int)flit_size;
172  dyn_p.num_do_b_mat = (int) flit_size;
173  dyn_p.num_di_b_mat = (int) flit_size;
174  dyn_p.num_do_b_mat = (int) flit_size;
175  dyn_p.num_di_b_mat = (int) flit_size;
176  dyn_p.num_do_b_bank_per_port = (int) flit_size;
177  dyn_p.num_di_b_bank_per_port = (int) flit_size;
178  dyn_p.out_w = (int) flit_size;
179
180  dyn_p.use_inp_params = 1;
181  dyn_p.num_wr_ports = (unsigned int) vc_count;
182  dyn_p.num_rd_ports = 1;//(unsigned int) vc_count;//based on Bill Dally's book
183  dyn_p.num_rw_ports = 0;
184  dyn_p.num_se_rd_ports =0;
185  dyn_p.num_search_ports =0;
186
187
188
189  dyn_p.cell.h = g_tp.sram.b_h + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_wr_ports +
190      dyn_p.num_rw_ports - 1 + dyn_p.num_rd_ports);
191  dyn_p.cell.w = g_tp.sram.b_w + 2 * g_tp.wire_outside_mat.pitch * (dyn_p.num_rw_ports - 1 +
192      (dyn_p.num_rd_ports - dyn_p.num_se_rd_ports) +
193      dyn_p.num_wr_ports) + g_tp.wire_outside_mat.pitch * dyn_p.num_se_rd_ports;
194
195  Mat buff(dyn_p);
196  buff.compute_delays(0);
197  buff.compute_power_energy();
198  buffer.power.readOp  = buff.power.readOp;
199  buffer.power.writeOp = buffer.power.readOp; //FIXME
200  buffer.area = buff.area;
201}
202
203
204
205  void
206Router::cb_stats ()
207{
208  if (1) {
209    Crossbar c_b(I, O, flit_size);
210    c_b.compute_power();
211    crossbar.delay = c_b.delay;
212    crossbar.power.readOp.dynamic = c_b.power.readOp.dynamic;
213    crossbar.power.readOp.leakage = c_b.power.readOp.leakage;
214    crossbar.power.readOp.gate_leakage = c_b.power.readOp.gate_leakage;
215    crossbar.area = c_b.area;
216//  c_b.print_crossbar();
217  }
218  else {
219    crossbar.power.readOp.dynamic = tr_crossbar_power();
220    crossbar.power.readOp.leakage = flit_size * I * O *
221        cmos_Isub_leakage(NTtr*g_tp.min_w_nmos_, PTtr*min_w_pmos, 1, tg);
222    crossbar.power.readOp.gate_leakage = flit_size * I * O *
223        cmos_Ig_leakage(NTtr*g_tp.min_w_nmos_, PTtr*min_w_pmos, 1, tg);
224  }
225}
226
227void
228Router::get_router_power()
229{
230  /* calculate buffer stats */
231  buffer_stats();
232
233  /* calculate cross-bar stats */
234  cb_stats();
235
236  /* calculate arbiter stats */
237  Arbiter vcarb(vc_count, flit_size, buffer.area.w);
238  Arbiter cbarb(I, flit_size, crossbar.area.w);
239  vcarb.compute_power();
240  cbarb.compute_power();
241  arbiter.power.readOp.dynamic = vcarb.power.readOp.dynamic * I +
242    cbarb.power.readOp.dynamic * O;
243  arbiter.power.readOp.leakage = vcarb.power.readOp.leakage * I +
244    cbarb.power.readOp.leakage * O;
245  arbiter.power.readOp.gate_leakage = vcarb.power.readOp.gate_leakage * I +
246    cbarb.power.readOp.gate_leakage * O;
247
248//  arb_stats();
249  power.readOp.dynamic = ((buffer.power.readOp.dynamic+buffer.power.writeOp.dynamic) +
250                  crossbar.power.readOp.dynamic +
251                  arbiter.power.readOp.dynamic)*MIN(I, O)*M;
252  double pppm_t[4]    = {1,I,I,1};
253  power = power + (buffer.power*pppm_t + crossbar.power + arbiter.power)*pppm_lkg;
254
255}
256
257  void
258Router::get_router_delay ()
259{
260  FREQUENCY=5; // move this to config file --TODO
261  cycle_time = (1/(double)FREQUENCY)*1e3; //ps
262  delay = 4;
263  max_cyc = 17 * g_tp.FO4; //s
264  max_cyc *= 1e12; //ps
265  if (cycle_time < max_cyc) {
266    FREQUENCY = (1/max_cyc)*1e3; //GHz
267  }
268}
269
270  void
271Router::get_router_area()
272{
273  area.h = I*buffer.area.h;
274  area.w = buffer.area.w+crossbar.area.w;
275}
276
277  void
278Router::calc_router_parameters()
279{
280  /* calculate router frequency and pipeline cycles */
281  get_router_delay();
282
283  /* router power stats */
284  get_router_power();
285
286  /* area stats */
287  get_router_area();
288}
289
290  void
291Router::print_router()
292{
293  cout << "\n\nRouter stats:\n";
294  cout << "\tRouter Area - "<< area.get_area()*1e-6<<"(mm^2)\n";
295  cout << "\tMaximum possible network frequency - " << (1/max_cyc)*1e3 << "GHz\n";
296  cout << "\tNetwork frequency - " << FREQUENCY <<" GHz\n";
297  cout << "\tNo. of Virtual channels - " << vc_count << "\n";
298  cout << "\tNo. of pipeline stages - " << delay << endl;
299  cout << "\tLink bandwidth - " << flit_size << " (bits)\n";
300  cout << "\tNo. of buffer entries per virtual channel -  "<< vc_buffer_size << "\n";
301  cout << "\tSimple buffer Area - "<< buffer.area.get_area()*1e-6<<"(mm^2)\n";
302  cout << "\tSimple buffer access (Read) - " << buffer.power.readOp.dynamic * 1e9 <<" (nJ)\n";
303  cout << "\tSimple buffer leakage - " << buffer.power.readOp.leakage * 1e3 <<" (mW)\n";
304  cout << "\tCrossbar Area - "<< crossbar.area.get_area()*1e-6<<"(mm^2)\n";
305  cout << "\tCross bar access energy - " << crossbar.power.readOp.dynamic * 1e9<<" (nJ)\n";
306  cout << "\tCross bar leakage power - " << crossbar.power.readOp.leakage * 1e3<<" (mW)\n";
307  cout << "\tArbiter access energy (VC arb + Crossbar arb) - "<<arbiter.power.readOp.dynamic * 1e9 <<" (nJ)\n";
308  cout << "\tArbiter leakage (VC arb + Crossbar arb) - "<<arbiter.power.readOp.leakage * 1e3 <<" (mW)\n";
309
310}
311
312