parameter.h revision 10234 
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32
33
34
35#ifndef __PARAMETER_H__
36#define __PARAMETER_H__
37
38#include "area.h"
39#include "cacti_interface.h"
40#include "const.h"
41#include "io.h"
42
43// parameters which are functions of certain device technology
44class TechnologyParameter {
45public:
46    class DeviceType {
47    public:
48        double C_g_ideal;
49        double C_fringe;
50        double C_overlap;
51        double C_junc;  // C_junc_area
52        double C_junc_sidewall;
53        double l_phy;
54        double l_elec;
55        double R_nch_on;
56        double R_pch_on;
57        double Vdd;
58        double Vth;
59        double I_on_n;
60        double I_on_p;
61        double I_off_n;
62        double I_off_p;
63        double I_g_on_n;
64        double I_g_on_p;
65        double C_ox;
66        double t_ox;
67        double n_to_p_eff_curr_drv_ratio;
68        double long_channel_leakage_reduction;
69
70        DeviceType(): C_g_ideal(0), C_fringe(0), C_overlap(0), C_junc(0),
71                C_junc_sidewall(0), l_phy(0), l_elec(0), R_nch_on(0), R_pch_on(0),
72                Vdd(0), Vth(0),
73                I_on_n(0), I_on_p(0), I_off_n(0), I_off_p(0), I_g_on_n(0),
74                      I_g_on_p(0),
75                C_ox(0), t_ox(0), n_to_p_eff_curr_drv_ratio(0),
76                      long_channel_leakage_reduction(0) { };
77        void reset() {
78            C_g_ideal = 0;
79            C_fringe  = 0;
80            C_overlap = 0;
81            C_junc    = 0;
82            l_phy     = 0;
83            l_elec    = 0;
84            R_nch_on  = 0;
85            R_pch_on  = 0;
86            Vdd       = 0;
87            Vth       = 0;
88            I_on_n    = 0;
89            I_on_p    = 0;
90            I_off_n   = 0;
91            I_off_p   = 0;
92            I_g_on_n   = 0;
93            I_g_on_p   = 0;
94            C_ox      = 0;
95            t_ox      = 0;
96            n_to_p_eff_curr_drv_ratio = 0;
97            long_channel_leakage_reduction = 0;
98        }
99
100        void display(uint32_t indent = 0);
101    };
102    class InterconnectType {
103    public:
104        double pitch;
105        double R_per_um;
106        double C_per_um;
107        double horiz_dielectric_constant;
108        double vert_dielectric_constant;
109        double aspect_ratio;
110        double miller_value;
111        double ild_thickness;
112
113        InterconnectType(): pitch(0), R_per_um(0), C_per_um(0) { };
114
115        void reset() {
116            pitch = 0;
117            R_per_um = 0;
118            C_per_um = 0;
119            horiz_dielectric_constant = 0;
120            vert_dielectric_constant = 0;
121            aspect_ratio = 0;
122            miller_value = 0;
123            ild_thickness = 0;
124        }
125
126        void display(uint32_t indent = 0);
127    };
128    class MemoryType {
129    public:
130        double b_w;
131        double b_h;
132        double cell_a_w;
133        double cell_pmos_w;
134        double cell_nmos_w;
135        double Vbitpre;
136
137        void reset() {
138            b_w = 0;
139            b_h = 0;
140            cell_a_w = 0;
141            cell_pmos_w = 0;
142            cell_nmos_w = 0;
143            Vbitpre = 0;
144        }
145
146        void display(uint32_t indent = 0);
147    };
148
149    class ScalingFactor {
150    public:
151        double logic_scaling_co_eff;
152        double core_tx_density;
153        double long_channel_leakage_reduction;
154
155        ScalingFactor(): logic_scaling_co_eff(0), core_tx_density(0),
156                long_channel_leakage_reduction(0) { };
157
158        void reset() {
159            logic_scaling_co_eff = 0;
160            core_tx_density = 0;
161            long_channel_leakage_reduction = 0;
162        }
163
164        void display(uint32_t indent = 0);
165    };
166
167    double ram_wl_stitching_overhead_;
168    double min_w_nmos_;
169    double max_w_nmos_;
170    double max_w_nmos_dec;
171    double unit_len_wire_del;
172    double FO4;
173    double kinv;
174    double vpp;
175    double w_sense_en;
176    double w_sense_n;
177    double w_sense_p;
178    double sense_delay;
179    double sense_dy_power;
180    double w_iso;
181    double w_poly_contact;
182    double spacing_poly_to_poly;
183    double spacing_poly_to_contact;
184
185    double w_comp_inv_p1;
186    double w_comp_inv_p2;
187    double w_comp_inv_p3;
188    double w_comp_inv_n1;
189    double w_comp_inv_n2;
190    double w_comp_inv_n3;
191    double w_eval_inv_p;
192    double w_eval_inv_n;
193    double w_comp_n;
194    double w_comp_p;
195
196    double dram_cell_I_on;
197    double dram_cell_Vdd;
198    double dram_cell_I_off_worst_case_len_temp;
199    double dram_cell_C;
200    double gm_sense_amp_latch;
201
202    double w_nmos_b_mux;
203    double w_nmos_sa_mux;
204    double w_pmos_bl_precharge;
205    double w_pmos_bl_eq;
206    double MIN_GAP_BET_P_AND_N_DIFFS;
207    double MIN_GAP_BET_SAME_TYPE_DIFFS;
208    double HPOWERRAIL;
209    double cell_h_def;
210
211    double chip_layout_overhead;
212    double macro_layout_overhead;
213    double sckt_co_eff;
214
215    double fringe_cap;
216
217    uint64_t h_dec;
218
219    DeviceType sram_cell;   // SRAM cell transistor
220    DeviceType dram_acc;    // DRAM access transistor
221    DeviceType dram_wl;     // DRAM wordline transistor
222    DeviceType peri_global; // peripheral global
223    DeviceType cam_cell;   // SRAM cell transistor
224
225    InterconnectType wire_local;
226    InterconnectType wire_inside_mat;
227    InterconnectType wire_outside_mat;
228
229    ScalingFactor scaling_factor;
230
231    MemoryType sram;
232    MemoryType dram;
233    MemoryType cam;
234
235    void display(uint32_t indent = 0);
236
237    void reset() {
238        dram_cell_Vdd  = 0;
239        dram_cell_I_on = 0;
240        dram_cell_C    = 0;
241        vpp            = 0;
242
243        sense_delay               = 0;
244        sense_dy_power            = 0;
245        fringe_cap                = 0;
246//    horiz_dielectric_constant = 0;
247//    vert_dielectric_constant  = 0;
248//    aspect_ratio              = 0;
249//    miller_value              = 0;
250//    ild_thickness             = 0;
251
252        dram_cell_I_off_worst_case_len_temp = 0;
253
254        sram_cell.reset();
255        dram_acc.reset();
256        dram_wl.reset();
257        peri_global.reset();
258        cam_cell.reset();
259
260        scaling_factor.reset();
261
262        wire_local.reset();
263        wire_inside_mat.reset();
264        wire_outside_mat.reset();
265
266        sram.reset();
267        dram.reset();
268        cam.reset();
269
270        chip_layout_overhead  = 0;
271        macro_layout_overhead = 0;
272        sckt_co_eff           = 0;
273    }
274};
275
276
277
278class DynamicParameter {
279public:
280    bool is_tag;
281    bool pure_ram;
282    bool pure_cam;
283    bool fully_assoc;
284    int tagbits;
285    int num_subarrays;  // only for leakage computation  -- the number of subarrays per bank
286    int num_mats;       // only for leakage computation  -- the number of mats per bank
287    double Nspd;
288    int Ndwl;
289    int Ndbl;
290    int Ndcm;
291    int deg_bl_muxing;
292    int deg_senseamp_muxing_non_associativity;
293    int Ndsam_lev_1;
294    int Ndsam_lev_2;
295    int number_addr_bits_mat;             // per port
296    int number_subbanks_decode;           // per_port
297    int num_di_b_bank_per_port;
298    int num_do_b_bank_per_port;
299    int num_di_b_mat;
300    int num_do_b_mat;
301    int num_di_b_subbank;
302    int num_do_b_subbank;
303
304    int num_si_b_mat;
305    int num_so_b_mat;
306    int num_si_b_subbank;
307    int num_so_b_subbank;
308    int num_si_b_bank_per_port;
309    int num_so_b_bank_per_port;
310
311    int number_way_select_signals_mat;
312    int num_act_mats_hor_dir;
313
314    int num_act_mats_hor_dir_sl;
315    bool is_dram;
316    double V_b_sense;
317    unsigned int num_r_subarray;
318    unsigned int num_c_subarray;
319    int tag_num_r_subarray;//sheng: fully associative cache tag and data must be computed together, data and tag must be separate
320    int tag_num_c_subarray;
321    int data_num_r_subarray;
322    int data_num_c_subarray;
323    int num_mats_h_dir;
324    int num_mats_v_dir;
325    uint32_t ram_cell_tech_type;
326    double dram_refresh_period;
327
328    DynamicParameter();
329    DynamicParameter(
330        bool         is_tag_,
331        int          pure_ram_,
332        int          pure_cam_,
333        double       Nspd_,
334        unsigned int Ndwl_,
335        unsigned int Ndbl_,
336        unsigned int Ndcm_,
337        unsigned int Ndsam_lev_1_,
338        unsigned int Ndsam_lev_2_,
339        bool         is_main_mem_);
340
341    int use_inp_params;
342    unsigned int num_rw_ports;
343    unsigned int num_rd_ports;
344    unsigned int num_wr_ports;
345    unsigned int num_se_rd_ports;  // number of single ended read ports
346    unsigned int num_search_ports;
347    unsigned int out_w;// == nr_bits_out
348    bool   is_main_mem;
349    Area   cell, cam_cell;//cell is the sram_cell in both nomal cache/ram and FA.
350    bool   is_valid;
351};
352
353
354
355extern InputParameter * g_ip;
356extern TechnologyParameter g_tp;
357
358#endif
359
360