io.cc revision 10234
110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT/CACTI 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu 3510152Satgutier@umich.edu#include <fstream> 3610152Satgutier@umich.edu#include <iostream> 3710152Satgutier@umich.edu#include <sstream> 3810152Satgutier@umich.edu 3910152Satgutier@umich.edu#include "Ucache.h" 4010152Satgutier@umich.edu#include "arbiter.h" 4110152Satgutier@umich.edu#include "area.h" 4210152Satgutier@umich.edu#include "basic_circuit.h" 4310152Satgutier@umich.edu#include "crossbar.h" 4410152Satgutier@umich.edu#include "io.h" 4510152Satgutier@umich.edu#include "nuca.h" 4610152Satgutier@umich.edu#include "parameter.h" 4710152Satgutier@umich.edu//#include "highradix.h" 4810152Satgutier@umich.edu 4910152Satgutier@umich.eduusing namespace std; 5010152Satgutier@umich.edu 5110152Satgutier@umich.edu 5210152Satgutier@umich.edu/* Parses "cache.cfg" file */ 5310234Syasuko.eckert@amd.comvoid 5410234Syasuko.eckert@amd.comInputParameter::parse_cfg(const string & in_file) { 5510234Syasuko.eckert@amd.com FILE *fp = fopen(in_file.c_str(), "r"); 5610234Syasuko.eckert@amd.com char line[5000]; 5710234Syasuko.eckert@amd.com char jk[5000]; 5810234Syasuko.eckert@amd.com char temp_var[5000]; 5910152Satgutier@umich.edu 6010234Syasuko.eckert@amd.com if (!fp) { 6110234Syasuko.eckert@amd.com cout << in_file << " is missing!\n"; 6210234Syasuko.eckert@amd.com exit(-1); 6310152Satgutier@umich.edu } 6410152Satgutier@umich.edu 6510234Syasuko.eckert@amd.com while (fscanf(fp, "%[^\n]\n", line) != EOF) { 6610152Satgutier@umich.edu 6710234Syasuko.eckert@amd.com if (!strncmp("-size", line, strlen("-size"))) { 6810234Syasuko.eckert@amd.com sscanf(line, "-size %[(:-~)*]%u", jk, &(cache_sz)); 6910234Syasuko.eckert@amd.com continue; 7010234Syasuko.eckert@amd.com } 7110152Satgutier@umich.edu 7210234Syasuko.eckert@amd.com if (!strncmp("-page size", line, strlen("-page size"))) { 7310234Syasuko.eckert@amd.com sscanf(line, "-page size %[(:-~)*]%u", jk, &(page_sz_bits)); 7410234Syasuko.eckert@amd.com continue; 7510234Syasuko.eckert@amd.com } 7610152Satgutier@umich.edu 7710234Syasuko.eckert@amd.com if (!strncmp("-burst length", line, strlen("-burst length"))) { 7810234Syasuko.eckert@amd.com sscanf(line, "-burst %[(:-~)*]%u", jk, &(burst_len)); 7910234Syasuko.eckert@amd.com continue; 8010234Syasuko.eckert@amd.com } 8110152Satgutier@umich.edu 8210234Syasuko.eckert@amd.com if (!strncmp("-internal prefetch width", line, strlen("-internal prefetch width"))) { 8310234Syasuko.eckert@amd.com sscanf(line, "-internal prefetch %[(:-~)*]%u", jk, &(int_prefetch_w)); 8410234Syasuko.eckert@amd.com continue; 8510234Syasuko.eckert@amd.com } 8610152Satgutier@umich.edu 8710234Syasuko.eckert@amd.com if (!strncmp("-block", line, strlen("-block"))) { 8810234Syasuko.eckert@amd.com sscanf(line, "-block size (bytes) %d", &(line_sz)); 8910234Syasuko.eckert@amd.com continue; 9010234Syasuko.eckert@amd.com } 9110152Satgutier@umich.edu 9210234Syasuko.eckert@amd.com if (!strncmp("-associativity", line, strlen("-associativity"))) { 9310234Syasuko.eckert@amd.com sscanf(line, "-associativity %d", &(assoc)); 9410234Syasuko.eckert@amd.com continue; 9510234Syasuko.eckert@amd.com } 9610152Satgutier@umich.edu 9710234Syasuko.eckert@amd.com if (!strncmp("-read-write", line, strlen("-read-write"))) { 9810234Syasuko.eckert@amd.com sscanf(line, "-read-write port %d", &(num_rw_ports)); 9910234Syasuko.eckert@amd.com continue; 10010234Syasuko.eckert@amd.com } 10110152Satgutier@umich.edu 10210234Syasuko.eckert@amd.com if (!strncmp("-exclusive read", line, strlen("exclusive read"))) { 10310234Syasuko.eckert@amd.com sscanf(line, "-exclusive read port %d", &(num_rd_ports)); 10410234Syasuko.eckert@amd.com continue; 10510234Syasuko.eckert@amd.com } 10610152Satgutier@umich.edu 10710234Syasuko.eckert@amd.com if (!strncmp("-exclusive write", line, strlen("-exclusive write"))) { 10810234Syasuko.eckert@amd.com sscanf(line, "-exclusive write port %d", &(num_wr_ports)); 10910234Syasuko.eckert@amd.com continue; 11010234Syasuko.eckert@amd.com } 11110152Satgutier@umich.edu 11210234Syasuko.eckert@amd.com if (!strncmp("-single ended", line, strlen("-single ended"))) { 11310234Syasuko.eckert@amd.com sscanf(line, "-single %[(:-~)*]%d", jk, 11410234Syasuko.eckert@amd.com &(num_se_rd_ports)); 11510234Syasuko.eckert@amd.com continue; 11610234Syasuko.eckert@amd.com } 11710152Satgutier@umich.edu 11810234Syasuko.eckert@amd.com if (!strncmp("-search", line, strlen("-search"))) { 11910234Syasuko.eckert@amd.com sscanf(line, "-search port %d", &(num_search_ports)); 12010234Syasuko.eckert@amd.com continue; 12110234Syasuko.eckert@amd.com } 12210152Satgutier@umich.edu 12310234Syasuko.eckert@amd.com if (!strncmp("-UCA bank", line, strlen("-UCA bank"))) { 12410234Syasuko.eckert@amd.com sscanf(line, "-UCA bank%[((:-~)| )*]%d", jk, &(nbanks)); 12510234Syasuko.eckert@amd.com continue; 12610234Syasuko.eckert@amd.com } 12710152Satgutier@umich.edu 12810234Syasuko.eckert@amd.com if (!strncmp("-technology", line, strlen("-technology"))) { 12910234Syasuko.eckert@amd.com sscanf(line, "-technology (u) %lf", &(F_sz_um)); 13010234Syasuko.eckert@amd.com F_sz_nm = F_sz_um * 1000; 13110234Syasuko.eckert@amd.com continue; 13210234Syasuko.eckert@amd.com } 13310152Satgutier@umich.edu 13410234Syasuko.eckert@amd.com if (!strncmp("-output/input", line, strlen("-output/input"))) { 13510234Syasuko.eckert@amd.com sscanf(line, "-output/input bus %[(:-~)*]%d", jk, &(out_w)); 13610234Syasuko.eckert@amd.com continue; 13710234Syasuko.eckert@amd.com } 13810152Satgutier@umich.edu 13910234Syasuko.eckert@amd.com if (!strncmp("-operating temperature", line, strlen("-operating temperature"))) { 14010234Syasuko.eckert@amd.com sscanf(line, "-operating temperature %[(:-~)*]%d", jk, &(temp)); 14110234Syasuko.eckert@amd.com continue; 14210234Syasuko.eckert@amd.com } 14310152Satgutier@umich.edu 14410234Syasuko.eckert@amd.com if (!strncmp("-cache type", line, strlen("-cache type"))) { 14510234Syasuko.eckert@amd.com sscanf(line, "-cache type%[^\"]\"%[^\"]\"", jk, temp_var); 14610152Satgutier@umich.edu 14710234Syasuko.eckert@amd.com if (!strncmp("cache", temp_var, sizeof("cache"))) { 14810234Syasuko.eckert@amd.com is_cache = true; 14910234Syasuko.eckert@amd.com } else { 15010234Syasuko.eckert@amd.com is_cache = false; 15110234Syasuko.eckert@amd.com } 15210152Satgutier@umich.edu 15310234Syasuko.eckert@amd.com if (!strncmp("main memory", temp_var, sizeof("main memory"))) { 15410234Syasuko.eckert@amd.com is_main_mem = true; 15510234Syasuko.eckert@amd.com } else { 15610234Syasuko.eckert@amd.com is_main_mem = false; 15710234Syasuko.eckert@amd.com } 15810152Satgutier@umich.edu 15910234Syasuko.eckert@amd.com if (!strncmp("cam", temp_var, sizeof("cam"))) { 16010234Syasuko.eckert@amd.com pure_cam = true; 16110234Syasuko.eckert@amd.com } else { 16210234Syasuko.eckert@amd.com pure_cam = false; 16310234Syasuko.eckert@amd.com } 16410152Satgutier@umich.edu 16510234Syasuko.eckert@amd.com if (!strncmp("ram", temp_var, sizeof("ram"))) { 16610234Syasuko.eckert@amd.com pure_ram = true; 16710234Syasuko.eckert@amd.com } else { 16810234Syasuko.eckert@amd.com if (!is_main_mem) 16910234Syasuko.eckert@amd.com pure_ram = false; 17010234Syasuko.eckert@amd.com else 17110234Syasuko.eckert@amd.com pure_ram = true; 17210234Syasuko.eckert@amd.com } 17310152Satgutier@umich.edu 17410234Syasuko.eckert@amd.com continue; 17510234Syasuko.eckert@amd.com } 17610234Syasuko.eckert@amd.com 17710234Syasuko.eckert@amd.com 17810234Syasuko.eckert@amd.com if (!strncmp("-tag size", line, strlen("-tag size"))) { 17910234Syasuko.eckert@amd.com sscanf(line, "-tag size%[^\"]\"%[^\"]\"", jk, temp_var); 18010234Syasuko.eckert@amd.com if (!strncmp("default", temp_var, sizeof("default"))) { 18110234Syasuko.eckert@amd.com specific_tag = false; 18210234Syasuko.eckert@amd.com tag_w = 42; /* the acutal value is calculated 18310152Satgutier@umich.edu * later based on the cache size, bank count, and associativity 18410152Satgutier@umich.edu */ 18510234Syasuko.eckert@amd.com } else { 18610234Syasuko.eckert@amd.com specific_tag = true; 18710234Syasuko.eckert@amd.com sscanf(line, "-tag size (b) %d", &(tag_w)); 18810234Syasuko.eckert@amd.com } 18910234Syasuko.eckert@amd.com continue; 19010234Syasuko.eckert@amd.com } 19110152Satgutier@umich.edu 19210234Syasuko.eckert@amd.com if (!strncmp("-access mode", line, strlen("-access mode"))) { 19310234Syasuko.eckert@amd.com sscanf(line, "-access %[^\"]\"%[^\"]\"", jk, temp_var); 19410234Syasuko.eckert@amd.com if (!strncmp("fast", temp_var, strlen("fast"))) { 19510234Syasuko.eckert@amd.com access_mode = 2; 19610234Syasuko.eckert@amd.com } else if (!strncmp("sequential", temp_var, strlen("sequential"))) { 19710234Syasuko.eckert@amd.com access_mode = 1; 19810234Syasuko.eckert@amd.com } else if (!strncmp("normal", temp_var, strlen("normal"))) { 19910234Syasuko.eckert@amd.com access_mode = 0; 20010234Syasuko.eckert@amd.com } else { 20110234Syasuko.eckert@amd.com cout << "ERROR: Invalid access mode!\n"; 20210234Syasuko.eckert@amd.com exit(0); 20310234Syasuko.eckert@amd.com } 20410234Syasuko.eckert@amd.com continue; 20510234Syasuko.eckert@amd.com } 20610152Satgutier@umich.edu 20710234Syasuko.eckert@amd.com if (!strncmp("-Data array cell type", line, 20810234Syasuko.eckert@amd.com strlen("-Data array cell type"))) { 20910234Syasuko.eckert@amd.com sscanf(line, "-Data array cell type %[^\"]\"%[^\"]\"", jk, temp_var); 21010152Satgutier@umich.edu 21110234Syasuko.eckert@amd.com if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { 21210234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type = 0; 21310234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { 21410234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type = 1; 21510234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { 21610234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type = 2; 21710234Syasuko.eckert@amd.com } else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { 21810234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type = 3; 21910234Syasuko.eckert@amd.com } else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { 22010234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type = 4; 22110234Syasuko.eckert@amd.com } else { 22210234Syasuko.eckert@amd.com cout << "ERROR: Invalid type!\n"; 22310234Syasuko.eckert@amd.com exit(0); 22410234Syasuko.eckert@amd.com } 22510234Syasuko.eckert@amd.com continue; 22610234Syasuko.eckert@amd.com } 22710152Satgutier@umich.edu 22810234Syasuko.eckert@amd.com if (!strncmp("-Data array peripheral type", line, strlen("-Data array peripheral type"))) { 22910234Syasuko.eckert@amd.com sscanf(line, "-Data array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var); 23010152Satgutier@umich.edu 23110234Syasuko.eckert@amd.com if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { 23210234Syasuko.eckert@amd.com data_arr_peri_global_tech_type = 0; 23310234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { 23410234Syasuko.eckert@amd.com data_arr_peri_global_tech_type = 1; 23510234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { 23610234Syasuko.eckert@amd.com data_arr_peri_global_tech_type = 2; 23710234Syasuko.eckert@amd.com } else { 23810234Syasuko.eckert@amd.com cout << "ERROR: Invalid type!\n"; 23910234Syasuko.eckert@amd.com exit(0); 24010234Syasuko.eckert@amd.com } 24110234Syasuko.eckert@amd.com continue; 24210234Syasuko.eckert@amd.com } 24310152Satgutier@umich.edu 24410234Syasuko.eckert@amd.com if (!strncmp("-Tag array cell type", line, strlen("-Tag array cell type"))) { 24510234Syasuko.eckert@amd.com sscanf(line, "-Tag array cell type %[^\"]\"%[^\"]\"", jk, temp_var); 24610152Satgutier@umich.edu 24710234Syasuko.eckert@amd.com if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { 24810234Syasuko.eckert@amd.com tag_arr_ram_cell_tech_type = 0; 24910234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { 25010234Syasuko.eckert@amd.com tag_arr_ram_cell_tech_type = 1; 25110234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { 25210234Syasuko.eckert@amd.com tag_arr_ram_cell_tech_type = 2; 25310234Syasuko.eckert@amd.com } else if (!strncmp("lp-dram", temp_var, strlen("lp-dram"))) { 25410234Syasuko.eckert@amd.com tag_arr_ram_cell_tech_type = 3; 25510234Syasuko.eckert@amd.com } else if (!strncmp("comm-dram", temp_var, strlen("comm-dram"))) { 25610234Syasuko.eckert@amd.com tag_arr_ram_cell_tech_type = 4; 25710234Syasuko.eckert@amd.com } else { 25810234Syasuko.eckert@amd.com cout << "ERROR: Invalid type!\n"; 25910234Syasuko.eckert@amd.com exit(0); 26010234Syasuko.eckert@amd.com } 26110234Syasuko.eckert@amd.com continue; 26210234Syasuko.eckert@amd.com } 26310152Satgutier@umich.edu 26410234Syasuko.eckert@amd.com if (!strncmp("-Tag array peripheral type", line, strlen("-Tag array peripheral type"))) { 26510234Syasuko.eckert@amd.com sscanf(line, "-Tag array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var); 26610152Satgutier@umich.edu 26710234Syasuko.eckert@amd.com if (!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) { 26810234Syasuko.eckert@amd.com tag_arr_peri_global_tech_type = 0; 26910234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) { 27010234Syasuko.eckert@amd.com tag_arr_peri_global_tech_type = 1; 27110234Syasuko.eckert@amd.com } else if (!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) { 27210234Syasuko.eckert@amd.com tag_arr_peri_global_tech_type = 2; 27310234Syasuko.eckert@amd.com } else { 27410234Syasuko.eckert@amd.com cout << "ERROR: Invalid type!\n"; 27510234Syasuko.eckert@amd.com exit(0); 27610234Syasuko.eckert@amd.com } 27710234Syasuko.eckert@amd.com continue; 27810234Syasuko.eckert@amd.com } 27910234Syasuko.eckert@amd.com if (!strncmp("-design", line, strlen("-design"))) { 28010234Syasuko.eckert@amd.com sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, 28110234Syasuko.eckert@amd.com &(delay_wt), &(dynamic_power_wt), 28210234Syasuko.eckert@amd.com &(leakage_power_wt), 28310234Syasuko.eckert@amd.com &(cycle_time_wt), &(area_wt)); 28410234Syasuko.eckert@amd.com continue; 28510234Syasuko.eckert@amd.com } 28610152Satgutier@umich.edu 28710234Syasuko.eckert@amd.com if (!strncmp("-deviate", line, strlen("-deviate"))) { 28810234Syasuko.eckert@amd.com sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, 28910234Syasuko.eckert@amd.com &(delay_dev), &(dynamic_power_dev), 29010234Syasuko.eckert@amd.com &(leakage_power_dev), 29110234Syasuko.eckert@amd.com &(cycle_time_dev), &(area_dev)); 29210234Syasuko.eckert@amd.com continue; 29310234Syasuko.eckert@amd.com } 29410152Satgutier@umich.edu 29510234Syasuko.eckert@amd.com if (!strncmp("-Optimize", line, strlen("-Optimize"))) { 29610234Syasuko.eckert@amd.com sscanf(line, "-Optimize %[^\"]\"%[^\"]\"", jk, temp_var); 29710152Satgutier@umich.edu 29810234Syasuko.eckert@amd.com if (!strncmp("ED^2", temp_var, strlen("ED^2"))) { 29910234Syasuko.eckert@amd.com ed = 2; 30010234Syasuko.eckert@amd.com } else if (!strncmp("ED", temp_var, strlen("ED"))) { 30110234Syasuko.eckert@amd.com ed = 1; 30210234Syasuko.eckert@amd.com } else { 30310234Syasuko.eckert@amd.com ed = 0; 30410234Syasuko.eckert@amd.com } 30510234Syasuko.eckert@amd.com } 30610152Satgutier@umich.edu 30710234Syasuko.eckert@amd.com if (!strncmp("-NUCAdesign", line, strlen("-NUCAdesign"))) { 30810234Syasuko.eckert@amd.com sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, 30910234Syasuko.eckert@amd.com &(delay_wt_nuca), &(dynamic_power_wt_nuca), 31010234Syasuko.eckert@amd.com &(leakage_power_wt_nuca), 31110234Syasuko.eckert@amd.com &(cycle_time_wt_nuca), &(area_wt_nuca)); 31210234Syasuko.eckert@amd.com continue; 31310234Syasuko.eckert@amd.com } 31410152Satgutier@umich.edu 31510234Syasuko.eckert@amd.com if (!strncmp("-NUCAdeviate", line, strlen("-NUCAdeviate"))) { 31610234Syasuko.eckert@amd.com sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk, 31710234Syasuko.eckert@amd.com &(delay_dev_nuca), &(dynamic_power_dev_nuca), 31810234Syasuko.eckert@amd.com &(leakage_power_dev_nuca), 31910234Syasuko.eckert@amd.com &(cycle_time_dev_nuca), &(area_dev_nuca)); 32010234Syasuko.eckert@amd.com continue; 32110234Syasuko.eckert@amd.com } 32210152Satgutier@umich.edu 32310234Syasuko.eckert@amd.com if (!strncmp("-Cache model", line, strlen("-cache model"))) { 32410234Syasuko.eckert@amd.com sscanf(line, "-Cache model %[^\"]\"%[^\"]\"", jk, temp_var); 32510152Satgutier@umich.edu 32610234Syasuko.eckert@amd.com if (!strncmp("UCA", temp_var, strlen("UCA"))) { 32710234Syasuko.eckert@amd.com nuca = 0; 32810234Syasuko.eckert@amd.com } else { 32910234Syasuko.eckert@amd.com nuca = 1; 33010234Syasuko.eckert@amd.com } 33110234Syasuko.eckert@amd.com continue; 33210234Syasuko.eckert@amd.com } 33310152Satgutier@umich.edu 33410234Syasuko.eckert@amd.com if (!strncmp("-NUCA bank", line, strlen("-NUCA bank"))) { 33510234Syasuko.eckert@amd.com sscanf(line, "-NUCA bank count %d", &(nuca_bank_count)); 33610152Satgutier@umich.edu 33710234Syasuko.eckert@amd.com if (nuca_bank_count != 0) { 33810234Syasuko.eckert@amd.com force_nuca_bank = 1; 33910234Syasuko.eckert@amd.com } 34010234Syasuko.eckert@amd.com continue; 34110234Syasuko.eckert@amd.com } 34210152Satgutier@umich.edu 34310234Syasuko.eckert@amd.com if (!strncmp("-Wire inside mat", line, strlen("-Wire inside mat"))) { 34410234Syasuko.eckert@amd.com sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); 34510152Satgutier@umich.edu 34610234Syasuko.eckert@amd.com if (!strncmp("global", temp_var, strlen("global"))) { 34710234Syasuko.eckert@amd.com wire_is_mat_type = 2; 34810234Syasuko.eckert@amd.com continue; 34910234Syasuko.eckert@amd.com } else if (!strncmp("local", temp_var, strlen("local"))) { 35010234Syasuko.eckert@amd.com wire_is_mat_type = 0; 35110234Syasuko.eckert@amd.com continue; 35210234Syasuko.eckert@amd.com } else { 35310234Syasuko.eckert@amd.com wire_is_mat_type = 1; 35410234Syasuko.eckert@amd.com continue; 35510234Syasuko.eckert@amd.com } 35610234Syasuko.eckert@amd.com } 35710152Satgutier@umich.edu 35810234Syasuko.eckert@amd.com if (!strncmp("-Wire outside mat", line, strlen("-Wire outside mat"))) { 35910234Syasuko.eckert@amd.com sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); 36010152Satgutier@umich.edu 36110234Syasuko.eckert@amd.com if (!strncmp("global", temp_var, strlen("global"))) { 36210234Syasuko.eckert@amd.com wire_os_mat_type = 2; 36310234Syasuko.eckert@amd.com } else { 36410234Syasuko.eckert@amd.com wire_os_mat_type = 1; 36510234Syasuko.eckert@amd.com } 36610234Syasuko.eckert@amd.com continue; 36710234Syasuko.eckert@amd.com } 36810152Satgutier@umich.edu 36910234Syasuko.eckert@amd.com if (!strncmp("-Interconnect projection", line, strlen("-Interconnect projection"))) { 37010234Syasuko.eckert@amd.com sscanf(line, "-Interconnect projection%[^\"]\"%[^\"]\"", jk, temp_var); 37110152Satgutier@umich.edu 37210234Syasuko.eckert@amd.com if (!strncmp("aggressive", temp_var, strlen("aggressive"))) { 37310234Syasuko.eckert@amd.com ic_proj_type = 0; 37410234Syasuko.eckert@amd.com } else { 37510234Syasuko.eckert@amd.com ic_proj_type = 1; 37610234Syasuko.eckert@amd.com } 37710234Syasuko.eckert@amd.com continue; 37810234Syasuko.eckert@amd.com } 37910152Satgutier@umich.edu 38010234Syasuko.eckert@amd.com if (!strncmp("-Wire signalling", line, strlen("-wire signalling"))) { 38110234Syasuko.eckert@amd.com sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var); 38210152Satgutier@umich.edu 38310234Syasuko.eckert@amd.com if (!strncmp("default", temp_var, strlen("default"))) { 38410234Syasuko.eckert@amd.com force_wiretype = 0; 38510234Syasuko.eckert@amd.com wt = Global; 38610234Syasuko.eckert@amd.com } else if (!(strncmp("Global_10", temp_var, strlen("Global_10")))) { 38710234Syasuko.eckert@amd.com force_wiretype = 1; 38810234Syasuko.eckert@amd.com wt = Global_10; 38910234Syasuko.eckert@amd.com } else if (!(strncmp("Global_20", temp_var, strlen("Global_20")))) { 39010234Syasuko.eckert@amd.com force_wiretype = 1; 39110234Syasuko.eckert@amd.com wt = Global_20; 39210234Syasuko.eckert@amd.com } else if (!(strncmp("Global_30", temp_var, strlen("Global_30")))) { 39310234Syasuko.eckert@amd.com force_wiretype = 1; 39410234Syasuko.eckert@amd.com wt = Global_30; 39510234Syasuko.eckert@amd.com } else if (!(strncmp("Global_5", temp_var, strlen("Global_5")))) { 39610234Syasuko.eckert@amd.com force_wiretype = 1; 39710234Syasuko.eckert@amd.com wt = Global_5; 39810234Syasuko.eckert@amd.com } else if (!(strncmp("Global", temp_var, strlen("Global")))) { 39910234Syasuko.eckert@amd.com force_wiretype = 1; 40010234Syasuko.eckert@amd.com wt = Global; 40110234Syasuko.eckert@amd.com } else { 40210234Syasuko.eckert@amd.com wt = Low_swing; 40310234Syasuko.eckert@amd.com force_wiretype = 1; 40410234Syasuko.eckert@amd.com } 40510234Syasuko.eckert@amd.com continue; 40610234Syasuko.eckert@amd.com } 40710152Satgutier@umich.edu 40810152Satgutier@umich.edu 40910152Satgutier@umich.edu 41010234Syasuko.eckert@amd.com if (!strncmp("-Core", line, strlen("-Core"))) { 41110234Syasuko.eckert@amd.com sscanf(line, "-Core count %d\n", &(cores)); 41210234Syasuko.eckert@amd.com if (cores > 16) { 41310234Syasuko.eckert@amd.com printf("No. of cores should be less than 16!\n"); 41410234Syasuko.eckert@amd.com } 41510234Syasuko.eckert@amd.com continue; 41610234Syasuko.eckert@amd.com } 41710152Satgutier@umich.edu 41810234Syasuko.eckert@amd.com if (!strncmp("-Cache level", line, strlen("-Cache level"))) { 41910234Syasuko.eckert@amd.com sscanf(line, "-Cache l%[^\"]\"%[^\"]\"", jk, temp_var); 42010234Syasuko.eckert@amd.com if (!strncmp("L2", temp_var, strlen("L2"))) { 42110234Syasuko.eckert@amd.com cache_level = 0; 42210234Syasuko.eckert@amd.com } else { 42310234Syasuko.eckert@amd.com cache_level = 1; 42410234Syasuko.eckert@amd.com } 42510234Syasuko.eckert@amd.com } 42610152Satgutier@umich.edu 42710234Syasuko.eckert@amd.com if (!strncmp("-Print level", line, strlen("-Print level"))) { 42810234Syasuko.eckert@amd.com sscanf(line, "-Print l%[^\"]\"%[^\"]\"", jk, temp_var); 42910234Syasuko.eckert@amd.com if (!strncmp("DETAILED", temp_var, strlen("DETAILED"))) { 43010234Syasuko.eckert@amd.com print_detail = 1; 43110234Syasuko.eckert@amd.com } else { 43210234Syasuko.eckert@amd.com print_detail = 0; 43310234Syasuko.eckert@amd.com } 43410234Syasuko.eckert@amd.com 43510234Syasuko.eckert@amd.com } 43610234Syasuko.eckert@amd.com if (!strncmp("-Add ECC", line, strlen("-Add ECC"))) { 43710234Syasuko.eckert@amd.com sscanf(line, "-Add ECC %[^\"]\"%[^\"]\"", jk, temp_var); 43810234Syasuko.eckert@amd.com if (!strncmp("true", temp_var, strlen("true"))) { 43910234Syasuko.eckert@amd.com add_ecc_b_ = true; 44010234Syasuko.eckert@amd.com } else { 44110234Syasuko.eckert@amd.com add_ecc_b_ = false; 44210234Syasuko.eckert@amd.com } 44310234Syasuko.eckert@amd.com } 44410234Syasuko.eckert@amd.com 44510234Syasuko.eckert@amd.com if (!strncmp("-Print input parameters", line, strlen("-Print input parameters"))) { 44610234Syasuko.eckert@amd.com sscanf(line, "-Print input %[^\"]\"%[^\"]\"", jk, temp_var); 44710234Syasuko.eckert@amd.com if (!strncmp("true", temp_var, strlen("true"))) { 44810234Syasuko.eckert@amd.com print_input_args = true; 44910234Syasuko.eckert@amd.com } else { 45010234Syasuko.eckert@amd.com print_input_args = false; 45110234Syasuko.eckert@amd.com } 45210234Syasuko.eckert@amd.com } 45310234Syasuko.eckert@amd.com 45410234Syasuko.eckert@amd.com if (!strncmp("-Force cache config", line, strlen("-Force cache config"))) { 45510234Syasuko.eckert@amd.com sscanf(line, "-Force cache %[^\"]\"%[^\"]\"", jk, temp_var); 45610234Syasuko.eckert@amd.com if (!strncmp("true", temp_var, strlen("true"))) { 45710234Syasuko.eckert@amd.com force_cache_config = true; 45810234Syasuko.eckert@amd.com } else { 45910234Syasuko.eckert@amd.com force_cache_config = false; 46010234Syasuko.eckert@amd.com } 46110234Syasuko.eckert@amd.com } 46210234Syasuko.eckert@amd.com 46310234Syasuko.eckert@amd.com if (!strncmp("-Ndbl", line, strlen("-Ndbl"))) { 46410234Syasuko.eckert@amd.com sscanf(line, "-Ndbl %d\n", &(ndbl)); 46510234Syasuko.eckert@amd.com continue; 46610234Syasuko.eckert@amd.com } 46710234Syasuko.eckert@amd.com if (!strncmp("-Ndwl", line, strlen("-Ndwl"))) { 46810234Syasuko.eckert@amd.com sscanf(line, "-Ndwl %d\n", &(ndwl)); 46910234Syasuko.eckert@amd.com continue; 47010234Syasuko.eckert@amd.com } 47110234Syasuko.eckert@amd.com if (!strncmp("-Nspd", line, strlen("-Nspd"))) { 47210234Syasuko.eckert@amd.com sscanf(line, "-Nspd %d\n", &(nspd)); 47310234Syasuko.eckert@amd.com continue; 47410234Syasuko.eckert@amd.com } 47510234Syasuko.eckert@amd.com if (!strncmp("-Ndsam1", line, strlen("-Ndsam1"))) { 47610234Syasuko.eckert@amd.com sscanf(line, "-Ndsam1 %d\n", &(ndsam1)); 47710234Syasuko.eckert@amd.com continue; 47810234Syasuko.eckert@amd.com } 47910234Syasuko.eckert@amd.com if (!strncmp("-Ndsam2", line, strlen("-Ndsam2"))) { 48010234Syasuko.eckert@amd.com sscanf(line, "-Ndsam2 %d\n", &(ndsam2)); 48110234Syasuko.eckert@amd.com continue; 48210234Syasuko.eckert@amd.com } 48310234Syasuko.eckert@amd.com if (!strncmp("-Ndcm", line, strlen("-Ndcm"))) { 48410234Syasuko.eckert@amd.com sscanf(line, "-Ndcm %d\n", &(ndcm)); 48510234Syasuko.eckert@amd.com continue; 48610234Syasuko.eckert@amd.com } 48710152Satgutier@umich.edu 48810152Satgutier@umich.edu } 48910234Syasuko.eckert@amd.com rpters_in_htree = true; 49010234Syasuko.eckert@amd.com fclose(fp); 49110152Satgutier@umich.edu} 49210152Satgutier@umich.edu 49310234Syasuko.eckert@amd.comvoid 49410234Syasuko.eckert@amd.comInputParameter::display_ip() { 49510234Syasuko.eckert@amd.com cout << "Cache size : " << cache_sz << endl; 49610234Syasuko.eckert@amd.com cout << "Block size : " << line_sz << endl; 49710234Syasuko.eckert@amd.com cout << "Associativity : " << assoc << endl; 49810234Syasuko.eckert@amd.com cout << "Read only ports : " << num_rd_ports << endl; 49910234Syasuko.eckert@amd.com cout << "Write only ports : " << num_wr_ports << endl; 50010234Syasuko.eckert@amd.com cout << "Read write ports : " << num_rw_ports << endl; 50110234Syasuko.eckert@amd.com cout << "Single ended read ports : " << num_se_rd_ports << endl; 50210234Syasuko.eckert@amd.com if (fully_assoc || pure_cam) { 50310234Syasuko.eckert@amd.com cout << "Search ports : " << num_search_ports << endl; 50410234Syasuko.eckert@amd.com } 50510234Syasuko.eckert@amd.com cout << "Cache banks (UCA) : " << nbanks << endl; 50610234Syasuko.eckert@amd.com cout << "Technology : " << F_sz_um << endl; 50710234Syasuko.eckert@amd.com cout << "Temperature : " << temp << endl; 50810234Syasuko.eckert@amd.com cout << "Tag size : " << tag_w << endl; 50910234Syasuko.eckert@amd.com if (is_cache) { 51010234Syasuko.eckert@amd.com cout << "array type : " << "Cache" << endl; 51110234Syasuko.eckert@amd.com } 51210234Syasuko.eckert@amd.com if (pure_ram) { 51310234Syasuko.eckert@amd.com cout << "array type : " << "Scratch RAM" << endl; 51410234Syasuko.eckert@amd.com } 51510234Syasuko.eckert@amd.com if (pure_cam) { 51610234Syasuko.eckert@amd.com cout << "array type : " << "CAM" << endl; 51710234Syasuko.eckert@amd.com } 51810234Syasuko.eckert@amd.com cout << "Model as memory : " << is_main_mem << endl; 51910234Syasuko.eckert@amd.com cout << "Access mode : " << access_mode << endl; 52010234Syasuko.eckert@amd.com cout << "Data array cell type : " << data_arr_ram_cell_tech_type << endl; 52110234Syasuko.eckert@amd.com cout << "Data array peripheral type : " << data_arr_peri_global_tech_type << endl; 52210234Syasuko.eckert@amd.com cout << "Tag array cell type : " << tag_arr_ram_cell_tech_type << endl; 52310234Syasuko.eckert@amd.com cout << "Tag array peripheral type : " << tag_arr_peri_global_tech_type << endl; 52410234Syasuko.eckert@amd.com cout << "Optimization target : " << ed << endl; 52510234Syasuko.eckert@amd.com cout << "Design objective (UCA wt) : " << delay_wt << " " 52610234Syasuko.eckert@amd.com << dynamic_power_wt << " " << leakage_power_wt << " " << cycle_time_wt 52710234Syasuko.eckert@amd.com << " " << area_wt << endl; 52810234Syasuko.eckert@amd.com cout << "Design objective (UCA dev) : " << delay_dev << " " 52910234Syasuko.eckert@amd.com << dynamic_power_dev << " " << leakage_power_dev << " " << cycle_time_dev 53010234Syasuko.eckert@amd.com << " " << area_dev << endl; 53110234Syasuko.eckert@amd.com if (nuca) { 53210234Syasuko.eckert@amd.com cout << "Cores : " << cores << endl; 53310152Satgutier@umich.edu 53410152Satgutier@umich.edu 53510234Syasuko.eckert@amd.com cout << "Design objective (NUCA wt) : " << delay_wt_nuca << " " 53610234Syasuko.eckert@amd.com << dynamic_power_wt_nuca << " " << leakage_power_wt_nuca << " " << cycle_time_wt_nuca 53710234Syasuko.eckert@amd.com << " " << area_wt_nuca << endl; 53810234Syasuko.eckert@amd.com cout << "Design objective (NUCA dev) : " << delay_dev_nuca << " " 53910234Syasuko.eckert@amd.com << dynamic_power_dev_nuca << " " << leakage_power_dev_nuca << " " << cycle_time_dev_nuca 54010234Syasuko.eckert@amd.com << " " << area_dev_nuca << endl; 54110152Satgutier@umich.edu } 54210234Syasuko.eckert@amd.com cout << "Cache model : " << nuca << endl; 54310234Syasuko.eckert@amd.com cout << "Nuca bank : " << nuca_bank_count << endl; 54410234Syasuko.eckert@amd.com cout << "Wire inside mat : " << wire_is_mat_type << endl; 54510234Syasuko.eckert@amd.com cout << "Wire outside mat : " << wire_os_mat_type << endl; 54610234Syasuko.eckert@amd.com cout << "Interconnect projection : " << ic_proj_type << endl; 54710234Syasuko.eckert@amd.com cout << "Wire signalling : " << force_wiretype << endl; 54810234Syasuko.eckert@amd.com cout << "Print level : " << print_detail << endl; 54910234Syasuko.eckert@amd.com cout << "ECC overhead : " << add_ecc_b_ << endl; 55010234Syasuko.eckert@amd.com cout << "Page size : " << page_sz_bits << endl; 55110234Syasuko.eckert@amd.com cout << "Burst length : " << burst_len << endl; 55210234Syasuko.eckert@amd.com cout << "Internal prefetch width : " << int_prefetch_w << endl; 55310234Syasuko.eckert@amd.com cout << "Force cache config : " << g_ip->force_cache_config << endl; 55410234Syasuko.eckert@amd.com if (g_ip->force_cache_config) { 55510234Syasuko.eckert@amd.com cout << "Ndwl : " << g_ip->ndwl << endl; 55610234Syasuko.eckert@amd.com cout << "Ndbl : " << g_ip->ndbl << endl; 55710234Syasuko.eckert@amd.com cout << "Nspd : " << g_ip->nspd << endl; 55810234Syasuko.eckert@amd.com cout << "Ndcm : " << g_ip->ndcm << endl; 55910234Syasuko.eckert@amd.com cout << "Ndsam1 : " << g_ip->ndsam1 << endl; 56010234Syasuko.eckert@amd.com cout << "Ndsam2 : " << g_ip->ndsam2 << endl; 56110234Syasuko.eckert@amd.com } 56210152Satgutier@umich.edu} 56310152Satgutier@umich.edu 56410152Satgutier@umich.edu 56510152Satgutier@umich.edu 56610234Syasuko.eckert@amd.compowerComponents operator+(const powerComponents & x, const powerComponents & y) { 56710234Syasuko.eckert@amd.com powerComponents z; 56810152Satgutier@umich.edu 56910234Syasuko.eckert@amd.com z.dynamic = x.dynamic + y.dynamic; 57010234Syasuko.eckert@amd.com z.leakage = x.leakage + y.leakage; 57110234Syasuko.eckert@amd.com z.gate_leakage = x.gate_leakage + y.gate_leakage; 57210234Syasuko.eckert@amd.com z.short_circuit = x.short_circuit + y.short_circuit; 57310234Syasuko.eckert@amd.com z.longer_channel_leakage = x.longer_channel_leakage + y.longer_channel_leakage; 57410152Satgutier@umich.edu 57510234Syasuko.eckert@amd.com return z; 57610152Satgutier@umich.edu} 57710152Satgutier@umich.edu 57810234Syasuko.eckert@amd.compowerComponents operator*(const powerComponents & x, double const * const y) { 57910234Syasuko.eckert@amd.com powerComponents z; 58010152Satgutier@umich.edu 58110234Syasuko.eckert@amd.com z.dynamic = x.dynamic * y[0]; 58210234Syasuko.eckert@amd.com z.leakage = x.leakage * y[1]; 58310234Syasuko.eckert@amd.com z.gate_leakage = x.gate_leakage * y[2]; 58410234Syasuko.eckert@amd.com z.short_circuit = x.short_circuit * y[3]; 58510234Syasuko.eckert@amd.com //longer channel leakage has the same behavior as normal leakage 58610234Syasuko.eckert@amd.com z.longer_channel_leakage = x.longer_channel_leakage * y[1]; 58710152Satgutier@umich.edu 58810234Syasuko.eckert@amd.com return z; 58910152Satgutier@umich.edu} 59010152Satgutier@umich.edu 59110152Satgutier@umich.edu 59210234Syasuko.eckert@amd.compowerDef operator+(const powerDef & x, const powerDef & y) { 59310234Syasuko.eckert@amd.com powerDef z; 59410152Satgutier@umich.edu 59510234Syasuko.eckert@amd.com z.readOp = x.readOp + y.readOp; 59610234Syasuko.eckert@amd.com z.writeOp = x.writeOp + y.writeOp; 59710234Syasuko.eckert@amd.com z.searchOp = x.searchOp + y.searchOp; 59810234Syasuko.eckert@amd.com return z; 59910152Satgutier@umich.edu} 60010152Satgutier@umich.edu 60110234Syasuko.eckert@amd.compowerDef operator*(const powerDef & x, double const * const y) { 60210234Syasuko.eckert@amd.com powerDef z; 60310152Satgutier@umich.edu 60410234Syasuko.eckert@amd.com z.readOp = x.readOp * y; 60510234Syasuko.eckert@amd.com z.writeOp = x.writeOp * y; 60610234Syasuko.eckert@amd.com z.searchOp = x.searchOp * y; 60710234Syasuko.eckert@amd.com return z; 60810152Satgutier@umich.edu} 60910152Satgutier@umich.edu 61010234Syasuko.eckert@amd.comuca_org_t cacti_interface(const string & infile_name) { 61110152Satgutier@umich.edu 61210234Syasuko.eckert@amd.com uca_org_t fin_res; 61310234Syasuko.eckert@amd.com //uca_org_t result; 61410234Syasuko.eckert@amd.com fin_res.valid = false; 61510152Satgutier@umich.edu 61610234Syasuko.eckert@amd.com g_ip = new InputParameter(); 61710234Syasuko.eckert@amd.com g_ip->parse_cfg(infile_name); 61810234Syasuko.eckert@amd.com if (!g_ip->error_checking(infile_name)) 61910234Syasuko.eckert@amd.com exit(0); 62010234Syasuko.eckert@amd.com if (g_ip->print_input_args) 62110234Syasuko.eckert@amd.com g_ip->display_ip(); 62210152Satgutier@umich.edu 62310234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 62410234Syasuko.eckert@amd.com Wire winit; // Do not delete this line. It initializes wires. 62510152Satgutier@umich.edu 62610152Satgutier@umich.edu 62710152Satgutier@umich.edu// For HighRadix Only 62810152Satgutier@umich.edu// //// Wire wirea(g_ip->wt, 1000); 62910152Satgutier@umich.edu// //// wirea.print_wire(); 63010152Satgutier@umich.edu// //// cout << "Wire Area " << wirea.area.get_area() << " sq. u" << endl; 63110152Satgutier@umich.edu// // winit.print_wire(); 63210152Satgutier@umich.edu// // 63310152Satgutier@umich.edu// HighRadix *hr; 63410152Satgutier@umich.edu// hr = new HighRadix(); 63510152Satgutier@umich.edu// hr->compute_power(); 63610152Satgutier@umich.edu// hr->print_router(); 63710152Satgutier@umich.edu// exit(0); 63810152Satgutier@umich.edu// 63910152Satgutier@umich.edu// double sub_switch_sz = 2; 64010152Satgutier@umich.edu// double rows = 32; 64110152Satgutier@umich.edu// for (int i=0; i<6; i++) { 64210152Satgutier@umich.edu// sub_switch_sz = pow(2, i); 64310152Satgutier@umich.edu// rows = 64/sub_switch_sz; 64410152Satgutier@umich.edu// hr = new HighRadix(sub_switch_sz, rows, .8/* freq */, 64, 2, 64, 0.7); 64510152Satgutier@umich.edu// hr->compute_power(); 64610152Satgutier@umich.edu// hr->print_router(); 64710152Satgutier@umich.edu// delete hr; 64810152Satgutier@umich.edu// } 64910152Satgutier@umich.edu// // HighRadix yarc; 65010152Satgutier@umich.edu// // yarc.compute_power(); 65110152Satgutier@umich.edu// // yarc.print_router(); 65210152Satgutier@umich.edu// winit.print_wire(); 65310152Satgutier@umich.edu// exit(0); 65410152Satgutier@umich.edu// For HighRadix Only End 65510152Satgutier@umich.edu 65610234Syasuko.eckert@amd.com if (g_ip->nuca == 1) { 65710234Syasuko.eckert@amd.com Nuca n(&g_tp.peri_global); 65810234Syasuko.eckert@amd.com n.sim_nuca(); 65910234Syasuko.eckert@amd.com } 66010234Syasuko.eckert@amd.com g_ip->display_ip(); 66110234Syasuko.eckert@amd.com solve(&fin_res); 66210152Satgutier@umich.edu 66310234Syasuko.eckert@amd.com output_UCA(&fin_res); 66410234Syasuko.eckert@amd.com output_data_csv(fin_res); 66510152Satgutier@umich.edu 66610234Syasuko.eckert@amd.com delete (g_ip); 66710234Syasuko.eckert@amd.com return fin_res; 66810152Satgutier@umich.edu} 66910152Satgutier@umich.edu 67010152Satgutier@umich.edu//cacti6.5's plain interface, please keep !!! 67110152Satgutier@umich.eduuca_org_t cacti_interface( 67210152Satgutier@umich.edu int cache_size, 67310152Satgutier@umich.edu int line_size, 67410152Satgutier@umich.edu int associativity, 67510152Satgutier@umich.edu int rw_ports, 67610152Satgutier@umich.edu int excl_read_ports, 67710152Satgutier@umich.edu int excl_write_ports, 67810152Satgutier@umich.edu int single_ended_read_ports, 67910152Satgutier@umich.edu int banks, 68010152Satgutier@umich.edu double tech_node, // in nm 68110152Satgutier@umich.edu int page_sz, 68210152Satgutier@umich.edu int burst_length, 68310152Satgutier@umich.edu int pre_width, 68410152Satgutier@umich.edu int output_width, 68510152Satgutier@umich.edu int specific_tag, 68610152Satgutier@umich.edu int tag_width, 68710152Satgutier@umich.edu int access_mode, //0 normal, 1 seq, 2 fast 68810152Satgutier@umich.edu int cache, //scratch ram or cache 68910152Satgutier@umich.edu int main_mem, 69010152Satgutier@umich.edu int obj_func_delay, 69110152Satgutier@umich.edu int obj_func_dynamic_power, 69210152Satgutier@umich.edu int obj_func_leakage_power, 69310152Satgutier@umich.edu int obj_func_area, 69410152Satgutier@umich.edu int obj_func_cycle_time, 69510152Satgutier@umich.edu int dev_func_delay, 69610152Satgutier@umich.edu int dev_func_dynamic_power, 69710152Satgutier@umich.edu int dev_func_leakage_power, 69810152Satgutier@umich.edu int dev_func_area, 69910152Satgutier@umich.edu int dev_func_cycle_time, 70010152Satgutier@umich.edu int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate 70110152Satgutier@umich.edu int temp, 70210152Satgutier@umich.edu int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing 70310152Satgutier@umich.edu int data_arr_ram_cell_tech_flavor_in, // 0-4 70410152Satgutier@umich.edu int data_arr_peri_global_tech_flavor_in, 70510152Satgutier@umich.edu int tag_arr_ram_cell_tech_flavor_in, 70610152Satgutier@umich.edu int tag_arr_peri_global_tech_flavor_in, 70710152Satgutier@umich.edu int interconnect_projection_type_in, // 0 - aggressive, 1 - normal 70810152Satgutier@umich.edu int wire_inside_mat_type_in, 70910152Satgutier@umich.edu int wire_outside_mat_type_in, 71010152Satgutier@umich.edu int is_nuca, // 0 - UCA, 1 - NUCA 71110152Satgutier@umich.edu int core_count, 71210152Satgutier@umich.edu int cache_level, // 0 - L2, 1 - L3 71310152Satgutier@umich.edu int nuca_bank_count, 71410152Satgutier@umich.edu int nuca_obj_func_delay, 71510152Satgutier@umich.edu int nuca_obj_func_dynamic_power, 71610152Satgutier@umich.edu int nuca_obj_func_leakage_power, 71710152Satgutier@umich.edu int nuca_obj_func_area, 71810152Satgutier@umich.edu int nuca_obj_func_cycle_time, 71910152Satgutier@umich.edu int nuca_dev_func_delay, 72010152Satgutier@umich.edu int nuca_dev_func_dynamic_power, 72110152Satgutier@umich.edu int nuca_dev_func_leakage_power, 72210152Satgutier@umich.edu int nuca_dev_func_area, 72310152Satgutier@umich.edu int nuca_dev_func_cycle_time, 72410152Satgutier@umich.edu int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported 72510234Syasuko.eckert@amd.com int p_input) { 72610234Syasuko.eckert@amd.com g_ip = new InputParameter(); 72710234Syasuko.eckert@amd.com g_ip->add_ecc_b_ = true; 72810152Satgutier@umich.edu 72910234Syasuko.eckert@amd.com g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; 73010234Syasuko.eckert@amd.com g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; 73110234Syasuko.eckert@amd.com g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; 73210234Syasuko.eckert@amd.com g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; 73310152Satgutier@umich.edu 73410234Syasuko.eckert@amd.com g_ip->ic_proj_type = interconnect_projection_type_in; 73510234Syasuko.eckert@amd.com g_ip->wire_is_mat_type = wire_inside_mat_type_in; 73610234Syasuko.eckert@amd.com g_ip->wire_os_mat_type = wire_outside_mat_type_in; 73710234Syasuko.eckert@amd.com g_ip->burst_len = burst_length; 73810234Syasuko.eckert@amd.com g_ip->int_prefetch_w = pre_width; 73910234Syasuko.eckert@amd.com g_ip->page_sz_bits = page_sz; 74010152Satgutier@umich.edu 74110234Syasuko.eckert@amd.com g_ip->cache_sz = cache_size; 74210234Syasuko.eckert@amd.com g_ip->line_sz = line_size; 74310234Syasuko.eckert@amd.com g_ip->assoc = associativity; 74410234Syasuko.eckert@amd.com g_ip->nbanks = banks; 74510234Syasuko.eckert@amd.com g_ip->out_w = output_width; 74610234Syasuko.eckert@amd.com g_ip->specific_tag = specific_tag; 74710234Syasuko.eckert@amd.com if (tag_width == 0) { 74810234Syasuko.eckert@amd.com g_ip->tag_w = 42; 74910234Syasuko.eckert@amd.com } else { 75010234Syasuko.eckert@amd.com g_ip->tag_w = tag_width; 75110234Syasuko.eckert@amd.com } 75210152Satgutier@umich.edu 75310234Syasuko.eckert@amd.com g_ip->access_mode = access_mode; 75410234Syasuko.eckert@amd.com g_ip->delay_wt = obj_func_delay; 75510234Syasuko.eckert@amd.com g_ip->dynamic_power_wt = obj_func_dynamic_power; 75610234Syasuko.eckert@amd.com g_ip->leakage_power_wt = obj_func_leakage_power; 75710234Syasuko.eckert@amd.com g_ip->area_wt = obj_func_area; 75810234Syasuko.eckert@amd.com g_ip->cycle_time_wt = obj_func_cycle_time; 75910234Syasuko.eckert@amd.com g_ip->delay_dev = dev_func_delay; 76010234Syasuko.eckert@amd.com g_ip->dynamic_power_dev = dev_func_dynamic_power; 76110234Syasuko.eckert@amd.com g_ip->leakage_power_dev = dev_func_leakage_power; 76210234Syasuko.eckert@amd.com g_ip->area_dev = dev_func_area; 76310234Syasuko.eckert@amd.com g_ip->cycle_time_dev = dev_func_cycle_time; 76410234Syasuko.eckert@amd.com g_ip->ed = ed_ed2_none; 76510152Satgutier@umich.edu 76610234Syasuko.eckert@amd.com switch (wt) { 76710152Satgutier@umich.edu case (0): 76810234Syasuko.eckert@amd.com g_ip->force_wiretype = 0; 76910234Syasuko.eckert@amd.com g_ip->wt = Global; 77010234Syasuko.eckert@amd.com break; 77110152Satgutier@umich.edu case (1): 77210234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 77310234Syasuko.eckert@amd.com g_ip->wt = Global; 77410234Syasuko.eckert@amd.com break; 77510152Satgutier@umich.edu case (2): 77610234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 77710234Syasuko.eckert@amd.com g_ip->wt = Global_5; 77810234Syasuko.eckert@amd.com break; 77910152Satgutier@umich.edu case (3): 78010234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 78110234Syasuko.eckert@amd.com g_ip->wt = Global_10; 78210234Syasuko.eckert@amd.com break; 78310152Satgutier@umich.edu case (4): 78410234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 78510234Syasuko.eckert@amd.com g_ip->wt = Global_20; 78610234Syasuko.eckert@amd.com break; 78710152Satgutier@umich.edu case (5): 78810234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 78910234Syasuko.eckert@amd.com g_ip->wt = Global_30; 79010234Syasuko.eckert@amd.com break; 79110152Satgutier@umich.edu case (6): 79210234Syasuko.eckert@amd.com g_ip->force_wiretype = 1; 79310234Syasuko.eckert@amd.com g_ip->wt = Low_swing; 79410234Syasuko.eckert@amd.com break; 79510152Satgutier@umich.edu default: 79610234Syasuko.eckert@amd.com cout << "Unknown wire type!\n"; 79710234Syasuko.eckert@amd.com exit(0); 79810234Syasuko.eckert@amd.com } 79910152Satgutier@umich.edu 80010234Syasuko.eckert@amd.com g_ip->delay_wt_nuca = nuca_obj_func_delay; 80110234Syasuko.eckert@amd.com g_ip->dynamic_power_wt_nuca = nuca_obj_func_dynamic_power; 80210234Syasuko.eckert@amd.com g_ip->leakage_power_wt_nuca = nuca_obj_func_leakage_power; 80310234Syasuko.eckert@amd.com g_ip->area_wt_nuca = nuca_obj_func_area; 80410234Syasuko.eckert@amd.com g_ip->cycle_time_wt_nuca = nuca_obj_func_cycle_time; 80510234Syasuko.eckert@amd.com g_ip->delay_dev_nuca = dev_func_delay; 80610234Syasuko.eckert@amd.com g_ip->dynamic_power_dev_nuca = nuca_dev_func_dynamic_power; 80710234Syasuko.eckert@amd.com g_ip->leakage_power_dev_nuca = nuca_dev_func_leakage_power; 80810234Syasuko.eckert@amd.com g_ip->area_dev_nuca = nuca_dev_func_area; 80910234Syasuko.eckert@amd.com g_ip->cycle_time_dev_nuca = nuca_dev_func_cycle_time; 81010234Syasuko.eckert@amd.com g_ip->nuca = is_nuca; 81110234Syasuko.eckert@amd.com g_ip->nuca_bank_count = nuca_bank_count; 81210234Syasuko.eckert@amd.com if (nuca_bank_count > 0) { 81310234Syasuko.eckert@amd.com g_ip->force_nuca_bank = 1; 81410234Syasuko.eckert@amd.com } 81510234Syasuko.eckert@amd.com g_ip->cores = core_count; 81610234Syasuko.eckert@amd.com g_ip->cache_level = cache_level; 81710152Satgutier@umich.edu 81810234Syasuko.eckert@amd.com g_ip->temp = temp; 81910152Satgutier@umich.edu 82010234Syasuko.eckert@amd.com g_ip->F_sz_nm = tech_node; 82110234Syasuko.eckert@amd.com g_ip->F_sz_um = tech_node / 1000; 82210234Syasuko.eckert@amd.com g_ip->is_main_mem = (main_mem != 0) ? true : false; 82310234Syasuko.eckert@amd.com g_ip->is_cache = (cache != 0) ? true : false; 82410234Syasuko.eckert@amd.com g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; 82510152Satgutier@umich.edu 82610234Syasuko.eckert@amd.com g_ip->num_rw_ports = rw_ports; 82710234Syasuko.eckert@amd.com g_ip->num_rd_ports = excl_read_ports; 82810234Syasuko.eckert@amd.com g_ip->num_wr_ports = excl_write_ports; 82910234Syasuko.eckert@amd.com g_ip->num_se_rd_ports = single_ended_read_ports; 83010234Syasuko.eckert@amd.com g_ip->print_detail = 1; 83110234Syasuko.eckert@amd.com g_ip->nuca = 0; 83210152Satgutier@umich.edu 83310234Syasuko.eckert@amd.com g_ip->wt = Global_5; 83410234Syasuko.eckert@amd.com g_ip->force_cache_config = false; 83510234Syasuko.eckert@amd.com g_ip->force_wiretype = false; 83610234Syasuko.eckert@amd.com g_ip->print_input_args = p_input; 83710152Satgutier@umich.edu 83810152Satgutier@umich.edu 83910234Syasuko.eckert@amd.com uca_org_t fin_res; 84010234Syasuko.eckert@amd.com fin_res.valid = false; 84110152Satgutier@umich.edu 84210234Syasuko.eckert@amd.com if (g_ip->error_checking() == false) exit(0); 84310234Syasuko.eckert@amd.com if (g_ip->print_input_args) 84410234Syasuko.eckert@amd.com g_ip->display_ip(); 84510234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 84610234Syasuko.eckert@amd.com Wire winit; // Do not delete this line. It initializes wires. 84710152Satgutier@umich.edu 84810234Syasuko.eckert@amd.com if (g_ip->nuca == 1) { 84910234Syasuko.eckert@amd.com Nuca n(&g_tp.peri_global); 85010234Syasuko.eckert@amd.com n.sim_nuca(); 85110234Syasuko.eckert@amd.com } 85210234Syasuko.eckert@amd.com solve(&fin_res); 85310152Satgutier@umich.edu 85410234Syasuko.eckert@amd.com output_UCA(&fin_res); 85510152Satgutier@umich.edu 85610234Syasuko.eckert@amd.com delete (g_ip); 85710234Syasuko.eckert@amd.com return fin_res; 85810152Satgutier@umich.edu} 85910152Satgutier@umich.edu 86010152Satgutier@umich.edu//McPAT's plain interface, please keep !!! 86110152Satgutier@umich.eduuca_org_t cacti_interface( 86210152Satgutier@umich.edu int cache_size, 86310152Satgutier@umich.edu int line_size, 86410152Satgutier@umich.edu int associativity, 86510152Satgutier@umich.edu int rw_ports, 86610152Satgutier@umich.edu int excl_read_ports,// para5 86710152Satgutier@umich.edu int excl_write_ports, 86810152Satgutier@umich.edu int single_ended_read_ports, 86910152Satgutier@umich.edu int search_ports, 87010152Satgutier@umich.edu int banks, 87110152Satgutier@umich.edu double tech_node,//para10 87210152Satgutier@umich.edu int output_width, 87310152Satgutier@umich.edu int specific_tag, 87410152Satgutier@umich.edu int tag_width, 87510152Satgutier@umich.edu int access_mode, 87610152Satgutier@umich.edu int cache, //para15 87710152Satgutier@umich.edu int main_mem, 87810152Satgutier@umich.edu int obj_func_delay, 87910152Satgutier@umich.edu int obj_func_dynamic_power, 88010152Satgutier@umich.edu int obj_func_leakage_power, 88110152Satgutier@umich.edu int obj_func_cycle_time, //para20 88210152Satgutier@umich.edu int obj_func_area, 88310152Satgutier@umich.edu int dev_func_delay, 88410152Satgutier@umich.edu int dev_func_dynamic_power, 88510152Satgutier@umich.edu int dev_func_leakage_power, 88610152Satgutier@umich.edu int dev_func_area, //para25 88710152Satgutier@umich.edu int dev_func_cycle_time, 88810152Satgutier@umich.edu int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate 88910152Satgutier@umich.edu int temp, 89010152Satgutier@umich.edu int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing 89110152Satgutier@umich.edu int data_arr_ram_cell_tech_flavor_in,//para30 89210152Satgutier@umich.edu int data_arr_peri_global_tech_flavor_in, 89310152Satgutier@umich.edu int tag_arr_ram_cell_tech_flavor_in, 89410152Satgutier@umich.edu int tag_arr_peri_global_tech_flavor_in, 89510152Satgutier@umich.edu int interconnect_projection_type_in, 89610152Satgutier@umich.edu int wire_inside_mat_type_in,//para35 89710152Satgutier@umich.edu int wire_outside_mat_type_in, 89810152Satgutier@umich.edu int REPEATERS_IN_HTREE_SEGMENTS_in, 89910152Satgutier@umich.edu int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, 90010152Satgutier@umich.edu int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, 90110152Satgutier@umich.edu int PAGE_SIZE_BITS_in,//para40 90210152Satgutier@umich.edu int BURST_LENGTH_in, 90310152Satgutier@umich.edu int INTERNAL_PREFETCH_WIDTH_in, 90410152Satgutier@umich.edu int force_wiretype, 90510152Satgutier@umich.edu int wiretype, 90610152Satgutier@umich.edu int force_config,//para45 90710152Satgutier@umich.edu int ndwl, 90810152Satgutier@umich.edu int ndbl, 90910152Satgutier@umich.edu int nspd, 91010152Satgutier@umich.edu int ndcm, 91110152Satgutier@umich.edu int ndsam1,//para50 91210152Satgutier@umich.edu int ndsam2, 91310234Syasuko.eckert@amd.com int ecc) { 91410234Syasuko.eckert@amd.com g_ip = new InputParameter(); 91510152Satgutier@umich.edu 91610234Syasuko.eckert@amd.com uca_org_t fin_res; 91710234Syasuko.eckert@amd.com fin_res.valid = false; 91810152Satgutier@umich.edu 91910234Syasuko.eckert@amd.com g_ip->data_arr_ram_cell_tech_type = data_arr_ram_cell_tech_flavor_in; 92010234Syasuko.eckert@amd.com g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in; 92110234Syasuko.eckert@amd.com g_ip->tag_arr_ram_cell_tech_type = tag_arr_ram_cell_tech_flavor_in; 92210234Syasuko.eckert@amd.com g_ip->tag_arr_peri_global_tech_type = tag_arr_peri_global_tech_flavor_in; 92310152Satgutier@umich.edu 92410234Syasuko.eckert@amd.com g_ip->ic_proj_type = interconnect_projection_type_in; 92510234Syasuko.eckert@amd.com g_ip->wire_is_mat_type = wire_inside_mat_type_in; 92610234Syasuko.eckert@amd.com g_ip->wire_os_mat_type = wire_outside_mat_type_in; 92710234Syasuko.eckert@amd.com g_ip->burst_len = BURST_LENGTH_in; 92810234Syasuko.eckert@amd.com g_ip->int_prefetch_w = INTERNAL_PREFETCH_WIDTH_in; 92910234Syasuko.eckert@amd.com g_ip->page_sz_bits = PAGE_SIZE_BITS_in; 93010152Satgutier@umich.edu 93110234Syasuko.eckert@amd.com g_ip->cache_sz = cache_size; 93210234Syasuko.eckert@amd.com g_ip->line_sz = line_size; 93310234Syasuko.eckert@amd.com g_ip->assoc = associativity; 93410234Syasuko.eckert@amd.com g_ip->nbanks = banks; 93510234Syasuko.eckert@amd.com g_ip->out_w = output_width; 93610234Syasuko.eckert@amd.com g_ip->specific_tag = specific_tag; 93710234Syasuko.eckert@amd.com if (specific_tag == 0) { 93810234Syasuko.eckert@amd.com g_ip->tag_w = 42; 93910234Syasuko.eckert@amd.com } else { 94010234Syasuko.eckert@amd.com g_ip->tag_w = tag_width; 94110234Syasuko.eckert@amd.com } 94210152Satgutier@umich.edu 94310234Syasuko.eckert@amd.com g_ip->access_mode = access_mode; 94410234Syasuko.eckert@amd.com g_ip->delay_wt = obj_func_delay; 94510234Syasuko.eckert@amd.com g_ip->dynamic_power_wt = obj_func_dynamic_power; 94610234Syasuko.eckert@amd.com g_ip->leakage_power_wt = obj_func_leakage_power; 94710234Syasuko.eckert@amd.com g_ip->area_wt = obj_func_area; 94810234Syasuko.eckert@amd.com g_ip->cycle_time_wt = obj_func_cycle_time; 94910234Syasuko.eckert@amd.com g_ip->delay_dev = dev_func_delay; 95010234Syasuko.eckert@amd.com g_ip->dynamic_power_dev = dev_func_dynamic_power; 95110234Syasuko.eckert@amd.com g_ip->leakage_power_dev = dev_func_leakage_power; 95210234Syasuko.eckert@amd.com g_ip->area_dev = dev_func_area; 95310234Syasuko.eckert@amd.com g_ip->cycle_time_dev = dev_func_cycle_time; 95410234Syasuko.eckert@amd.com g_ip->temp = temp; 95510234Syasuko.eckert@amd.com g_ip->ed = ed_ed2_none; 95610152Satgutier@umich.edu 95710234Syasuko.eckert@amd.com g_ip->F_sz_nm = tech_node; 95810234Syasuko.eckert@amd.com g_ip->F_sz_um = tech_node / 1000; 95910234Syasuko.eckert@amd.com g_ip->is_main_mem = (main_mem != 0) ? true : false; 96010234Syasuko.eckert@amd.com g_ip->is_cache = (cache == 1) ? true : false; 96110234Syasuko.eckert@amd.com g_ip->pure_ram = (cache == 0) ? true : false; 96210234Syasuko.eckert@amd.com g_ip->pure_cam = (cache == 2) ? true : false; 96310234Syasuko.eckert@amd.com g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false; 96410234Syasuko.eckert@amd.com g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in; 96510234Syasuko.eckert@amd.com g_ip->broadcast_addr_din_over_ver_htrees = BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in; 96610152Satgutier@umich.edu 96710234Syasuko.eckert@amd.com g_ip->num_rw_ports = rw_ports; 96810234Syasuko.eckert@amd.com g_ip->num_rd_ports = excl_read_ports; 96910234Syasuko.eckert@amd.com g_ip->num_wr_ports = excl_write_ports; 97010234Syasuko.eckert@amd.com g_ip->num_se_rd_ports = single_ended_read_ports; 97110234Syasuko.eckert@amd.com g_ip->num_search_ports = search_ports; 97210152Satgutier@umich.edu 97310234Syasuko.eckert@amd.com g_ip->print_detail = 1; 97410234Syasuko.eckert@amd.com g_ip->nuca = 0; 97510152Satgutier@umich.edu 97610234Syasuko.eckert@amd.com if (force_wiretype == 0) { 97710234Syasuko.eckert@amd.com g_ip->wt = Global; 97810234Syasuko.eckert@amd.com g_ip->force_wiretype = false; 97910234Syasuko.eckert@amd.com } else { 98010234Syasuko.eckert@amd.com g_ip->force_wiretype = true; 98110234Syasuko.eckert@amd.com if (wiretype == 10) { 98210234Syasuko.eckert@amd.com g_ip->wt = Global_10; 98310234Syasuko.eckert@amd.com } 98410234Syasuko.eckert@amd.com if (wiretype == 20) { 98510234Syasuko.eckert@amd.com g_ip->wt = Global_20; 98610234Syasuko.eckert@amd.com } 98710234Syasuko.eckert@amd.com if (wiretype == 30) { 98810234Syasuko.eckert@amd.com g_ip->wt = Global_30; 98910234Syasuko.eckert@amd.com } 99010234Syasuko.eckert@amd.com if (wiretype == 5) { 99110234Syasuko.eckert@amd.com g_ip->wt = Global_5; 99210234Syasuko.eckert@amd.com } 99310234Syasuko.eckert@amd.com if (wiretype == 0) { 99410234Syasuko.eckert@amd.com g_ip->wt = Low_swing; 99510234Syasuko.eckert@amd.com } 99610152Satgutier@umich.edu } 99710234Syasuko.eckert@amd.com //g_ip->wt = Global_5; 99810234Syasuko.eckert@amd.com if (force_config == 0) { 99910234Syasuko.eckert@amd.com g_ip->force_cache_config = false; 100010234Syasuko.eckert@amd.com } else { 100110152Satgutier@umich.edu g_ip->force_cache_config = true; 100210234Syasuko.eckert@amd.com g_ip->ndbl = ndbl; 100310234Syasuko.eckert@amd.com g_ip->ndwl = ndwl; 100410234Syasuko.eckert@amd.com g_ip->nspd = nspd; 100510234Syasuko.eckert@amd.com g_ip->ndcm = ndcm; 100610234Syasuko.eckert@amd.com g_ip->ndsam1 = ndsam1; 100710234Syasuko.eckert@amd.com g_ip->ndsam2 = ndsam2; 100810152Satgutier@umich.edu 100910152Satgutier@umich.edu 101010152Satgutier@umich.edu } 101110152Satgutier@umich.edu 101210234Syasuko.eckert@amd.com if (ecc == 0) { 101310234Syasuko.eckert@amd.com g_ip->add_ecc_b_ = false; 101410234Syasuko.eckert@amd.com } else { 101510234Syasuko.eckert@amd.com g_ip->add_ecc_b_ = true; 101610234Syasuko.eckert@amd.com } 101710152Satgutier@umich.edu 101810152Satgutier@umich.edu 101910234Syasuko.eckert@amd.com if (!g_ip->error_checking()) 102010234Syasuko.eckert@amd.com exit(0); 102110152Satgutier@umich.edu 102210234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 102310234Syasuko.eckert@amd.com Wire winit; // Do not delete this line. It initializes wires. 102410152Satgutier@umich.edu 102510234Syasuko.eckert@amd.com g_ip->display_ip(); 102610234Syasuko.eckert@amd.com solve(&fin_res); 102710234Syasuko.eckert@amd.com output_UCA(&fin_res); 102810234Syasuko.eckert@amd.com output_data_csv(fin_res); 102910234Syasuko.eckert@amd.com delete (g_ip); 103010152Satgutier@umich.edu 103110234Syasuko.eckert@amd.com return fin_res; 103210152Satgutier@umich.edu} 103310152Satgutier@umich.edu 103410152Satgutier@umich.edu 103510152Satgutier@umich.edu 103610234Syasuko.eckert@amd.combool InputParameter::error_checking(string name) { 103710234Syasuko.eckert@amd.com int A; 103810234Syasuko.eckert@amd.com bool seq_access = false; 103910234Syasuko.eckert@amd.com fast_access = true; 104010152Satgutier@umich.edu 104110234Syasuko.eckert@amd.com switch (access_mode) { 104210152Satgutier@umich.edu case 0: 104310234Syasuko.eckert@amd.com seq_access = false; 104410234Syasuko.eckert@amd.com fast_access = false; 104510234Syasuko.eckert@amd.com break; 104610152Satgutier@umich.edu case 1: 104710234Syasuko.eckert@amd.com seq_access = true; 104810234Syasuko.eckert@amd.com fast_access = false; 104910234Syasuko.eckert@amd.com break; 105010152Satgutier@umich.edu case 2: 105110234Syasuko.eckert@amd.com seq_access = false; 105210234Syasuko.eckert@amd.com fast_access = true; 105310234Syasuko.eckert@amd.com break; 105410234Syasuko.eckert@amd.com } 105510152Satgutier@umich.edu 105610234Syasuko.eckert@amd.com if (is_main_mem) { 105710234Syasuko.eckert@amd.com if (ic_proj_type == 0) { 105810234Syasuko.eckert@amd.com cerr << name 105910234Syasuko.eckert@amd.com << ": DRAM model supports only conservative interconnect " 106010234Syasuko.eckert@amd.com << "projection but is set to aggressive!\n\n"; 106110234Syasuko.eckert@amd.com return false; 106210234Syasuko.eckert@amd.com } 106310152Satgutier@umich.edu } 106410152Satgutier@umich.edu 106510152Satgutier@umich.edu 106610234Syasuko.eckert@amd.com uint32_t B = line_sz; 106710152Satgutier@umich.edu 106810234Syasuko.eckert@amd.com if (B < 1) { 106910234Syasuko.eckert@amd.com cerr << name << ": Block size must be >= 1, but is set to " << B 107010234Syasuko.eckert@amd.com << endl; 107110234Syasuko.eckert@amd.com return false; 107210234Syasuko.eckert@amd.com } else if (B*8 < out_w) { 107310234Syasuko.eckert@amd.com cerr << name << ": Block size must be at least " << out_w / 8 107410234Syasuko.eckert@amd.com << ", but is set to " << B << endl; 107510234Syasuko.eckert@amd.com return false; 107610234Syasuko.eckert@amd.com } 107710152Satgutier@umich.edu 107810234Syasuko.eckert@amd.com if (F_sz_um <= 0) { 107910234Syasuko.eckert@amd.com cerr << name << ": Feature size must be > 0, but is set to " 108010234Syasuko.eckert@amd.com << F_sz_um << endl; 108110234Syasuko.eckert@amd.com return false; 108210234Syasuko.eckert@amd.com } else if (F_sz_um > 0.091) { 108310234Syasuko.eckert@amd.com cerr << name << ": Feature size must be <= 90 nm, but is set to " 108410234Syasuko.eckert@amd.com << F_sz_um << endl; 108510234Syasuko.eckert@amd.com return false; 108610234Syasuko.eckert@amd.com } 108710152Satgutier@umich.edu 108810152Satgutier@umich.edu 108910234Syasuko.eckert@amd.com uint32_t RWP = num_rw_ports; 109010234Syasuko.eckert@amd.com uint32_t ERP = num_rd_ports; 109110234Syasuko.eckert@amd.com uint32_t EWP = num_wr_ports; 109210234Syasuko.eckert@amd.com uint32_t NSER = num_se_rd_ports; 109310234Syasuko.eckert@amd.com uint32_t SCHP = num_search_ports; 109410152Satgutier@umich.edu 109510152Satgutier@umich.edu//TODO: revisit this. This is an important feature. Sheng thought this should be used 109610152Satgutier@umich.edu// // If multiple banks and multiple ports are specified, then if number of ports is less than or equal to 109710152Satgutier@umich.edu// // the number of banks, we assume that the multiple ports are implemented via the multiple banks. 109810152Satgutier@umich.edu// // In such a case we assume that each bank has 1 RWP port. 109910152Satgutier@umich.edu// if ((RWP + ERP + EWP) <= nbanks && nbanks>1) 110010152Satgutier@umich.edu// { 110110152Satgutier@umich.edu// RWP = 1; 110210152Satgutier@umich.edu// ERP = 0; 110310152Satgutier@umich.edu// EWP = 0; 110410152Satgutier@umich.edu// NSER = 0; 110510152Satgutier@umich.edu// } 110610152Satgutier@umich.edu// else if ((RWP < 0) || (EWP < 0) || (ERP < 0)) 110710152Satgutier@umich.edu// { 110810152Satgutier@umich.edu// cerr << "Ports must >=0" << endl; 110910152Satgutier@umich.edu// return false; 111010152Satgutier@umich.edu// } 111110152Satgutier@umich.edu// else if (RWP > 2) 111210152Satgutier@umich.edu// { 111310152Satgutier@umich.edu// cerr << "Maximum of 2 read/write ports" << endl; 111410152Satgutier@umich.edu// return false; 111510152Satgutier@umich.edu// } 111610152Satgutier@umich.edu// else if ((RWP+ERP+EWP) < 1) 111710234Syasuko.eckert@amd.com // Changed to new implementation: 111810234Syasuko.eckert@amd.com // The number of ports specified at input is per bank 111910234Syasuko.eckert@amd.com if ((RWP + ERP + EWP) < 1) { 112010234Syasuko.eckert@amd.com cerr << name << ": Must have at least one port" << endl; 112110234Syasuko.eckert@amd.com return false; 112210234Syasuko.eckert@amd.com } 112310152Satgutier@umich.edu 112410234Syasuko.eckert@amd.com if (is_pow2(nbanks) == false) { 112510234Syasuko.eckert@amd.com cerr << name << ": Number of subbanks should be greater than or " 112610234Syasuko.eckert@amd.com << "equal to 1 and should be a power of 2, but is set to " 112710234Syasuko.eckert@amd.com << nbanks << endl; 112810234Syasuko.eckert@amd.com return false; 112910234Syasuko.eckert@amd.com } 113010152Satgutier@umich.edu 113110234Syasuko.eckert@amd.com int C = cache_sz / nbanks; 113210234Syasuko.eckert@amd.com if (C < 64) { 113310234Syasuko.eckert@amd.com cerr << name << ": Cache size must be >=64, but is set to " << C 113410234Syasuko.eckert@amd.com << endl; 113510234Syasuko.eckert@amd.com return false; 113610234Syasuko.eckert@amd.com } 113710152Satgutier@umich.edu 113810152Satgutier@umich.edu//TODO: revisit this 113910152Satgutier@umich.edu// if (pure_ram==true && assoc!=1) 114010152Satgutier@umich.edu// { 114110152Satgutier@umich.edu// cerr << "Pure RAM must have assoc as 1" << endl; 114210152Satgutier@umich.edu// return false; 114310152Satgutier@umich.edu// } 114410152Satgutier@umich.edu 114510152Satgutier@umich.edu //fully assoc and cam check 114610234Syasuko.eckert@amd.com if (is_cache && assoc == 0) 114710234Syasuko.eckert@amd.com fully_assoc = true; 114810152Satgutier@umich.edu else 114910152Satgutier@umich.edu fully_assoc = false; 115010152Satgutier@umich.edu 115110234Syasuko.eckert@amd.com if (pure_cam == true && assoc != 0) { 115210234Syasuko.eckert@amd.com cerr << name 115310234Syasuko.eckert@amd.com << ": Pure CAM must have associativity as 0, but is set to" 115410234Syasuko.eckert@amd.com << assoc << endl; 115510234Syasuko.eckert@amd.com return false; 115610152Satgutier@umich.edu } 115710152Satgutier@umich.edu 115810234Syasuko.eckert@amd.com if (assoc == 0 && (pure_cam == false && is_cache == false)) { 115910234Syasuko.eckert@amd.com cerr << name 116010234Syasuko.eckert@amd.com << ": Only CAM or Fully associative cache can have associativity " 116110234Syasuko.eckert@amd.com << "as 0" << endl; 116210234Syasuko.eckert@amd.com return false; 116310152Satgutier@umich.edu } 116410152Satgutier@umich.edu 116510234Syasuko.eckert@amd.com if ((fully_assoc == true || pure_cam == true) 116610234Syasuko.eckert@amd.com && (data_arr_ram_cell_tech_type != tag_arr_ram_cell_tech_type 116710234Syasuko.eckert@amd.com || data_arr_peri_global_tech_type != tag_arr_peri_global_tech_type)) { 116810234Syasuko.eckert@amd.com cerr << name 116910234Syasuko.eckert@amd.com << ": CAM and fully associative cache must have same device type " 117010234Syasuko.eckert@amd.com << "for both data and tag array" << endl; 117110234Syasuko.eckert@amd.com cerr << "\tData array RAM cell = " << data_arr_ram_cell_tech_type 117210234Syasuko.eckert@amd.com << ", Tag array RAM cell = " << tag_arr_ram_cell_tech_type << endl 117310234Syasuko.eckert@amd.com << "\tData array peripheral = " << data_arr_peri_global_tech_type 117410234Syasuko.eckert@amd.com << ", Tag array peripheral = " << tag_arr_peri_global_tech_type 117510234Syasuko.eckert@amd.com << endl; 117610234Syasuko.eckert@amd.com return false; 117710152Satgutier@umich.edu } 117810152Satgutier@umich.edu 117910234Syasuko.eckert@amd.com if ((fully_assoc == true || pure_cam == true) 118010234Syasuko.eckert@amd.com && (data_arr_ram_cell_tech_type == lp_dram || 118110234Syasuko.eckert@amd.com data_arr_ram_cell_tech_type == comm_dram)) { 118210234Syasuko.eckert@amd.com cerr << name << ": DRAM based CAM and fully associative cache are not " 118310234Syasuko.eckert@amd.com << "supported" << endl; 118410234Syasuko.eckert@amd.com return false; 118510152Satgutier@umich.edu } 118610152Satgutier@umich.edu 118710234Syasuko.eckert@amd.com if ((fully_assoc == true || pure_cam == true) 118810234Syasuko.eckert@amd.com && (is_main_mem == true)) { 118910234Syasuko.eckert@amd.com cerr << name 119010234Syasuko.eckert@amd.com << ": CAM and fully associative cache cannot be as main memory" 119110234Syasuko.eckert@amd.com << endl; 119210234Syasuko.eckert@amd.com return false; 119310152Satgutier@umich.edu } 119410152Satgutier@umich.edu 119510234Syasuko.eckert@amd.com if ((fully_assoc || pure_cam) && SCHP < 1) { 119610234Syasuko.eckert@amd.com cerr << name 119710234Syasuko.eckert@amd.com << ": CAM and fully associative must have at least 1 search port," 119810234Syasuko.eckert@amd.com << " but are set to " << SCHP << endl; 119910234Syasuko.eckert@amd.com return false; 120010152Satgutier@umich.edu } 120110152Satgutier@umich.edu 120210234Syasuko.eckert@amd.com if (RWP == 0 && ERP == 0 && SCHP > 0 && ((fully_assoc || pure_cam))) { 120310234Syasuko.eckert@amd.com ERP = SCHP; 120410152Satgutier@umich.edu } 120510152Satgutier@umich.edu 120610152Satgutier@umich.edu// if ((!(fully_assoc || pure_cam)) && SCHP>=1) 120710152Satgutier@umich.edu// { 120810152Satgutier@umich.edu// cerr << "None CAM and fully associative cannot have search ports" << endl; 120910152Satgutier@umich.edu// return false; 121010152Satgutier@umich.edu// } 121110152Satgutier@umich.edu 121210234Syasuko.eckert@amd.com if (assoc == 0) { 121310234Syasuko.eckert@amd.com A = C / B; 121410234Syasuko.eckert@amd.com //fully_assoc = true; 121510234Syasuko.eckert@amd.com } else { 121610234Syasuko.eckert@amd.com if (assoc == 1) { 121710234Syasuko.eckert@amd.com A = 1; 121810234Syasuko.eckert@amd.com //fully_assoc = false; 121910234Syasuko.eckert@amd.com } else { 122010234Syasuko.eckert@amd.com //fully_assoc = false; 122110234Syasuko.eckert@amd.com A = assoc; 122210234Syasuko.eckert@amd.com if (is_pow2(A) == false) { 122310234Syasuko.eckert@amd.com cerr << name 122410234Syasuko.eckert@amd.com << ": Associativity must be a power of 2, but is set to " 122510234Syasuko.eckert@amd.com << A << endl; 122610234Syasuko.eckert@amd.com return false; 122710234Syasuko.eckert@amd.com } 122810234Syasuko.eckert@amd.com } 122910152Satgutier@umich.edu } 123010234Syasuko.eckert@amd.com 123110234Syasuko.eckert@amd.com if (C / (B*A) <= 1 && assoc != 0) { 123210234Syasuko.eckert@amd.com cerr << name << ": Number of sets (" << (C / (B * A)) 123310234Syasuko.eckert@amd.com << ") is too small: " << endl; 123410234Syasuko.eckert@amd.com cerr << " Need to either increase cache size, or decrease " 123510234Syasuko.eckert@amd.com << "associativity or block size" << endl; 123610234Syasuko.eckert@amd.com cerr << " (or use fully associative cache)" << endl; 123710152Satgutier@umich.edu return false; 123810152Satgutier@umich.edu } 123910152Satgutier@umich.edu 124010234Syasuko.eckert@amd.com block_sz = B; 124110152Satgutier@umich.edu 124210234Syasuko.eckert@amd.com /*dt: testing sequential access mode*/ 124310234Syasuko.eckert@amd.com if (seq_access) { 124410234Syasuko.eckert@amd.com tag_assoc = A; 124510234Syasuko.eckert@amd.com data_assoc = 1; 124610234Syasuko.eckert@amd.com is_seq_acc = true; 124710234Syasuko.eckert@amd.com } else { 124810234Syasuko.eckert@amd.com tag_assoc = A; 124910234Syasuko.eckert@amd.com data_assoc = A; 125010234Syasuko.eckert@amd.com is_seq_acc = false; 125110234Syasuko.eckert@amd.com } 125210152Satgutier@umich.edu 125310234Syasuko.eckert@amd.com if (assoc == 0) { 125410234Syasuko.eckert@amd.com data_assoc = 1; 125510234Syasuko.eckert@amd.com } 125610234Syasuko.eckert@amd.com num_rw_ports = RWP; 125710234Syasuko.eckert@amd.com num_rd_ports = ERP; 125810234Syasuko.eckert@amd.com num_wr_ports = EWP; 125910234Syasuko.eckert@amd.com num_se_rd_ports = NSER; 126010234Syasuko.eckert@amd.com if (!(fully_assoc || pure_cam)) 126110234Syasuko.eckert@amd.com num_search_ports = 0; 126210234Syasuko.eckert@amd.com nsets = C / (B * A); 126310152Satgutier@umich.edu 126410234Syasuko.eckert@amd.com if (temp < 300 || temp > 400 || temp % 10 != 0) { 126510234Syasuko.eckert@amd.com cerr << name << ": " << temp 126610234Syasuko.eckert@amd.com << " Temperature must be between 300 and 400 Kelvin and multiple " 126710234Syasuko.eckert@amd.com << "of 10." << endl; 126810234Syasuko.eckert@amd.com return false; 126910234Syasuko.eckert@amd.com } 127010152Satgutier@umich.edu 127110234Syasuko.eckert@amd.com if (nsets < 1) { 127210234Syasuko.eckert@amd.com cerr << name << ": Less than one set..." << endl; 127310234Syasuko.eckert@amd.com return false; 127410234Syasuko.eckert@amd.com } 127510152Satgutier@umich.edu 127610234Syasuko.eckert@amd.com return true; 127710152Satgutier@umich.edu} 127810152Satgutier@umich.edu 127910152Satgutier@umich.edu 128010152Satgutier@umich.edu 128110234Syasuko.eckert@amd.comvoid output_data_csv(const uca_org_t & fin_res) { 128210234Syasuko.eckert@amd.com //TODO: the csv output should remain 128310234Syasuko.eckert@amd.com fstream file("out.csv", ios::in); 128410234Syasuko.eckert@amd.com bool print_index = file.fail(); 128510234Syasuko.eckert@amd.com file.close(); 128610152Satgutier@umich.edu 128710234Syasuko.eckert@amd.com file.open("out.csv", ios::out | ios::app); 128810234Syasuko.eckert@amd.com if (file.fail() == true) { 128910234Syasuko.eckert@amd.com cerr << "File out.csv could not be opened successfully" << endl; 129010234Syasuko.eckert@amd.com } else { 129110234Syasuko.eckert@amd.com if (print_index == true) { 129210234Syasuko.eckert@amd.com file << "Tech node (nm), "; 129310234Syasuko.eckert@amd.com file << "Capacity (bytes), "; 129410234Syasuko.eckert@amd.com file << "Number of banks, "; 129510234Syasuko.eckert@amd.com file << "Associativity, "; 129610234Syasuko.eckert@amd.com file << "Output width (bits), "; 129710234Syasuko.eckert@amd.com file << "Access time (ns), "; 129810234Syasuko.eckert@amd.com file << "Random cycle time (ns), "; 129910234Syasuko.eckert@amd.com file << "Dynamic search energy (nJ), "; 130010234Syasuko.eckert@amd.com file << "Dynamic read energy (nJ), "; 130110234Syasuko.eckert@amd.com file << "Dynamic write energy (nJ), "; 130210234Syasuko.eckert@amd.com file << "Standby leakage per bank(mW), "; 130310234Syasuko.eckert@amd.com file << "Area (mm2), "; 130410234Syasuko.eckert@amd.com file << "Ndwl, "; 130510234Syasuko.eckert@amd.com file << "Ndbl, "; 130610234Syasuko.eckert@amd.com file << "Nspd, "; 130710234Syasuko.eckert@amd.com file << "Ndcm, "; 130810234Syasuko.eckert@amd.com file << "Ndsam_level_1, "; 130910234Syasuko.eckert@amd.com file << "Ndsam_level_2, "; 131010234Syasuko.eckert@amd.com file << "Data arrary area efficiency %, "; 131110234Syasuko.eckert@amd.com file << "Ntwl, "; 131210234Syasuko.eckert@amd.com file << "Ntbl, "; 131310234Syasuko.eckert@amd.com file << "Ntspd, "; 131410234Syasuko.eckert@amd.com file << "Ntcm, "; 131510234Syasuko.eckert@amd.com file << "Ntsam_level_1, "; 131610234Syasuko.eckert@amd.com file << "Ntsam_level_2, "; 131710234Syasuko.eckert@amd.com file << "Tag arrary area efficiency %, "; 131810152Satgutier@umich.edu 131910152Satgutier@umich.edu// file << "Resistance per unit micron (ohm-micron), "; 132010152Satgutier@umich.edu// file << "Capacitance per unit micron (fF per micron), "; 132110152Satgutier@umich.edu// file << "Unit-length wire delay (ps), "; 132210152Satgutier@umich.edu// file << "FO4 delay (ps), "; 132310152Satgutier@umich.edu// file << "delay route to bank (including crossb delay) (ps), "; 132410152Satgutier@umich.edu// file << "Crossbar delay (ps), "; 132510152Satgutier@umich.edu// file << "Dyn read energy per access from closed page (nJ), "; 132610152Satgutier@umich.edu// file << "Dyn read energy per access from open page (nJ), "; 132710152Satgutier@umich.edu// file << "Leak power of an subbank with page closed (mW), "; 132810152Satgutier@umich.edu// file << "Leak power of a subbank with page open (mW), "; 132910152Satgutier@umich.edu// file << "Leak power of request and reply networks (mW), "; 133010152Satgutier@umich.edu// file << "Number of subbanks, "; 133110152Satgutier@umich.edu// file << "Page size in bits, "; 133210152Satgutier@umich.edu// file << "Activate power, "; 133310152Satgutier@umich.edu// file << "Read power, "; 133410152Satgutier@umich.edu// file << "Write power, "; 133510152Satgutier@umich.edu// file << "Precharge power, "; 133610152Satgutier@umich.edu// file << "tRCD, "; 133710152Satgutier@umich.edu// file << "CAS latency, "; 133810152Satgutier@umich.edu// file << "Precharge delay, "; 133910152Satgutier@umich.edu// file << "Perc dyn energy bitlines, "; 134010152Satgutier@umich.edu// file << "perc dyn energy wordlines, "; 134110152Satgutier@umich.edu// file << "perc dyn energy outside mat, "; 134210152Satgutier@umich.edu// file << "Area opt (perc), "; 134310152Satgutier@umich.edu// file << "Delay opt (perc), "; 134410152Satgutier@umich.edu// file << "Repeater opt (perc), "; 134510152Satgutier@umich.edu// file << "Aspect ratio"; 134610234Syasuko.eckert@amd.com file << endl; 134710234Syasuko.eckert@amd.com } 134810234Syasuko.eckert@amd.com file << g_ip->F_sz_nm << ", "; 134910234Syasuko.eckert@amd.com file << g_ip->cache_sz << ", "; 135010234Syasuko.eckert@amd.com file << g_ip->nbanks << ", "; 135110234Syasuko.eckert@amd.com file << g_ip->tag_assoc << ", "; 135210234Syasuko.eckert@amd.com file << g_ip->out_w << ", "; 135310234Syasuko.eckert@amd.com file << fin_res.access_time*1e+9 << ", "; 135410234Syasuko.eckert@amd.com file << fin_res.cycle_time*1e+9 << ", "; 135510152Satgutier@umich.edu// file << fin_res.data_array2->multisubbank_interleave_cycle_time*1e+9 << ", "; 135610152Satgutier@umich.edu// file << fin_res.data_array2->delay_request_network*1e+9 << ", "; 135710152Satgutier@umich.edu// file << fin_res.data_array2->delay_inside_mat*1e+9 << ", "; 135810152Satgutier@umich.edu// file << fin_res.data_array2.delay_reply_network*1e+9 << ", "; 135910152Satgutier@umich.edu 136010152Satgutier@umich.edu// if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) 136110152Satgutier@umich.edu// { 136210152Satgutier@umich.edu// file << fin_res.tag_array2->access_time*1e+9 << ", "; 136310152Satgutier@umich.edu// } 136410152Satgutier@umich.edu// else 136510152Satgutier@umich.edu// { 136610152Satgutier@umich.edu// file << 0 << ", "; 136710152Satgutier@umich.edu// } 136810152Satgutier@umich.edu// file << fin_res.data_array2->access_time*1e+9 << ", "; 136910152Satgutier@umich.edu// file << fin_res.data_array2->dram_refresh_period*1e+6 << ", "; 137010152Satgutier@umich.edu// file << fin_res.data_array2->dram_array_availability << ", "; 137110234Syasuko.eckert@amd.com if (g_ip->fully_assoc || g_ip->pure_cam) { 137210234Syasuko.eckert@amd.com file << fin_res.power.searchOp.dynamic*1e+9 << ", "; 137310234Syasuko.eckert@amd.com } else { 137410234Syasuko.eckert@amd.com file << "N/A" << ", "; 137510234Syasuko.eckert@amd.com } 137610234Syasuko.eckert@amd.com file << fin_res.power.readOp.dynamic*1e+9 << ", "; 137710234Syasuko.eckert@amd.com file << fin_res.power.writeOp.dynamic*1e+9 << ", "; 137810152Satgutier@umich.edu// if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) 137910152Satgutier@umich.edu// { 138010152Satgutier@umich.edu// file << fin_res.tag_array2->power.readOp.dynamic*1e+9 << ", "; 138110152Satgutier@umich.edu// } 138210152Satgutier@umich.edu// else 138310152Satgutier@umich.edu// { 138410152Satgutier@umich.edu// file << "NA" << ", "; 138510152Satgutier@umich.edu// } 138610152Satgutier@umich.edu// file << fin_res.data_array2->power.readOp.dynamic*1e+9 << ", "; 138710152Satgutier@umich.edu// if (g_ip->fully_assoc || g_ip->pure_cam) 138810152Satgutier@umich.edu// { 138910152Satgutier@umich.edu// file << fin_res.power.searchOp.dynamic*1000/fin_res.cycle_time << ", "; 139010152Satgutier@umich.edu// } 139110152Satgutier@umich.edu// else 139210152Satgutier@umich.edu// { 139310152Satgutier@umich.edu// file << fin_res.power.readOp.dynamic*1000/fin_res.cycle_time << ", "; 139410152Satgutier@umich.edu// } 139510152Satgutier@umich.edu 139610152Satgutier@umich.edu file <<( fin_res.power.readOp.leakage + fin_res.power.readOp.gate_leakage )*1000 << ", "; 139710152Satgutier@umich.edu// file << fin_res.leak_power_with_sleep_transistors_in_mats*1000 << ", "; 139810152Satgutier@umich.edu// file << fin_res.data_array.refresh_power / fin_res.data_array.total_power.readOp.leakage << ", "; 139910234Syasuko.eckert@amd.com file << fin_res.area*1e-6 << ", "; 140010152Satgutier@umich.edu 140110234Syasuko.eckert@amd.com file << fin_res.data_array2->Ndwl << ", "; 140210234Syasuko.eckert@amd.com file << fin_res.data_array2->Ndbl << ", "; 140310234Syasuko.eckert@amd.com file << fin_res.data_array2->Nspd << ", "; 140410234Syasuko.eckert@amd.com file << fin_res.data_array2->deg_bl_muxing << ", "; 140510234Syasuko.eckert@amd.com file << fin_res.data_array2->Ndsam_lev_1 << ", "; 140610234Syasuko.eckert@amd.com file << fin_res.data_array2->Ndsam_lev_2 << ", "; 140710234Syasuko.eckert@amd.com file << fin_res.data_array2->area_efficiency << ", "; 140810234Syasuko.eckert@amd.com if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram)) { 140910234Syasuko.eckert@amd.com file << fin_res.tag_array2->Ndwl << ", "; 141010234Syasuko.eckert@amd.com file << fin_res.tag_array2->Ndbl << ", "; 141110234Syasuko.eckert@amd.com file << fin_res.tag_array2->Nspd << ", "; 141210234Syasuko.eckert@amd.com file << fin_res.tag_array2->deg_bl_muxing << ", "; 141310234Syasuko.eckert@amd.com file << fin_res.tag_array2->Ndsam_lev_1 << ", "; 141410234Syasuko.eckert@amd.com file << fin_res.tag_array2->Ndsam_lev_2 << ", "; 141510234Syasuko.eckert@amd.com file << fin_res.tag_array2->area_efficiency << ", "; 141610234Syasuko.eckert@amd.com } else { 141710152Satgutier@umich.edu file << "N/A" << ", "; 141810152Satgutier@umich.edu file << "N/A"<< ", "; 141910152Satgutier@umich.edu file << "N/A" << ", "; 142010152Satgutier@umich.edu file << "N/A" << ", "; 142110152Satgutier@umich.edu file << "N/A" << ", "; 142210152Satgutier@umich.edu file << "N/A" << ", "; 142310152Satgutier@umich.edu file << "N/A" << ", "; 142410152Satgutier@umich.edu } 142510152Satgutier@umich.edu 142610152Satgutier@umich.edu// file << g_tp.wire_inside_mat.R_per_um << ", "; 142710152Satgutier@umich.edu// file << g_tp.wire_inside_mat.C_per_um / 1e-15 << ", "; 142810152Satgutier@umich.edu// file << g_tp.unit_len_wire_del / 1e-12 << ", "; 142910152Satgutier@umich.edu// file << g_tp.FO4 / 1e-12 << ", "; 143010152Satgutier@umich.edu// file << fin_res.data_array.delay_route_to_bank / 1e-9 << ", "; 143110152Satgutier@umich.edu// file << fin_res.data_array.delay_crossbar / 1e-9 << ", "; 143210152Satgutier@umich.edu// file << fin_res.data_array.dyn_read_energy_from_closed_page / 1e-9 << ", "; 143310152Satgutier@umich.edu// file << fin_res.data_array.dyn_read_energy_from_open_page / 1e-9 << ", "; 143410152Satgutier@umich.edu// file << fin_res.data_array.leak_power_subbank_closed_page / 1e-3 << ", "; 143510152Satgutier@umich.edu// file << fin_res.data_array.leak_power_subbank_open_page / 1e-3 << ", "; 143610152Satgutier@umich.edu// file << fin_res.data_array.leak_power_request_and_reply_networks / 1e-3 << ", "; 143710152Satgutier@umich.edu// file << fin_res.data_array.number_subbanks << ", " ; 143810152Satgutier@umich.edu// file << fin_res.data_array.page_size_in_bits << ", " ; 143910152Satgutier@umich.edu// file << fin_res.data_array.activate_energy * 1e9 << ", " ; 144010152Satgutier@umich.edu// file << fin_res.data_array.read_energy * 1e9 << ", " ; 144110152Satgutier@umich.edu// file << fin_res.data_array.write_energy * 1e9 << ", " ; 144210152Satgutier@umich.edu// file << fin_res.data_array.precharge_energy * 1e9 << ", " ; 144310152Satgutier@umich.edu// file << fin_res.data_array.trcd * 1e9 << ", " ; 144410152Satgutier@umich.edu// file << fin_res.data_array.cas_latency * 1e9 << ", " ; 144510152Satgutier@umich.edu// file << fin_res.data_array.precharge_delay * 1e9 << ", " ; 144610152Satgutier@umich.edu// file << fin_res.data_array.all_banks_height / fin_res.data_array.all_banks_width; 144710234Syasuko.eckert@amd.com file<<endl; 144810234Syasuko.eckert@amd.com } 144910234Syasuko.eckert@amd.com file.close(); 145010152Satgutier@umich.edu} 145110152Satgutier@umich.edu 145210152Satgutier@umich.edu 145310152Satgutier@umich.edu 145410234Syasuko.eckert@amd.comvoid output_UCA(uca_org_t *fr) { 145510234Syasuko.eckert@amd.com // if (NUCA) 145610234Syasuko.eckert@amd.com if (0) { 145710234Syasuko.eckert@amd.com cout << "\n\n Detailed Bank Stats:\n"; 145810234Syasuko.eckert@amd.com cout << " Bank Size (bytes): %d\n" << 145910234Syasuko.eckert@amd.com (int) (g_ip->cache_sz); 146010234Syasuko.eckert@amd.com } else { 146110234Syasuko.eckert@amd.com if (g_ip->data_arr_ram_cell_tech_type == 3) { 146210234Syasuko.eckert@amd.com cout << "\n---------- CACTI version 6.5, Uniform Cache Access " << 146310234Syasuko.eckert@amd.com "Logic Process Based DRAM Model ----------\n"; 146410234Syasuko.eckert@amd.com } else if (g_ip->data_arr_ram_cell_tech_type == 4) { 146510234Syasuko.eckert@amd.com cout << "\n---------- CACTI version 6.5, Uniform" << 146610234Syasuko.eckert@amd.com "Cache Access Commodity DRAM Model ----------\n"; 146710234Syasuko.eckert@amd.com } else { 146810234Syasuko.eckert@amd.com cout << "\n---------- CACTI version 6.5, Uniform Cache Access " 146910234Syasuko.eckert@amd.com "SRAM Model ----------\n"; 147010234Syasuko.eckert@amd.com } 147110234Syasuko.eckert@amd.com cout << "\nCache Parameters:\n"; 147210234Syasuko.eckert@amd.com cout << " Total cache size (bytes): " << 147310234Syasuko.eckert@amd.com (int) (g_ip->cache_sz) << endl; 147410152Satgutier@umich.edu } 147510234Syasuko.eckert@amd.com 147610234Syasuko.eckert@amd.com cout << " Number of banks: " << (int) g_ip->nbanks << endl; 147710234Syasuko.eckert@amd.com if (g_ip->fully_assoc || g_ip->pure_cam) 147810234Syasuko.eckert@amd.com cout << " Associativity: fully associative\n"; 147910234Syasuko.eckert@amd.com else { 148010234Syasuko.eckert@amd.com if (g_ip->tag_assoc == 1) 148110234Syasuko.eckert@amd.com cout << " Associativity: direct mapped\n"; 148210234Syasuko.eckert@amd.com else 148310234Syasuko.eckert@amd.com cout << " Associativity: " << 148410234Syasuko.eckert@amd.com g_ip->tag_assoc << endl; 148510152Satgutier@umich.edu } 148610152Satgutier@umich.edu 148710152Satgutier@umich.edu 148810234Syasuko.eckert@amd.com cout << " Block size (bytes): " << g_ip->line_sz << endl; 148910234Syasuko.eckert@amd.com cout << " Read/write Ports: " << 149010234Syasuko.eckert@amd.com g_ip->num_rw_ports << endl; 149110234Syasuko.eckert@amd.com cout << " Read ports: " << 149210234Syasuko.eckert@amd.com g_ip->num_rd_ports << endl; 149310234Syasuko.eckert@amd.com cout << " Write ports: " << 149410234Syasuko.eckert@amd.com g_ip->num_wr_ports << endl; 149510234Syasuko.eckert@amd.com if (g_ip->fully_assoc || g_ip->pure_cam) 149610234Syasuko.eckert@amd.com cout << " search ports: " << 149710234Syasuko.eckert@amd.com g_ip->num_search_ports << endl; 149810234Syasuko.eckert@amd.com cout << " Technology size (nm): " << 149910234Syasuko.eckert@amd.com g_ip->F_sz_nm << endl << endl; 150010152Satgutier@umich.edu 150110234Syasuko.eckert@amd.com cout << " Access time (ns): " << fr->access_time*1e9 << endl; 150210234Syasuko.eckert@amd.com cout << " Cycle time (ns): " << fr->cycle_time*1e9 << endl; 150310234Syasuko.eckert@amd.com if (g_ip->data_arr_ram_cell_tech_type >= 4) { 150410234Syasuko.eckert@amd.com cout << " Precharge Delay (ns): " << fr->data_array2->precharge_delay*1e9 << endl; 150510234Syasuko.eckert@amd.com cout << " Activate Energy (nJ): " << fr->data_array2->activate_energy*1e9 << endl; 150610234Syasuko.eckert@amd.com cout << " Read Energy (nJ): " << fr->data_array2->read_energy*1e9 << endl; 150710234Syasuko.eckert@amd.com cout << " Write Energy (nJ): " << fr->data_array2->write_energy*1e9 << endl; 150810234Syasuko.eckert@amd.com cout << " Precharge Energy (nJ): " << fr->data_array2->precharge_energy*1e9 << endl; 150910234Syasuko.eckert@amd.com cout << " Leakage Power Closed Page (mW): " << fr->data_array2->leak_power_subbank_closed_page*1e3 << endl; 151010234Syasuko.eckert@amd.com cout << " Leakage Power Open Page (mW): " << fr->data_array2->leak_power_subbank_open_page*1e3 << endl; 151110234Syasuko.eckert@amd.com cout << " Leakage Power I/O (mW): " << fr->data_array2->leak_power_request_and_reply_networks*1e3 << endl; 151210234Syasuko.eckert@amd.com cout << " Refresh power (mW): " << 151310234Syasuko.eckert@amd.com fr->data_array2->refresh_power*1e3 << endl; 151410234Syasuko.eckert@amd.com } else { 151510234Syasuko.eckert@amd.com if ((g_ip->fully_assoc || g_ip->pure_cam)) { 151610234Syasuko.eckert@amd.com cout << " Total dynamic associative search energy per access (nJ): " << 151710234Syasuko.eckert@amd.com fr->power.searchOp.dynamic*1e9 << endl; 151810152Satgutier@umich.edu// cout << " Total dynamic read energy per access (nJ): " << 151910152Satgutier@umich.edu// fr->power.readOp.dynamic*1e9 << endl; 152010152Satgutier@umich.edu// cout << " Total dynamic write energy per access (nJ): " << 152110152Satgutier@umich.edu// fr->power.writeOp.dynamic*1e9 << endl; 152210234Syasuko.eckert@amd.com } 152310152Satgutier@umich.edu// else 152410152Satgutier@umich.edu// { 152510234Syasuko.eckert@amd.com cout << " Total dynamic read energy per access (nJ): " << 152610234Syasuko.eckert@amd.com fr->power.readOp.dynamic*1e9 << endl; 152710234Syasuko.eckert@amd.com cout << " Total dynamic write energy per access (nJ): " << 152810234Syasuko.eckert@amd.com fr->power.writeOp.dynamic*1e9 << endl; 152910152Satgutier@umich.edu// } 153010234Syasuko.eckert@amd.com cout << " Total leakage power of a bank" 153110234Syasuko.eckert@amd.com " (mW): " << fr->power.readOp.leakage*1e3 << endl; 153210234Syasuko.eckert@amd.com cout << " Total gate leakage power of a bank" 153310234Syasuko.eckert@amd.com " (mW): " << fr->power.readOp.gate_leakage*1e3 << endl; 153410152Satgutier@umich.edu } 153510152Satgutier@umich.edu 153610234Syasuko.eckert@amd.com if (g_ip->data_arr_ram_cell_tech_type == 3 || g_ip->data_arr_ram_cell_tech_type == 4) { 153710234Syasuko.eckert@amd.com } 153810234Syasuko.eckert@amd.com cout << " Cache height x width (mm): " << 153910234Syasuko.eckert@amd.com fr->cache_ht*1e-3 << " x " << fr->cache_len*1e-3 << endl << endl; 154010152Satgutier@umich.edu 154110152Satgutier@umich.edu 154210234Syasuko.eckert@amd.com cout << " Best Ndwl : " << fr->data_array2->Ndwl << endl; 154310234Syasuko.eckert@amd.com cout << " Best Ndbl : " << fr->data_array2->Ndbl << endl; 154410234Syasuko.eckert@amd.com cout << " Best Nspd : " << fr->data_array2->Nspd << endl; 154510234Syasuko.eckert@amd.com cout << " Best Ndcm : " << fr->data_array2->deg_bl_muxing << endl; 154610234Syasuko.eckert@amd.com cout << " Best Ndsam L1 : " << fr->data_array2->Ndsam_lev_1 << endl; 154710234Syasuko.eckert@amd.com cout << " Best Ndsam L2 : " << fr->data_array2->Ndsam_lev_2 << endl << endl; 154810152Satgutier@umich.edu 154910234Syasuko.eckert@amd.com if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && 155010234Syasuko.eckert@amd.com !g_ip->is_main_mem) { 155110234Syasuko.eckert@amd.com cout << " Best Ntwl : " << fr->tag_array2->Ndwl << endl; 155210234Syasuko.eckert@amd.com cout << " Best Ntbl : " << fr->tag_array2->Ndbl << endl; 155310234Syasuko.eckert@amd.com cout << " Best Ntspd : " << fr->tag_array2->Nspd << endl; 155410234Syasuko.eckert@amd.com cout << " Best Ntcm : " << fr->tag_array2->deg_bl_muxing << endl; 155510234Syasuko.eckert@amd.com cout << " Best Ntsam L1 : " << fr->tag_array2->Ndsam_lev_1 << endl; 155610234Syasuko.eckert@amd.com cout << " Best Ntsam L2 : " << fr->tag_array2->Ndsam_lev_2 << endl; 155710152Satgutier@umich.edu } 155810152Satgutier@umich.edu 155910234Syasuko.eckert@amd.com switch (fr->data_array2->wt) { 156010234Syasuko.eckert@amd.com case (0): 156110234Syasuko.eckert@amd.com cout << " Data array, H-tree wire type: Delay optimized global wires\n"; 156210234Syasuko.eckert@amd.com break; 156310234Syasuko.eckert@amd.com case (1): 156410234Syasuko.eckert@amd.com cout << " Data array, H-tree wire type: Global wires with 5\% delay penalty\n"; 156510234Syasuko.eckert@amd.com break; 156610234Syasuko.eckert@amd.com case (2): 156710234Syasuko.eckert@amd.com cout << " Data array, H-tree wire type: Global wires with 10\% delay penalty\n"; 156810234Syasuko.eckert@amd.com break; 156910234Syasuko.eckert@amd.com case (3): 157010234Syasuko.eckert@amd.com cout << " Data array, H-tree wire type: Global wires with 20\% delay penalty\n"; 157110234Syasuko.eckert@amd.com break; 157210234Syasuko.eckert@amd.com case (4): 157310234Syasuko.eckert@amd.com cout << " Data array, H-tree wire type: Global wires with 30\% delay penalty\n"; 157410234Syasuko.eckert@amd.com break; 157510234Syasuko.eckert@amd.com case (5): 157610234Syasuko.eckert@amd.com cout << " Data array, wire type: Low swing wires\n"; 157710234Syasuko.eckert@amd.com break; 157810234Syasuko.eckert@amd.com default: 157910234Syasuko.eckert@amd.com cout << "ERROR - Unknown wire type " << (int) fr->data_array2->wt << endl; 158010234Syasuko.eckert@amd.com exit(0); 158110234Syasuko.eckert@amd.com } 158210152Satgutier@umich.edu 158310234Syasuko.eckert@amd.com if (!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) { 158410234Syasuko.eckert@amd.com switch (fr->tag_array2->wt) { 158510234Syasuko.eckert@amd.com case (0): 158610234Syasuko.eckert@amd.com cout << " Tag array, H-tree wire type: Delay optimized global wires\n"; 158710234Syasuko.eckert@amd.com break; 158810234Syasuko.eckert@amd.com case (1): 158910234Syasuko.eckert@amd.com cout << " Tag array, H-tree wire type: Global wires with 5\% delay penalty\n"; 159010234Syasuko.eckert@amd.com break; 159110234Syasuko.eckert@amd.com case (2): 159210234Syasuko.eckert@amd.com cout << " Tag array, H-tree wire type: Global wires with 10\% delay penalty\n"; 159310234Syasuko.eckert@amd.com break; 159410234Syasuko.eckert@amd.com case (3): 159510234Syasuko.eckert@amd.com cout << " Tag array, H-tree wire type: Global wires with 20\% delay penalty\n"; 159610234Syasuko.eckert@amd.com break; 159710234Syasuko.eckert@amd.com case (4): 159810234Syasuko.eckert@amd.com cout << " Tag array, H-tree wire type: Global wires with 30\% delay penalty\n"; 159910234Syasuko.eckert@amd.com break; 160010234Syasuko.eckert@amd.com case (5): 160110234Syasuko.eckert@amd.com cout << " Tag array, wire type: Low swing wires\n"; 160210234Syasuko.eckert@amd.com break; 160310234Syasuko.eckert@amd.com default: 160410234Syasuko.eckert@amd.com cout << "ERROR - Unknown wire type " << (int) fr->tag_array2->wt << endl; 160510234Syasuko.eckert@amd.com exit(-1); 160610234Syasuko.eckert@amd.com } 160710234Syasuko.eckert@amd.com } 160810152Satgutier@umich.edu 160910234Syasuko.eckert@amd.com if (g_ip->print_detail) { 161010234Syasuko.eckert@amd.com /* Delay stats */ 161110234Syasuko.eckert@amd.com /* data array stats */ 161210234Syasuko.eckert@amd.com cout << endl << "Time Components:" << endl << endl; 161310152Satgutier@umich.edu 161410234Syasuko.eckert@amd.com cout << " Data side (with Output driver) (ns): " << 161510234Syasuko.eckert@amd.com fr->data_array2->access_time / 1e-9 << endl; 161610152Satgutier@umich.edu 161710234Syasuko.eckert@amd.com cout << "\tH-tree input delay (ns): " << 161810234Syasuko.eckert@amd.com fr->data_array2->delay_route_to_bank * 1e9 + 161910234Syasuko.eckert@amd.com fr->data_array2->delay_input_htree * 1e9 << endl; 162010152Satgutier@umich.edu 162110234Syasuko.eckert@amd.com if (!(g_ip->pure_cam || g_ip->fully_assoc)) { 162210234Syasuko.eckert@amd.com cout << "\tDecoder + wordline delay (ns): " << 162310234Syasuko.eckert@amd.com fr->data_array2->delay_row_predecode_driver_and_block * 1e9 + 162410234Syasuko.eckert@amd.com fr->data_array2->delay_row_decoder * 1e9 << endl; 162510234Syasuko.eckert@amd.com } else { 162610234Syasuko.eckert@amd.com cout << "\tCAM search delay (ns): " << 162710234Syasuko.eckert@amd.com fr->data_array2->delay_matchlines * 1e9 << endl; 162810234Syasuko.eckert@amd.com } 162910234Syasuko.eckert@amd.com 163010234Syasuko.eckert@amd.com cout << "\tBitline delay (ns): " << 163110234Syasuko.eckert@amd.com fr->data_array2->delay_bitlines / 1e-9 << endl; 163210234Syasuko.eckert@amd.com 163310234Syasuko.eckert@amd.com cout << "\tSense Amplifier delay (ns): " << 163410234Syasuko.eckert@amd.com fr->data_array2->delay_sense_amp * 1e9 << endl; 163510234Syasuko.eckert@amd.com 163610234Syasuko.eckert@amd.com 163710234Syasuko.eckert@amd.com cout << "\tH-tree output delay (ns): " << 163810234Syasuko.eckert@amd.com fr->data_array2->delay_subarray_output_driver * 1e9 + 163910234Syasuko.eckert@amd.com fr->data_array2->delay_dout_htree * 1e9 << endl; 164010234Syasuko.eckert@amd.com 164110234Syasuko.eckert@amd.com if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && 164210234Syasuko.eckert@amd.com !g_ip->is_main_mem) { 164310234Syasuko.eckert@amd.com /* tag array stats */ 164410234Syasuko.eckert@amd.com cout << endl << " Tag side (with Output driver) (ns): " << 164510234Syasuko.eckert@amd.com fr->tag_array2->access_time / 1e-9 << endl; 164610234Syasuko.eckert@amd.com 164710234Syasuko.eckert@amd.com cout << "\tH-tree input delay (ns): " << 164810234Syasuko.eckert@amd.com fr->tag_array2->delay_route_to_bank * 1e9 + 164910234Syasuko.eckert@amd.com fr->tag_array2->delay_input_htree * 1e9 << endl; 165010234Syasuko.eckert@amd.com 165110234Syasuko.eckert@amd.com cout << "\tDecoder + wordline delay (ns): " << 165210234Syasuko.eckert@amd.com fr->tag_array2->delay_row_predecode_driver_and_block * 1e9 + 165310234Syasuko.eckert@amd.com fr->tag_array2->delay_row_decoder * 1e9 << endl; 165410234Syasuko.eckert@amd.com 165510234Syasuko.eckert@amd.com cout << "\tBitline delay (ns): " << 165610234Syasuko.eckert@amd.com fr->tag_array2->delay_bitlines / 1e-9 << endl; 165710234Syasuko.eckert@amd.com 165810234Syasuko.eckert@amd.com cout << "\tSense Amplifier delay (ns): " << 165910234Syasuko.eckert@amd.com fr->tag_array2->delay_sense_amp * 1e9 << endl; 166010234Syasuko.eckert@amd.com 166110234Syasuko.eckert@amd.com cout << "\tComparator delay (ns): " << 166210234Syasuko.eckert@amd.com fr->tag_array2->delay_comparator * 1e9 << endl; 166310234Syasuko.eckert@amd.com 166410234Syasuko.eckert@amd.com cout << "\tH-tree output delay (ns): " << 166510234Syasuko.eckert@amd.com fr->tag_array2->delay_subarray_output_driver * 1e9 + 166610234Syasuko.eckert@amd.com fr->tag_array2->delay_dout_htree * 1e9 << endl; 166710234Syasuko.eckert@amd.com } 166810234Syasuko.eckert@amd.com 166910234Syasuko.eckert@amd.com 167010234Syasuko.eckert@amd.com 167110234Syasuko.eckert@amd.com /* Energy/Power stats */ 167210234Syasuko.eckert@amd.com cout << endl << endl << "Power Components:" << endl << endl; 167310234Syasuko.eckert@amd.com 167410234Syasuko.eckert@amd.com if (!(g_ip->pure_cam || g_ip->fully_assoc)) { 167510234Syasuko.eckert@amd.com cout << " Data array: Total dynamic read energy/access (nJ): " << 167610234Syasuko.eckert@amd.com fr->data_array2->power.readOp.dynamic * 1e9 << endl; 167710234Syasuko.eckert@amd.com cout << "\tTotal leakage read/write power of a bank (mW): " << 167810234Syasuko.eckert@amd.com fr->data_array2->power.readOp.leakage * 1e3 << endl; 167910234Syasuko.eckert@amd.com 168010234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 168110234Syasuko.eckert@amd.com "address and data transfer) (nJ): " << 168210234Syasuko.eckert@amd.com (fr->data_array2->power_addr_input_htree.readOp.dynamic + 168310234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic + 168410234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl; 168510234Syasuko.eckert@amd.com 168610234Syasuko.eckert@amd.com cout << "\tTotal leakage power in H-tree (that includes both " 168710234Syasuko.eckert@amd.com "address and data network) ((mW)): " << 168810152Satgutier@umich.edu (fr->data_array2->power_addr_input_htree.readOp.leakage + 168910152Satgutier@umich.edu fr->data_array2->power_data_output_htree.readOp.leakage + 169010234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.readOp.leakage) * 1e3 169110234Syasuko.eckert@amd.com << endl; 169210152Satgutier@umich.edu 169310234Syasuko.eckert@amd.com cout << "\tTotal gate leakage power in H-tree (that includes both " 169410234Syasuko.eckert@amd.com "address and data network) ((mW)): " << 169510152Satgutier@umich.edu (fr->data_array2->power_addr_input_htree.readOp.gate_leakage + 169610152Satgutier@umich.edu fr->data_array2->power_data_output_htree.readOp.gate_leakage + 169710234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.readOp.gate_leakage) * 169810234Syasuko.eckert@amd.com 1e3 << endl; 169910152Satgutier@umich.edu 170010234Syasuko.eckert@amd.com cout << "\tOutput Htree inside bank Energy (nJ): " << 170110234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl; 170210234Syasuko.eckert@amd.com cout << "\tDecoder (nJ): " << 170310234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 + 170410234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl; 170510234Syasuko.eckert@amd.com cout << "\tWordline (nJ): " << 170610234Syasuko.eckert@amd.com fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl; 170710234Syasuko.eckert@amd.com cout << "\tBitline mux & associated drivers (nJ): " << 170810234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 + 170910234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 + 171010234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl; 171110234Syasuko.eckert@amd.com cout << "\tSense amp mux & associated drivers (nJ): " << 171210234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 + 171310234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 + 171410234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9 + 171510234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 + 171610234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 + 171710234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl; 171810152Satgutier@umich.edu 171910234Syasuko.eckert@amd.com cout << "\tBitlines precharge and equalization circuit (nJ): " << 172010234Syasuko.eckert@amd.com fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl; 172110234Syasuko.eckert@amd.com cout << "\tBitlines (nJ): " << 172210234Syasuko.eckert@amd.com fr->data_array2->power_bitlines.readOp.dynamic * 1e9 << endl; 172310234Syasuko.eckert@amd.com cout << "\tSense amplifier energy (nJ): " << 172410234Syasuko.eckert@amd.com fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl; 172510234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 172610234Syasuko.eckert@amd.com fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl; 172710234Syasuko.eckert@amd.com } 172810152Satgutier@umich.edu 172910234Syasuko.eckert@amd.com else if (g_ip->pure_cam) { 173010152Satgutier@umich.edu 173110234Syasuko.eckert@amd.com cout << " CAM array:" << endl; 173210234Syasuko.eckert@amd.com cout << " Total dynamic associative search energy/access (nJ): " << 173310234Syasuko.eckert@amd.com fr->data_array2->power.searchOp.dynamic * 1e9 << endl; 173410234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 173510234Syasuko.eckert@amd.com "match key and data transfer) (nJ): " << 173610234Syasuko.eckert@amd.com (fr->data_array2->power_htree_in_search.searchOp.dynamic + 173710234Syasuko.eckert@amd.com fr->data_array2->power_htree_out_search.searchOp.dynamic + 173810234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9 << endl; 173910234Syasuko.eckert@amd.com cout << "\tKeyword input and result output Htrees inside bank Energy (nJ): " << 174010234Syasuko.eckert@amd.com (fr->data_array2->power_htree_in_search.searchOp.dynamic + 174110234Syasuko.eckert@amd.com fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9 << endl; 174210234Syasuko.eckert@amd.com cout << "\tSearchlines (nJ): " << 174310234Syasuko.eckert@amd.com fr->data_array2->power_searchline.searchOp.dynamic * 1e9 + 174410234Syasuko.eckert@amd.com fr->data_array2->power_searchline_precharge.searchOp.dynamic * 1e9 << endl; 174510234Syasuko.eckert@amd.com cout << "\tMatchlines (nJ): " << 174610234Syasuko.eckert@amd.com fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 + 174710234Syasuko.eckert@amd.com fr->data_array2->power_matchline_precharge.searchOp.dynamic * 1e9 << endl; 174810234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 174910234Syasuko.eckert@amd.com fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic * 1e9 << endl; 175010152Satgutier@umich.edu 175110152Satgutier@umich.edu 175210234Syasuko.eckert@amd.com cout << endl << " Total dynamic read energy/access (nJ): " << 175310234Syasuko.eckert@amd.com fr->data_array2->power.readOp.dynamic * 1e9 << endl; 175410234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 175510234Syasuko.eckert@amd.com "address and data transfer) (nJ): " << 175610234Syasuko.eckert@amd.com (fr->data_array2->power_addr_input_htree.readOp.dynamic + 175710234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic + 175810234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl; 175910234Syasuko.eckert@amd.com cout << "\tOutput Htree inside bank Energy (nJ): " << 176010234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl; 176110234Syasuko.eckert@amd.com cout << "\tDecoder (nJ): " << 176210234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 + 176310234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl; 176410234Syasuko.eckert@amd.com cout << "\tWordline (nJ): " << 176510234Syasuko.eckert@amd.com fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl; 176610234Syasuko.eckert@amd.com cout << "\tBitline mux & associated drivers (nJ): " << 176710234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 + 176810234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 + 176910234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl; 177010234Syasuko.eckert@amd.com cout << "\tSense amp mux & associated drivers (nJ): " << 177110234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 + 177210234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 + 177310234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9 + 177410234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 + 177510234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 + 177610234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl; 177710234Syasuko.eckert@amd.com cout << "\tBitlines (nJ): " << 177810234Syasuko.eckert@amd.com fr->data_array2->power_bitlines.readOp.dynamic * 1e9 + 177910234Syasuko.eckert@amd.com fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl; 178010234Syasuko.eckert@amd.com cout << "\tSense amplifier energy (nJ): " << 178110234Syasuko.eckert@amd.com fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl; 178210234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 178310234Syasuko.eckert@amd.com fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl; 178410152Satgutier@umich.edu 178510234Syasuko.eckert@amd.com cout << endl << " Total leakage power of a bank (mW): " << 178610234Syasuko.eckert@amd.com fr->data_array2->power.readOp.leakage * 1e3 << endl; 178710234Syasuko.eckert@amd.com } else { 178810234Syasuko.eckert@amd.com cout << " Fully associative array:" << endl; 178910234Syasuko.eckert@amd.com cout << " Total dynamic associative search energy/access (nJ): " << 179010234Syasuko.eckert@amd.com fr->data_array2->power.searchOp.dynamic * 1e9 << endl; 179110234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 179210234Syasuko.eckert@amd.com "match key and data transfer) (nJ): " << 179310234Syasuko.eckert@amd.com (fr->data_array2->power_htree_in_search.searchOp.dynamic + 179410234Syasuko.eckert@amd.com fr->data_array2->power_htree_out_search.searchOp.dynamic + 179510234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9 << endl; 179610234Syasuko.eckert@amd.com cout << "\tKeyword input and result output Htrees inside bank Energy (nJ): " << 179710234Syasuko.eckert@amd.com (fr->data_array2->power_htree_in_search.searchOp.dynamic + 179810234Syasuko.eckert@amd.com fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9 << endl; 179910234Syasuko.eckert@amd.com cout << "\tSearchlines (nJ): " << 180010234Syasuko.eckert@amd.com fr->data_array2->power_searchline.searchOp.dynamic * 1e9 + 180110234Syasuko.eckert@amd.com fr->data_array2->power_searchline_precharge.searchOp.dynamic * 1e9 << endl; 180210234Syasuko.eckert@amd.com cout << "\tMatchlines (nJ): " << 180310234Syasuko.eckert@amd.com fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 + 180410234Syasuko.eckert@amd.com fr->data_array2->power_matchline_precharge.searchOp.dynamic * 1e9 << endl; 180510234Syasuko.eckert@amd.com cout << "\tData portion wordline (nJ): " << 180610234Syasuko.eckert@amd.com fr->data_array2->power_matchline_to_wordline_drv.searchOp.dynamic * 1e9 << endl; 180710234Syasuko.eckert@amd.com cout << "\tData Bitlines (nJ): " << 180810234Syasuko.eckert@amd.com fr->data_array2->power_bitlines.searchOp.dynamic * 1e9 + 180910234Syasuko.eckert@amd.com fr->data_array2->power_prechg_eq_drivers.searchOp.dynamic * 1e9 << endl; 181010234Syasuko.eckert@amd.com cout << "\tSense amplifier energy (nJ): " << 181110234Syasuko.eckert@amd.com fr->data_array2->power_sense_amps.searchOp.dynamic * 1e9 << endl; 181210234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 181310234Syasuko.eckert@amd.com fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic * 1e9 << endl; 181410234Syasuko.eckert@amd.com 181510234Syasuko.eckert@amd.com 181610234Syasuko.eckert@amd.com cout << endl << " Total dynamic read energy/access (nJ): " << 181710234Syasuko.eckert@amd.com fr->data_array2->power.readOp.dynamic * 1e9 << endl; 181810234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 181910234Syasuko.eckert@amd.com "address and data transfer) (nJ): " << 182010234Syasuko.eckert@amd.com (fr->data_array2->power_addr_input_htree.readOp.dynamic + 182110234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic + 182210234Syasuko.eckert@amd.com fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl; 182310234Syasuko.eckert@amd.com cout << "\tOutput Htree inside bank Energy (nJ): " << 182410234Syasuko.eckert@amd.com fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl; 182510234Syasuko.eckert@amd.com cout << "\tDecoder (nJ): " << 182610234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 + 182710234Syasuko.eckert@amd.com fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl; 182810234Syasuko.eckert@amd.com cout << "\tWordline (nJ): " << 182910234Syasuko.eckert@amd.com fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl; 183010234Syasuko.eckert@amd.com cout << "\tBitline mux & associated drivers (nJ): " << 183110234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 + 183210234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 + 183310234Syasuko.eckert@amd.com fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl; 183410234Syasuko.eckert@amd.com cout << "\tSense amp mux & associated drivers (nJ): " << 183510234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 + 183610234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 + 183710234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9 + 183810234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 + 183910234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 + 184010234Syasuko.eckert@amd.com fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl; 184110234Syasuko.eckert@amd.com cout << "\tBitlines (nJ): " << 184210234Syasuko.eckert@amd.com fr->data_array2->power_bitlines.readOp.dynamic * 1e9 + 184310234Syasuko.eckert@amd.com fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl; 184410234Syasuko.eckert@amd.com cout << "\tSense amplifier energy (nJ): " << 184510234Syasuko.eckert@amd.com fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl; 184610234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 184710234Syasuko.eckert@amd.com fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl; 184810234Syasuko.eckert@amd.com 184910234Syasuko.eckert@amd.com cout << endl << " Total leakage power of a bank (mW): " << 185010234Syasuko.eckert@amd.com fr->data_array2->power.readOp.leakage * 1e3 << endl; 185110152Satgutier@umich.edu } 185210152Satgutier@umich.edu 185310152Satgutier@umich.edu 185410234Syasuko.eckert@amd.com if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && 185510234Syasuko.eckert@amd.com !g_ip->is_main_mem) { 185610234Syasuko.eckert@amd.com cout << endl << " Tag array: Total dynamic read energy/access (nJ): " << 185710234Syasuko.eckert@amd.com fr->tag_array2->power.readOp.dynamic * 1e9 << endl; 185810234Syasuko.eckert@amd.com cout << "\tTotal leakage read/write power of a bank (mW): " << 185910234Syasuko.eckert@amd.com fr->tag_array2->power.readOp.leakage * 1e3 << endl; 186010234Syasuko.eckert@amd.com cout << "\tTotal energy in H-tree (that includes both " 186110234Syasuko.eckert@amd.com "address and data transfer) (nJ): " << 186210234Syasuko.eckert@amd.com (fr->tag_array2->power_addr_input_htree.readOp.dynamic + 186310234Syasuko.eckert@amd.com fr->tag_array2->power_data_output_htree.readOp.dynamic + 186410234Syasuko.eckert@amd.com fr->tag_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl; 186510152Satgutier@umich.edu 186610234Syasuko.eckert@amd.com cout << "\tTotal leakage power in H-tree (that includes both " 186710234Syasuko.eckert@amd.com "address and data network) ((mW)): " << 186810152Satgutier@umich.edu (fr->tag_array2->power_addr_input_htree.readOp.leakage + 186910152Satgutier@umich.edu fr->tag_array2->power_data_output_htree.readOp.leakage + 187010234Syasuko.eckert@amd.com fr->tag_array2->power_routing_to_bank.readOp.leakage) * 1e3 187110234Syasuko.eckert@amd.com << endl; 187210152Satgutier@umich.edu 187310234Syasuko.eckert@amd.com cout << "\tTotal gate leakage power in H-tree (that includes both " 187410234Syasuko.eckert@amd.com "address and data network) ((mW)): " << 187510152Satgutier@umich.edu (fr->tag_array2->power_addr_input_htree.readOp.gate_leakage + 187610152Satgutier@umich.edu fr->tag_array2->power_data_output_htree.readOp.gate_leakage + 187710234Syasuko.eckert@amd.com fr->tag_array2->power_routing_to_bank.readOp.gate_leakage) * 187810234Syasuko.eckert@amd.com 1e3 << endl; 187910152Satgutier@umich.edu 188010234Syasuko.eckert@amd.com cout << "\tOutput Htree inside a bank Energy (nJ): " << 188110234Syasuko.eckert@amd.com fr->tag_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl; 188210234Syasuko.eckert@amd.com cout << "\tDecoder (nJ): " << 188310234Syasuko.eckert@amd.com fr->tag_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 + 188410234Syasuko.eckert@amd.com fr->tag_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl; 188510234Syasuko.eckert@amd.com cout << "\tWordline (nJ): " << 188610234Syasuko.eckert@amd.com fr->tag_array2->power_row_decoders.readOp.dynamic * 1e9 << endl; 188710234Syasuko.eckert@amd.com cout << "\tBitline mux & associated drivers (nJ): " << 188810234Syasuko.eckert@amd.com fr->tag_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 + 188910234Syasuko.eckert@amd.com fr->tag_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 + 189010234Syasuko.eckert@amd.com fr->tag_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl; 189110234Syasuko.eckert@amd.com cout << "\tSense amp mux & associated drivers (nJ): " << 189210234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 + 189310234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 + 189410234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9 + 189510234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 + 189610234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 + 189710234Syasuko.eckert@amd.com fr->tag_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl; 189810234Syasuko.eckert@amd.com cout << "\tBitlines precharge and equalization circuit (nJ): " << 189910234Syasuko.eckert@amd.com fr->tag_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl; 190010234Syasuko.eckert@amd.com cout << "\tBitlines (nJ): " << 190110234Syasuko.eckert@amd.com fr->tag_array2->power_bitlines.readOp.dynamic * 1e9 << endl; 190210234Syasuko.eckert@amd.com cout << "\tSense amplifier energy (nJ): " << 190310234Syasuko.eckert@amd.com fr->tag_array2->power_sense_amps.readOp.dynamic * 1e9 << endl; 190410234Syasuko.eckert@amd.com cout << "\tSub-array output driver (nJ): " << 190510234Syasuko.eckert@amd.com fr->tag_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl; 190610234Syasuko.eckert@amd.com } 190710234Syasuko.eckert@amd.com 190810234Syasuko.eckert@amd.com cout << endl << endl << "Area Components:" << endl << endl; 190910234Syasuko.eckert@amd.com /* Data array area stats */ 191010234Syasuko.eckert@amd.com if (!(g_ip->pure_cam || g_ip->fully_assoc)) 191110234Syasuko.eckert@amd.com cout << " Data array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl; 191210234Syasuko.eckert@amd.com else if (g_ip->pure_cam) 191310234Syasuko.eckert@amd.com cout << " CAM array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl; 191410234Syasuko.eckert@amd.com else 191510234Syasuko.eckert@amd.com cout << " Fully associative cache array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl; 191610234Syasuko.eckert@amd.com cout << "\tHeight (mm): " << 191710234Syasuko.eckert@amd.com fr->data_array2->all_banks_height*1e-3 << endl; 191810234Syasuko.eckert@amd.com cout << "\tWidth (mm): " << 191910234Syasuko.eckert@amd.com fr->data_array2->all_banks_width*1e-3 << endl; 192010234Syasuko.eckert@amd.com if (g_ip->print_detail) { 192110234Syasuko.eckert@amd.com cout << "\tArea efficiency (Memory cell area/Total area) - " << 192210234Syasuko.eckert@amd.com fr->data_array2->area_efficiency << " %" << endl; 192310234Syasuko.eckert@amd.com cout << "\t\tMAT Height (mm): " << 192410234Syasuko.eckert@amd.com fr->data_array2->mat_height*1e-3 << endl; 192510234Syasuko.eckert@amd.com cout << "\t\tMAT Length (mm): " << 192610234Syasuko.eckert@amd.com fr->data_array2->mat_length*1e-3 << endl; 192710234Syasuko.eckert@amd.com cout << "\t\tSubarray Height (mm): " << 192810234Syasuko.eckert@amd.com fr->data_array2->subarray_height*1e-3 << endl; 192910234Syasuko.eckert@amd.com cout << "\t\tSubarray Length (mm): " << 193010234Syasuko.eckert@amd.com fr->data_array2->subarray_length*1e-3 << endl; 193110234Syasuko.eckert@amd.com } 193210234Syasuko.eckert@amd.com 193310234Syasuko.eckert@amd.com /* Tag array area stats */ 193410234Syasuko.eckert@amd.com if ((!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) && 193510234Syasuko.eckert@amd.com !g_ip->is_main_mem) { 193610234Syasuko.eckert@amd.com cout << endl << " Tag array: Area (mm2): " << fr->tag_array2->area * 1e-6 << endl; 193710234Syasuko.eckert@amd.com cout << "\tHeight (mm): " << 193810234Syasuko.eckert@amd.com fr->tag_array2->all_banks_height*1e-3 << endl; 193910234Syasuko.eckert@amd.com cout << "\tWidth (mm): " << 194010234Syasuko.eckert@amd.com fr->tag_array2->all_banks_width*1e-3 << endl; 194110234Syasuko.eckert@amd.com if (g_ip->print_detail) { 194210234Syasuko.eckert@amd.com cout << "\tArea efficiency (Memory cell area/Total area) - " << 194310234Syasuko.eckert@amd.com fr->tag_array2->area_efficiency << " %" << endl; 194410234Syasuko.eckert@amd.com cout << "\t\tMAT Height (mm): " << 194510234Syasuko.eckert@amd.com fr->tag_array2->mat_height*1e-3 << endl; 194610234Syasuko.eckert@amd.com cout << "\t\tMAT Length (mm): " << 194710234Syasuko.eckert@amd.com fr->tag_array2->mat_length*1e-3 << endl; 194810234Syasuko.eckert@amd.com cout << "\t\tSubarray Height (mm): " << 194910234Syasuko.eckert@amd.com fr->tag_array2->subarray_height*1e-3 << endl; 195010234Syasuko.eckert@amd.com cout << "\t\tSubarray Length (mm): " << 195110234Syasuko.eckert@amd.com fr->tag_array2->subarray_length*1e-3 << endl; 195210234Syasuko.eckert@amd.com } 195310234Syasuko.eckert@amd.com } 195410234Syasuko.eckert@amd.com Wire wpr; 195510234Syasuko.eckert@amd.com wpr.print_wire(); 195610152Satgutier@umich.edu } 195710152Satgutier@umich.edu} 195810152Satgutier@umich.edu 195910152Satgutier@umich.edu//McPAT's plain interface, please keep !!! 196010234Syasuko.eckert@amd.comuca_org_t cacti_interface(InputParameter * const local_interface) { 196110234Syasuko.eckert@amd.com uca_org_t fin_res; 196210234Syasuko.eckert@amd.com fin_res.valid = false; 196310152Satgutier@umich.edu 196410234Syasuko.eckert@amd.com g_ip = local_interface; 196510152Satgutier@umich.edu 196610234Syasuko.eckert@amd.com if (!g_ip->error_checking()) { 196710234Syasuko.eckert@amd.com exit(0); 196810234Syasuko.eckert@amd.com } 196910152Satgutier@umich.edu 197010234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 197110234Syasuko.eckert@amd.com Wire winit; // Do not delete this line. It initializes wires. 197210152Satgutier@umich.edu 197310234Syasuko.eckert@amd.com solve(&fin_res); 197410152Satgutier@umich.edu 197510234Syasuko.eckert@amd.com return fin_res; 197610152Satgutier@umich.edu} 197710152Satgutier@umich.edu 197810152Satgutier@umich.edu//McPAT's plain interface, please keep !!! 197910234Syasuko.eckert@amd.comuca_org_t init_interface(InputParameter* const local_interface, 198010234Syasuko.eckert@amd.com const string &name) { 198110234Syasuko.eckert@amd.com uca_org_t fin_res; 198210234Syasuko.eckert@amd.com fin_res.valid = false; 198310152Satgutier@umich.edu 198410234Syasuko.eckert@amd.com g_ip = local_interface; 198510152Satgutier@umich.edu 198610234Syasuko.eckert@amd.com if (!g_ip->error_checking(name)) { 198710234Syasuko.eckert@amd.com exit(0); 198810234Syasuko.eckert@amd.com } 198910152Satgutier@umich.edu 199010234Syasuko.eckert@amd.com init_tech_params(g_ip->F_sz_um, false); 199110234Syasuko.eckert@amd.com Wire winit; // Do not delete this line. It initializes wires. 199210234Syasuko.eckert@amd.com return fin_res; 199310152Satgutier@umich.edu} 199410152Satgutier@umich.edu 199510152Satgutier@umich.eduvoid reconfigure(InputParameter *local_interface, uca_org_t *fin_res) 199610152Satgutier@umich.edu{ 199710152Satgutier@umich.edu // Copy the InputParameter to global interface (g_ip) and do error checking. 199810152Satgutier@umich.edu g_ip = local_interface; 199910152Satgutier@umich.edu g_ip->error_checking(); 200010152Satgutier@umich.edu 200110152Satgutier@umich.edu // Initialize technology parameters 200210152Satgutier@umich.edu init_tech_params(g_ip->F_sz_um,false); 200310152Satgutier@umich.edu 200410152Satgutier@umich.edu Wire winit; // Do not delete this line. It initializes wires. 200510152Satgutier@umich.edu 200610152Satgutier@umich.edu // This corresponds to solve() in the initialization process. 200710152Satgutier@umich.edu update(fin_res); 200810152Satgutier@umich.edu} 2009