io.cc revision 10152
1/*****************************************************************************
2 *                                McPAT/CACTI
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright 2012 Hewlett-Packard Development Company, L.P.
5 *                          All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
29 *
30 ***************************************************************************/
31
32
33
34#include <fstream>
35#include <iostream>
36#include <sstream>
37
38#include "Ucache.h"
39#include "arbiter.h"
40#include "area.h"
41#include "basic_circuit.h"
42#include "crossbar.h"
43#include "io.h"
44#include "nuca.h"
45#include "parameter.h"
46//#include "highradix.h"
47
48using namespace std;
49
50
51/* Parses "cache.cfg" file */
52  void
53InputParameter::parse_cfg(const string & in_file)
54{
55  FILE *fp = fopen(in_file.c_str(), "r");
56  char line[5000];
57  char jk[5000];
58  char temp_var[5000];
59
60  if(!fp) {
61    cout << in_file << " is missing!\n";
62    exit(-1);
63  }
64
65  while(fscanf(fp, "%[^\n]\n", line) != EOF) {
66
67    if (!strncmp("-size", line, strlen("-size"))) {
68      sscanf(line, "-size %[(:-~)*]%u", jk, &(cache_sz));
69      continue;
70    }
71
72    if (!strncmp("-page size", line, strlen("-page size"))) {
73      sscanf(line, "-page size %[(:-~)*]%u", jk, &(page_sz_bits));
74      continue;
75    }
76
77    if (!strncmp("-burst length", line, strlen("-burst length"))) {
78      sscanf(line, "-burst %[(:-~)*]%u", jk, &(burst_len));
79      continue;
80    }
81
82    if (!strncmp("-internal prefetch width", line, strlen("-internal prefetch width"))) {
83      sscanf(line, "-internal prefetch %[(:-~)*]%u", jk, &(int_prefetch_w));
84      continue;
85    }
86
87    if (!strncmp("-block", line, strlen("-block"))) {
88      sscanf(line, "-block size (bytes) %d", &(line_sz));
89      continue;
90    }
91
92    if (!strncmp("-associativity", line, strlen("-associativity"))) {
93      sscanf(line, "-associativity %d", &(assoc));
94      continue;
95    }
96
97    if (!strncmp("-read-write", line, strlen("-read-write"))) {
98      sscanf(line, "-read-write port %d", &(num_rw_ports));
99      continue;
100    }
101
102    if (!strncmp("-exclusive read", line, strlen("exclusive read"))) {
103      sscanf(line, "-exclusive read port %d", &(num_rd_ports));
104      continue;
105    }
106
107    if(!strncmp("-exclusive write", line, strlen("-exclusive write"))) {
108      sscanf(line, "-exclusive write port %d", &(num_wr_ports));
109      continue;
110    }
111
112    if (!strncmp("-single ended", line, strlen("-single ended"))) {
113      sscanf(line, "-single %[(:-~)*]%d", jk,
114          &(num_se_rd_ports));
115      continue;
116    }
117
118    if (!strncmp("-search", line, strlen("-search"))) {
119      sscanf(line, "-search port %d", &(num_search_ports));
120      continue;
121    }
122
123    if (!strncmp("-UCA bank", line, strlen("-UCA bank"))) {
124      sscanf(line, "-UCA bank%[((:-~)| )*]%d", jk, &(nbanks));
125      continue;
126    }
127
128    if (!strncmp("-technology", line, strlen("-technology"))) {
129      sscanf(line, "-technology (u) %lf", &(F_sz_um));
130      F_sz_nm = F_sz_um*1000;
131      continue;
132    }
133
134    if (!strncmp("-output/input", line, strlen("-output/input"))) {
135      sscanf(line, "-output/input bus %[(:-~)*]%d", jk, &(out_w));
136      continue;
137    }
138
139    if (!strncmp("-operating temperature", line, strlen("-operating temperature"))) {
140      sscanf(line, "-operating temperature %[(:-~)*]%d", jk, &(temp));
141      continue;
142    }
143
144    if (!strncmp("-cache type", line, strlen("-cache type"))) {
145      sscanf(line, "-cache type%[^\"]\"%[^\"]\"", jk, temp_var);
146
147      if (!strncmp("cache", temp_var, sizeof("cache"))) {
148        is_cache = true;
149      }
150      else
151      {
152        is_cache = false;
153      }
154
155      if (!strncmp("main memory", temp_var, sizeof("main memory"))) {
156        is_main_mem = true;
157      }
158      else {
159        is_main_mem = false;
160      }
161
162      if (!strncmp("cam", temp_var, sizeof("cam"))) {
163        pure_cam = true;
164      }
165      else {
166        pure_cam = false;
167      }
168
169      if (!strncmp("ram", temp_var, sizeof("ram"))) {
170        pure_ram = true;
171      }
172      else {
173          if (!is_main_mem)
174                  pure_ram = false;
175          else
176                  pure_ram = true;
177      }
178
179      continue;
180    }
181
182
183    if (!strncmp("-tag size", line, strlen("-tag size"))) {
184      sscanf(line, "-tag size%[^\"]\"%[^\"]\"", jk, temp_var);
185      if (!strncmp("default", temp_var, sizeof("default"))) {
186        specific_tag = false;
187        tag_w = 42; /* the acutal value is calculated
188                     * later based on the cache size, bank count, and associativity
189                     */
190      }
191      else {
192        specific_tag = true;
193        sscanf(line, "-tag size (b) %d", &(tag_w));
194      }
195      continue;
196    }
197
198    if (!strncmp("-access mode", line, strlen("-access mode"))) {
199      sscanf(line, "-access %[^\"]\"%[^\"]\"", jk, temp_var);
200      if (!strncmp("fast", temp_var, strlen("fast"))) {
201        access_mode = 2;
202      }
203      else if (!strncmp("sequential", temp_var, strlen("sequential"))) {
204        access_mode = 1;
205      }
206      else if(!strncmp("normal", temp_var, strlen("normal"))) {
207        access_mode = 0;
208      }
209      else {
210        cout << "ERROR: Invalid access mode!\n";
211        exit(0);
212      }
213      continue;
214    }
215
216    if (!strncmp("-Data array cell type", line, strlen("-Data array cell type"))) {
217      sscanf(line, "-Data array cell type %[^\"]\"%[^\"]\"", jk, temp_var);
218
219      if(!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) {
220        data_arr_ram_cell_tech_type = 0;
221      }
222      else if(!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) {
223        data_arr_ram_cell_tech_type = 1;
224      }
225      else if(!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) {
226        data_arr_ram_cell_tech_type = 2;
227      }
228      else if(!strncmp("lp-dram", temp_var, strlen("lp-dram"))) {
229        data_arr_ram_cell_tech_type = 3;
230      }
231      else if(!strncmp("comm-dram", temp_var, strlen("comm-dram"))) {
232        data_arr_ram_cell_tech_type = 4;
233      }
234      else {
235        cout << "ERROR: Invalid type!\n";
236        exit(0);
237      }
238      continue;
239    }
240
241    if (!strncmp("-Data array peripheral type", line, strlen("-Data array peripheral type"))) {
242      sscanf(line, "-Data array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var);
243
244      if(!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) {
245        data_arr_peri_global_tech_type = 0;
246      }
247      else if(!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) {
248        data_arr_peri_global_tech_type = 1;
249      }
250      else if(!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) {
251        data_arr_peri_global_tech_type = 2;
252      }
253      else {
254        cout << "ERROR: Invalid type!\n";
255        exit(0);
256      }
257      continue;
258    }
259
260    if (!strncmp("-Tag array cell type", line, strlen("-Tag array cell type"))) {
261      sscanf(line, "-Tag array cell type %[^\"]\"%[^\"]\"", jk, temp_var);
262
263      if(!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) {
264        tag_arr_ram_cell_tech_type = 0;
265      }
266      else if(!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) {
267        tag_arr_ram_cell_tech_type = 1;
268      }
269      else if(!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) {
270        tag_arr_ram_cell_tech_type = 2;
271      }
272      else if(!strncmp("lp-dram", temp_var, strlen("lp-dram"))) {
273        tag_arr_ram_cell_tech_type = 3;
274      }
275      else if(!strncmp("comm-dram", temp_var, strlen("comm-dram"))) {
276        tag_arr_ram_cell_tech_type = 4;
277      }
278      else {
279        cout << "ERROR: Invalid type!\n";
280        exit(0);
281      }
282      continue;
283    }
284
285    if (!strncmp("-Tag array peripheral type", line, strlen("-Tag array peripheral type"))) {
286      sscanf(line, "-Tag array peripheral type %[^\"]\"%[^\"]\"", jk, temp_var);
287
288      if(!strncmp("itrs-hp", temp_var, strlen("itrs-hp"))) {
289        tag_arr_peri_global_tech_type = 0;
290      }
291      else if(!strncmp("itrs-lstp", temp_var, strlen("itrs-lstp"))) {
292        tag_arr_peri_global_tech_type = 1;
293      }
294      else if(!strncmp("itrs-lop", temp_var, strlen("itrs-lop"))) {
295        tag_arr_peri_global_tech_type = 2;
296      }
297      else {
298        cout << "ERROR: Invalid type!\n";
299        exit(0);
300      }
301      continue;
302    }
303    if(!strncmp("-design", line, strlen("-design"))) {
304      sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk,
305          &(delay_wt), &(dynamic_power_wt),
306          &(leakage_power_wt),
307          &(cycle_time_wt), &(area_wt));
308      continue;
309    }
310
311    if(!strncmp("-deviate", line, strlen("-deviate"))) {
312      sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk,
313          &(delay_dev), &(dynamic_power_dev),
314          &(leakage_power_dev),
315          &(cycle_time_dev), &(area_dev));
316      continue;
317    }
318
319    if(!strncmp("-Optimize", line, strlen("-Optimize"))) {
320      sscanf(line, "-Optimize  %[^\"]\"%[^\"]\"", jk, temp_var);
321
322      if(!strncmp("ED^2", temp_var, strlen("ED^2"))) {
323        ed = 2;
324      }
325      else if(!strncmp("ED", temp_var, strlen("ED"))) {
326        ed = 1;
327      }
328      else {
329        ed = 0;
330      }
331    }
332
333    if(!strncmp("-NUCAdesign", line, strlen("-NUCAdesign"))) {
334      sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk,
335          &(delay_wt_nuca), &(dynamic_power_wt_nuca),
336          &(leakage_power_wt_nuca),
337          &(cycle_time_wt_nuca), &(area_wt_nuca));
338      continue;
339    }
340
341    if(!strncmp("-NUCAdeviate", line, strlen("-NUCAdeviate"))) {
342      sscanf(line, "-%[((:-~)| |,)*]%d:%d:%d:%d:%d", jk,
343          &(delay_dev_nuca), &(dynamic_power_dev_nuca),
344          &(leakage_power_dev_nuca),
345          &(cycle_time_dev_nuca), &(area_dev_nuca));
346      continue;
347    }
348
349    if(!strncmp("-Cache model", line, strlen("-cache model"))) {
350      sscanf(line, "-Cache model %[^\"]\"%[^\"]\"", jk, temp_var);
351
352      if (!strncmp("UCA", temp_var, strlen("UCA"))) {
353        nuca = 0;
354      }
355      else {
356        nuca = 1;
357      }
358      continue;
359    }
360
361    if(!strncmp("-NUCA bank", line, strlen("-NUCA bank"))) {
362      sscanf(line, "-NUCA bank count %d", &(nuca_bank_count));
363
364      if (nuca_bank_count != 0) {
365        force_nuca_bank = 1;
366      }
367      continue;
368    }
369
370    if(!strncmp("-Wire inside mat", line, strlen("-Wire inside mat"))) {
371      sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var);
372
373      if (!strncmp("global", temp_var, strlen("global"))) {
374        wire_is_mat_type = 2;
375        continue;
376      }
377      else if (!strncmp("local", temp_var, strlen("local"))) {
378        wire_is_mat_type = 0;
379        continue;
380      }
381      else {
382        wire_is_mat_type = 1;
383        continue;
384      }
385    }
386
387    if(!strncmp("-Wire outside mat", line, strlen("-Wire outside mat"))) {
388      sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var);
389
390      if (!strncmp("global", temp_var, strlen("global"))) {
391        wire_os_mat_type = 2;
392      }
393      else {
394        wire_os_mat_type = 1;
395      }
396      continue;
397    }
398
399    if(!strncmp("-Interconnect projection", line, strlen("-Interconnect projection"))) {
400      sscanf(line, "-Interconnect projection%[^\"]\"%[^\"]\"", jk, temp_var);
401
402      if (!strncmp("aggressive", temp_var, strlen("aggressive"))) {
403        ic_proj_type = 0;
404      }
405      else {
406        ic_proj_type = 1;
407      }
408      continue;
409    }
410
411    if(!strncmp("-Wire signalling", line, strlen("-wire signalling"))) {
412      sscanf(line, "-Wire%[^\"]\"%[^\"]\"", jk, temp_var);
413
414      if (!strncmp("default", temp_var, strlen("default"))) {
415        force_wiretype = 0;
416        wt = Global;
417      }
418      else if (!(strncmp("Global_10", temp_var, strlen("Global_10")))) {
419        force_wiretype = 1;
420        wt = Global_10;
421      }
422      else if (!(strncmp("Global_20", temp_var, strlen("Global_20")))) {
423        force_wiretype = 1;
424        wt = Global_20;
425      }
426      else if (!(strncmp("Global_30", temp_var, strlen("Global_30")))) {
427        force_wiretype = 1;
428        wt = Global_30;
429      }
430      else if (!(strncmp("Global_5", temp_var, strlen("Global_5")))) {
431        force_wiretype = 1;
432        wt = Global_5;
433      }
434      else if (!(strncmp("Global", temp_var, strlen("Global")))) {
435        force_wiretype = 1;
436        wt = Global;
437      }
438      else {
439        wt = Low_swing;
440        force_wiretype = 1;
441      }
442      continue;
443    }
444
445
446
447    if(!strncmp("-Core", line, strlen("-Core"))) {
448      sscanf(line, "-Core count %d\n", &(cores));
449      if (cores > 16) {
450        printf("No. of cores should be less than 16!\n");
451      }
452      continue;
453    }
454
455    if(!strncmp("-Cache level", line, strlen("-Cache level"))) {
456      sscanf(line, "-Cache l%[^\"]\"%[^\"]\"", jk, temp_var);
457      if (!strncmp("L2", temp_var, strlen("L2"))) {
458        cache_level = 0;
459      }
460      else {
461        cache_level = 1;
462      }
463    }
464
465    if(!strncmp("-Print level", line, strlen("-Print level"))) {
466      sscanf(line, "-Print l%[^\"]\"%[^\"]\"", jk, temp_var);
467      if (!strncmp("DETAILED", temp_var, strlen("DETAILED"))) {
468        print_detail = 1;
469      }
470      else {
471        print_detail = 0;
472      }
473
474    }
475    if(!strncmp("-Add ECC", line, strlen("-Add ECC"))) {
476      sscanf(line, "-Add ECC %[^\"]\"%[^\"]\"", jk, temp_var);
477      if (!strncmp("true", temp_var, strlen("true"))) {
478        add_ecc_b_ = true;
479      }
480      else {
481        add_ecc_b_ = false;
482      }
483    }
484
485    if(!strncmp("-Print input parameters", line, strlen("-Print input parameters"))) {
486      sscanf(line, "-Print input %[^\"]\"%[^\"]\"", jk, temp_var);
487      if (!strncmp("true", temp_var, strlen("true"))) {
488        print_input_args = true;
489      }
490      else {
491        print_input_args = false;
492      }
493    }
494
495    if(!strncmp("-Force cache config", line, strlen("-Force cache config"))) {
496      sscanf(line, "-Force cache %[^\"]\"%[^\"]\"", jk, temp_var);
497      if (!strncmp("true", temp_var, strlen("true"))) {
498        force_cache_config = true;
499      }
500      else {
501        force_cache_config = false;
502      }
503    }
504
505    if(!strncmp("-Ndbl", line, strlen("-Ndbl"))) {
506      sscanf(line, "-Ndbl %d\n", &(ndbl));
507      continue;
508    }
509    if(!strncmp("-Ndwl", line, strlen("-Ndwl"))) {
510      sscanf(line, "-Ndwl %d\n", &(ndwl));
511      continue;
512    }
513    if(!strncmp("-Nspd", line, strlen("-Nspd"))) {
514      sscanf(line, "-Nspd %d\n", &(nspd));
515      continue;
516    }
517    if(!strncmp("-Ndsam1", line, strlen("-Ndsam1"))) {
518      sscanf(line, "-Ndsam1 %d\n", &(ndsam1));
519      continue;
520    }
521    if(!strncmp("-Ndsam2", line, strlen("-Ndsam2"))) {
522      sscanf(line, "-Ndsam2 %d\n", &(ndsam2));
523      continue;
524    }
525   if(!strncmp("-Ndcm", line, strlen("-Ndcm"))) {
526      sscanf(line, "-Ndcm %d\n", &(ndcm));
527      continue;
528    }
529
530  }
531  rpters_in_htree = true;
532  fclose(fp);
533}
534
535  void
536InputParameter::display_ip()
537{
538  cout << "Cache size                    : " << cache_sz << endl;
539  cout << "Block size                    : " << line_sz << endl;
540  cout << "Associativity                 : " << assoc << endl;
541  cout << "Read only ports               : " << num_rd_ports << endl;
542  cout << "Write only ports              : " << num_wr_ports << endl;
543  cout << "Read write ports              : " << num_rw_ports << endl;
544  cout << "Single ended read ports       : " << num_se_rd_ports << endl;
545  if (fully_assoc||pure_cam)
546  {
547          cout << "Search ports                  : " << num_search_ports << endl;
548  }
549  cout << "Cache banks (UCA)             : " << nbanks << endl;
550  cout << "Technology                    : " << F_sz_um << endl;
551  cout << "Temperature                   : " << temp << endl;
552  cout << "Tag size                      : " << tag_w << endl;
553  if (is_cache) {
554    cout << "array type                    : " << "Cache" << endl;
555  }
556  if (pure_ram) {
557    cout << "array type                    : " << "Scratch RAM" << endl;
558  }
559  if (pure_cam)
560  {
561      cout << "array type                    : " << "CAM" << endl;
562  }
563  cout << "Model as memory               : " << is_main_mem << endl;
564  cout << "Access mode                   : " << access_mode << endl;
565  cout << "Data array cell type          : " << data_arr_ram_cell_tech_type << endl;
566  cout << "Data array peripheral type    : " << data_arr_peri_global_tech_type << endl;
567  cout << "Tag array cell type           : " << tag_arr_ram_cell_tech_type << endl;
568  cout << "Tag array peripheral type     : " << tag_arr_peri_global_tech_type << endl;
569  cout << "Optimization target           : " << ed << endl;
570  cout << "Design objective (UCA wt)     : " << delay_wt << " "
571                                                << dynamic_power_wt << " " << leakage_power_wt << " " << cycle_time_wt
572                                                << " " << area_wt << endl;
573  cout << "Design objective (UCA dev)    : " << delay_dev << " "
574                                                << dynamic_power_dev << " " << leakage_power_dev << " " << cycle_time_dev
575                                                << " " << area_dev << endl;
576  if (nuca)
577    {
578    cout << "Cores                         : " << cores << endl;
579
580
581    cout << "Design objective (NUCA wt)    : " << delay_wt_nuca << " "
582                                                << dynamic_power_wt_nuca << " " << leakage_power_wt_nuca << " " << cycle_time_wt_nuca
583                                                << " " << area_wt_nuca << endl;
584    cout << "Design objective (NUCA dev)   : " << delay_dev_nuca << " "
585                                                << dynamic_power_dev_nuca << " " << leakage_power_dev_nuca << " " << cycle_time_dev_nuca
586                                       << " " << area_dev_nuca << endl;
587    }
588  cout << "Cache model                   : " << nuca << endl;
589  cout << "Nuca bank                     : " << nuca_bank_count << endl;
590  cout << "Wire inside mat               : " << wire_is_mat_type << endl;
591  cout << "Wire outside mat              : " << wire_os_mat_type << endl;
592  cout << "Interconnect projection       : " << ic_proj_type << endl;
593  cout << "Wire signalling               : " << force_wiretype << endl;
594  cout << "Print level                   : " << print_detail << endl;
595  cout << "ECC overhead                  : " << add_ecc_b_ << endl;
596  cout << "Page size                     : " << page_sz_bits << endl;
597  cout << "Burst length                  : " << burst_len << endl;
598  cout << "Internal prefetch width       : " << int_prefetch_w << endl;
599  cout << "Force cache config            : " << g_ip->force_cache_config << endl;
600  if (g_ip->force_cache_config) {
601    cout << "Ndwl                          : " << g_ip->ndwl << endl;
602    cout << "Ndbl                          : " << g_ip->ndbl << endl;
603    cout << "Nspd                          : " << g_ip->nspd << endl;
604    cout << "Ndcm                          : " << g_ip->ndcm << endl;
605    cout << "Ndsam1                        : " << g_ip->ndsam1 << endl;
606    cout << "Ndsam2                        : " << g_ip->ndsam2 << endl;
607  }
608}
609
610
611
612powerComponents operator+(const powerComponents & x, const powerComponents & y)
613{
614  powerComponents z;
615
616  z.dynamic = x.dynamic + y.dynamic;
617  z.leakage = x.leakage + y.leakage;
618  z.gate_leakage  = x.gate_leakage  + y.gate_leakage;
619  z.short_circuit = x.short_circuit + y.short_circuit;
620  z.longer_channel_leakage = x.longer_channel_leakage + y.longer_channel_leakage;
621
622  return z;
623}
624
625powerComponents operator*(const powerComponents & x, double const * const y)
626{
627  powerComponents z;
628
629  z.dynamic = x.dynamic*y[0];
630  z.leakage = x.leakage*y[1];
631  z.gate_leakage  = x.gate_leakage*y[2];
632  z.short_circuit = x.short_circuit*y[3];
633  z.longer_channel_leakage = x.longer_channel_leakage*y[1];//longer channel leakage has the same behavior as normal leakage
634
635  return z;
636}
637
638
639powerDef operator+(const powerDef & x, const powerDef & y)
640{
641  powerDef z;
642
643  z.readOp   = x.readOp  + y.readOp;
644  z.writeOp  = x.writeOp + y.writeOp;
645  z.searchOp = x.searchOp + y.searchOp;
646  return z;
647}
648
649powerDef operator*(const powerDef & x, double const * const y)
650{
651  powerDef z;
652
653  z.readOp   = x.readOp*y;
654  z.writeOp  = x.writeOp*y;
655  z.searchOp = x.searchOp*y;
656  return z;
657}
658
659uca_org_t cacti_interface(const string & infile_name)
660{
661
662  uca_org_t fin_res;
663  //uca_org_t result;
664  fin_res.valid = false;
665
666  g_ip = new InputParameter();
667  g_ip->parse_cfg(infile_name);
668  if(!g_ip->error_checking())
669          exit(0);
670  if (g_ip->print_input_args)
671    g_ip->display_ip();
672
673  init_tech_params(g_ip->F_sz_um, false);
674  Wire winit; // Do not delete this line. It initializes wires.
675
676
677//  For HighRadix Only
678//  ////  Wire wirea(g_ip->wt, 1000);
679//  ////  wirea.print_wire();
680//  ////  cout << "Wire Area " << wirea.area.get_area() << " sq. u" << endl;
681//  //  winit.print_wire();
682//  //
683//    HighRadix *hr;
684//      hr = new HighRadix();
685//      hr->compute_power();
686//      hr->print_router();
687//    exit(0);
688//
689//    double sub_switch_sz = 2;
690//    double rows = 32;
691//    for (int i=0; i<6; i++) {
692//      sub_switch_sz = pow(2, i);
693//      rows = 64/sub_switch_sz;
694//      hr = new HighRadix(sub_switch_sz, rows, .8/* freq */, 64, 2, 64, 0.7);
695//      hr->compute_power();
696//      hr->print_router();
697//      delete hr;
698//    }
699//  //  HighRadix yarc;
700//  //  yarc.compute_power();
701//  //  yarc.print_router();
702//    winit.print_wire();
703//    exit(0);
704//  For HighRadix Only End
705
706  if (g_ip->nuca == 1)
707  {
708    Nuca n(&g_tp.peri_global);
709    n.sim_nuca();
710  }
711  g_ip->display_ip();
712  solve(&fin_res);
713
714  output_UCA(&fin_res);
715  output_data_csv(fin_res);
716
717  delete (g_ip);
718  return fin_res;
719}
720
721//cacti6.5's plain interface, please keep !!!
722uca_org_t cacti_interface(
723    int cache_size,
724    int line_size,
725    int associativity,
726    int rw_ports,
727    int excl_read_ports,
728    int excl_write_ports,
729    int single_ended_read_ports,
730    int banks,
731    double tech_node, // in nm
732    int page_sz,
733    int burst_length,
734    int pre_width,
735    int output_width,
736    int specific_tag,
737    int tag_width,
738    int access_mode, //0 normal, 1 seq, 2 fast
739    int cache, //scratch ram or cache
740    int main_mem,
741    int obj_func_delay,
742    int obj_func_dynamic_power,
743    int obj_func_leakage_power,
744    int obj_func_area,
745    int obj_func_cycle_time,
746    int dev_func_delay,
747    int dev_func_dynamic_power,
748    int dev_func_leakage_power,
749    int dev_func_area,
750    int dev_func_cycle_time,
751    int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
752    int temp,
753    int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
754    int data_arr_ram_cell_tech_flavor_in, // 0-4
755    int data_arr_peri_global_tech_flavor_in,
756    int tag_arr_ram_cell_tech_flavor_in,
757    int tag_arr_peri_global_tech_flavor_in,
758    int interconnect_projection_type_in, // 0 - aggressive, 1 - normal
759    int wire_inside_mat_type_in,
760    int wire_outside_mat_type_in,
761    int is_nuca, // 0 - UCA, 1 - NUCA
762    int core_count,
763    int cache_level, // 0 - L2, 1 - L3
764    int nuca_bank_count,
765    int nuca_obj_func_delay,
766    int nuca_obj_func_dynamic_power,
767    int nuca_obj_func_leakage_power,
768    int nuca_obj_func_area,
769    int nuca_obj_func_cycle_time,
770    int nuca_dev_func_delay,
771    int nuca_dev_func_dynamic_power,
772    int nuca_dev_func_leakage_power,
773    int nuca_dev_func_area,
774    int nuca_dev_func_cycle_time,
775    int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported
776    int p_input)
777{
778  g_ip = new InputParameter();
779  g_ip->add_ecc_b_ = true;
780
781  g_ip->data_arr_ram_cell_tech_type    = data_arr_ram_cell_tech_flavor_in;
782  g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in;
783  g_ip->tag_arr_ram_cell_tech_type     = tag_arr_ram_cell_tech_flavor_in;
784  g_ip->tag_arr_peri_global_tech_type  = tag_arr_peri_global_tech_flavor_in;
785
786  g_ip->ic_proj_type     = interconnect_projection_type_in;
787  g_ip->wire_is_mat_type = wire_inside_mat_type_in;
788  g_ip->wire_os_mat_type = wire_outside_mat_type_in;
789  g_ip->burst_len        = burst_length;
790  g_ip->int_prefetch_w   = pre_width;
791  g_ip->page_sz_bits     = page_sz;
792
793  g_ip->cache_sz            = cache_size;
794  g_ip->line_sz             = line_size;
795  g_ip->assoc               = associativity;
796  g_ip->nbanks              = banks;
797  g_ip->out_w               = output_width;
798  g_ip->specific_tag        = specific_tag;
799  if (tag_width == 0) {
800    g_ip->tag_w = 42;
801  }
802  else {
803    g_ip->tag_w               = tag_width;
804  }
805
806  g_ip->access_mode         = access_mode;
807  g_ip->delay_wt = obj_func_delay;
808  g_ip->dynamic_power_wt = obj_func_dynamic_power;
809  g_ip->leakage_power_wt = obj_func_leakage_power;
810  g_ip->area_wt = obj_func_area;
811  g_ip->cycle_time_wt    = obj_func_cycle_time;
812  g_ip->delay_dev = dev_func_delay;
813  g_ip->dynamic_power_dev = dev_func_dynamic_power;
814  g_ip->leakage_power_dev = dev_func_leakage_power;
815  g_ip->area_dev = dev_func_area;
816  g_ip->cycle_time_dev    = dev_func_cycle_time;
817  g_ip->ed = ed_ed2_none;
818
819  switch(wt) {
820    case (0):
821      g_ip->force_wiretype = 0;
822      g_ip->wt = Global;
823      break;
824    case (1):
825      g_ip->force_wiretype = 1;
826      g_ip->wt = Global;
827      break;
828    case (2):
829      g_ip->force_wiretype = 1;
830      g_ip->wt = Global_5;
831      break;
832    case (3):
833      g_ip->force_wiretype = 1;
834      g_ip->wt = Global_10;
835      break;
836    case (4):
837      g_ip->force_wiretype = 1;
838      g_ip->wt = Global_20;
839      break;
840    case (5):
841      g_ip->force_wiretype = 1;
842      g_ip->wt = Global_30;
843      break;
844    case (6):
845      g_ip->force_wiretype = 1;
846      g_ip->wt = Low_swing;
847      break;
848    default:
849      cout << "Unknown wire type!\n";
850      exit(0);
851  }
852
853  g_ip->delay_wt_nuca = nuca_obj_func_delay;
854  g_ip->dynamic_power_wt_nuca = nuca_obj_func_dynamic_power;
855  g_ip->leakage_power_wt_nuca = nuca_obj_func_leakage_power;
856  g_ip->area_wt_nuca = nuca_obj_func_area;
857  g_ip->cycle_time_wt_nuca    = nuca_obj_func_cycle_time;
858  g_ip->delay_dev_nuca = dev_func_delay;
859  g_ip->dynamic_power_dev_nuca = nuca_dev_func_dynamic_power;
860  g_ip->leakage_power_dev_nuca = nuca_dev_func_leakage_power;
861  g_ip->area_dev_nuca = nuca_dev_func_area;
862  g_ip->cycle_time_dev_nuca    = nuca_dev_func_cycle_time;
863  g_ip->nuca = is_nuca;
864  g_ip->nuca_bank_count = nuca_bank_count;
865  if(nuca_bank_count > 0) {
866    g_ip->force_nuca_bank = 1;
867  }
868  g_ip->cores = core_count;
869  g_ip->cache_level = cache_level;
870
871  g_ip->temp = temp;
872
873  g_ip->F_sz_nm         = tech_node;
874  g_ip->F_sz_um         = tech_node / 1000;
875  g_ip->is_main_mem     = (main_mem != 0) ? true : false;
876  g_ip->is_cache        = (cache != 0) ? true : false;
877  g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false;
878
879  g_ip->num_rw_ports    = rw_ports;
880  g_ip->num_rd_ports    = excl_read_ports;
881  g_ip->num_wr_ports    = excl_write_ports;
882  g_ip->num_se_rd_ports = single_ended_read_ports;
883  g_ip->print_detail = 1;
884  g_ip->nuca = 0;
885
886  g_ip->wt = Global_5;
887  g_ip->force_cache_config = false;
888  g_ip->force_wiretype = false;
889  g_ip->print_input_args = p_input;
890
891
892  uca_org_t fin_res;
893  fin_res.valid = false;
894
895  if (g_ip->error_checking() == false) exit(0);
896  if (g_ip->print_input_args)
897    g_ip->display_ip();
898  init_tech_params(g_ip->F_sz_um, false);
899  Wire winit; // Do not delete this line. It initializes wires.
900
901  if (g_ip->nuca == 1)
902  {
903    Nuca n(&g_tp.peri_global);
904    n.sim_nuca();
905  }
906  solve(&fin_res);
907
908  output_UCA(&fin_res);
909
910  delete (g_ip);
911  return fin_res;
912}
913
914//McPAT's plain interface, please keep !!!
915uca_org_t cacti_interface(
916    int cache_size,
917    int line_size,
918    int associativity,
919    int rw_ports,
920    int excl_read_ports,// para5
921    int excl_write_ports,
922    int single_ended_read_ports,
923    int search_ports,
924    int banks,
925    double tech_node,//para10
926    int output_width,
927    int specific_tag,
928    int tag_width,
929    int access_mode,
930    int cache,      //para15
931    int main_mem,
932    int obj_func_delay,
933    int obj_func_dynamic_power,
934    int obj_func_leakage_power,
935    int obj_func_cycle_time, //para20
936    int obj_func_area,
937    int dev_func_delay,
938    int dev_func_dynamic_power,
939    int dev_func_leakage_power,
940    int dev_func_area, //para25
941    int dev_func_cycle_time,
942    int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate
943    int temp,
944    int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing
945    int data_arr_ram_cell_tech_flavor_in,//para30
946    int data_arr_peri_global_tech_flavor_in,
947    int tag_arr_ram_cell_tech_flavor_in,
948    int tag_arr_peri_global_tech_flavor_in,
949    int interconnect_projection_type_in,
950    int wire_inside_mat_type_in,//para35
951    int wire_outside_mat_type_in,
952    int REPEATERS_IN_HTREE_SEGMENTS_in,
953    int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in,
954    int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in,
955    int PAGE_SIZE_BITS_in,//para40
956    int BURST_LENGTH_in,
957    int INTERNAL_PREFETCH_WIDTH_in,
958    int force_wiretype,
959    int wiretype,
960    int force_config,//para45
961    int ndwl,
962    int ndbl,
963    int nspd,
964    int ndcm,
965    int ndsam1,//para50
966    int ndsam2,
967    int ecc)
968{
969  g_ip = new InputParameter();
970
971  uca_org_t fin_res;
972  fin_res.valid = false;
973
974  g_ip->data_arr_ram_cell_tech_type    = data_arr_ram_cell_tech_flavor_in;
975  g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in;
976  g_ip->tag_arr_ram_cell_tech_type     = tag_arr_ram_cell_tech_flavor_in;
977  g_ip->tag_arr_peri_global_tech_type  = tag_arr_peri_global_tech_flavor_in;
978
979  g_ip->ic_proj_type     = interconnect_projection_type_in;
980  g_ip->wire_is_mat_type = wire_inside_mat_type_in;
981  g_ip->wire_os_mat_type = wire_outside_mat_type_in;
982  g_ip->burst_len        = BURST_LENGTH_in;
983  g_ip->int_prefetch_w   = INTERNAL_PREFETCH_WIDTH_in;
984  g_ip->page_sz_bits     = PAGE_SIZE_BITS_in;
985
986  g_ip->cache_sz            = cache_size;
987  g_ip->line_sz             = line_size;
988  g_ip->assoc               = associativity;
989  g_ip->nbanks              = banks;
990  g_ip->out_w               = output_width;
991  g_ip->specific_tag        = specific_tag;
992  if (specific_tag == 0) {
993    g_ip->tag_w = 42;
994  }
995  else {
996    g_ip->tag_w               = tag_width;
997  }
998
999  g_ip->access_mode         = access_mode;
1000  g_ip->delay_wt = obj_func_delay;
1001  g_ip->dynamic_power_wt = obj_func_dynamic_power;
1002  g_ip->leakage_power_wt = obj_func_leakage_power;
1003  g_ip->area_wt = obj_func_area;
1004  g_ip->cycle_time_wt    = obj_func_cycle_time;
1005  g_ip->delay_dev = dev_func_delay;
1006  g_ip->dynamic_power_dev = dev_func_dynamic_power;
1007  g_ip->leakage_power_dev = dev_func_leakage_power;
1008  g_ip->area_dev = dev_func_area;
1009  g_ip->cycle_time_dev    = dev_func_cycle_time;
1010  g_ip->temp = temp;
1011  g_ip->ed = ed_ed2_none;
1012
1013  g_ip->F_sz_nm         = tech_node;
1014  g_ip->F_sz_um         = tech_node / 1000;
1015  g_ip->is_main_mem     = (main_mem != 0) ? true : false;
1016  g_ip->is_cache        = (cache ==1) ? true : false;
1017  g_ip->pure_ram        = (cache ==0) ? true : false;
1018  g_ip->pure_cam        = (cache ==2) ? true : false;
1019  g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false;
1020  g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in;
1021  g_ip->broadcast_addr_din_over_ver_htrees = BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in;
1022
1023  g_ip->num_rw_ports    = rw_ports;
1024  g_ip->num_rd_ports    = excl_read_ports;
1025  g_ip->num_wr_ports    = excl_write_ports;
1026  g_ip->num_se_rd_ports = single_ended_read_ports;
1027  g_ip->num_search_ports = search_ports;
1028
1029  g_ip->print_detail = 1;
1030  g_ip->nuca = 0;
1031
1032  if (force_wiretype == 0)
1033  {
1034          g_ip->wt = Global;
1035      g_ip->force_wiretype = false;
1036  }
1037  else
1038  {   g_ip->force_wiretype = true;
1039          if (wiretype==10) {
1040                  g_ip->wt = Global_10;
1041                }
1042          if (wiretype==20) {
1043                  g_ip->wt = Global_20;
1044                }
1045          if (wiretype==30) {
1046                  g_ip->wt = Global_30;
1047                }
1048          if (wiretype==5) {
1049              g_ip->wt = Global_5;
1050                }
1051          if (wiretype==0) {
1052                  g_ip->wt = Low_swing;
1053          }
1054  }
1055  //g_ip->wt = Global_5;
1056  if (force_config == 0)
1057    {
1058          g_ip->force_cache_config = false;
1059    }
1060    else
1061    {
1062        g_ip->force_cache_config = true;
1063        g_ip->ndbl=ndbl;
1064        g_ip->ndwl=ndwl;
1065        g_ip->nspd=nspd;
1066        g_ip->ndcm=ndcm;
1067        g_ip->ndsam1=ndsam1;
1068        g_ip->ndsam2=ndsam2;
1069
1070
1071    }
1072
1073  if (ecc==0){
1074          g_ip->add_ecc_b_=false;
1075  }
1076  else
1077  {
1078          g_ip->add_ecc_b_=true;
1079  }
1080
1081
1082  if(!g_ip->error_checking())
1083          exit(0);
1084
1085  init_tech_params(g_ip->F_sz_um, false);
1086  Wire winit; // Do not delete this line. It initializes wires.
1087
1088  g_ip->display_ip();
1089  solve(&fin_res);
1090  output_UCA(&fin_res);
1091  output_data_csv(fin_res);
1092  delete (g_ip);
1093
1094  return fin_res;
1095}
1096
1097
1098
1099bool InputParameter::error_checking()
1100{
1101  int  A;
1102  bool seq_access  = false;
1103  fast_access = true;
1104
1105  switch (access_mode)
1106  {
1107    case 0:
1108      seq_access  = false;
1109      fast_access = false;
1110      break;
1111    case 1:
1112      seq_access  = true;
1113      fast_access = false;
1114      break;
1115    case 2:
1116      seq_access  = false;
1117      fast_access = true;
1118      break;
1119  }
1120
1121  if(is_main_mem)
1122  {
1123    if(ic_proj_type == 0)
1124    {
1125      cerr << "DRAM model supports only conservative interconnect projection!\n\n";
1126      return false;
1127    }
1128  }
1129
1130
1131  uint32_t B = line_sz;
1132
1133  if (B < 1)
1134  {
1135    cerr << "Block size must >= 1" << endl;
1136    return false;
1137  }
1138  else if (B*8 < out_w)
1139  {
1140    cerr << "Block size must be at least " << out_w/8 << endl;
1141    return false;
1142  }
1143
1144  if (F_sz_um <= 0)
1145  {
1146    cerr << "Feature size must be > 0" << endl;
1147    return false;
1148  }
1149  else if (F_sz_um > 0.091)
1150  {
1151    cerr << "Feature size must be <= 90 nm" << endl;
1152    return false;
1153  }
1154
1155
1156  uint32_t RWP  = num_rw_ports;
1157  uint32_t ERP  = num_rd_ports;
1158  uint32_t EWP  = num_wr_ports;
1159  uint32_t NSER = num_se_rd_ports;
1160  uint32_t SCHP = num_search_ports;
1161
1162//TODO: revisit this. This is an important feature. Sheng thought this should be used
1163//  // If multiple banks and multiple ports are specified, then if number of ports is less than or equal to
1164//  // the number of banks, we assume that the multiple ports are implemented via the multiple banks.
1165//  // In such a case we assume that each bank has 1 RWP port.
1166//  if ((RWP + ERP + EWP) <= nbanks && nbanks>1)
1167//  {
1168//    RWP  = 1;
1169//    ERP  = 0;
1170//    EWP  = 0;
1171//    NSER = 0;
1172//  }
1173//  else if ((RWP < 0) || (EWP < 0) || (ERP < 0))
1174//  {
1175//    cerr << "Ports must >=0" << endl;
1176//    return false;
1177//  }
1178//  else if (RWP > 2)
1179//  {
1180//    cerr << "Maximum of 2 read/write ports" << endl;
1181//    return false;
1182//  }
1183//  else if ((RWP+ERP+EWP) < 1)
1184  // Changed to new implementation:
1185  // The number of ports specified at input is per bank
1186  if ((RWP+ERP+EWP) < 1)
1187  {
1188    cerr << "Must have at least one port" << endl;
1189    return false;
1190  }
1191
1192  if (is_pow2(nbanks) == false)
1193  {
1194    cerr << "Number of subbanks should be greater than or equal to 1 and should be a power of 2" << endl;
1195    return false;
1196  }
1197
1198  int C = cache_sz/nbanks;
1199  if (C < 64)
1200  {
1201    cerr << "Cache size must >=64" << endl;
1202    return false;
1203  }
1204
1205//TODO: revisit this
1206//   if (pure_ram==true && assoc!=1)
1207//    {
1208//  	  cerr << "Pure RAM must have assoc as 1" << endl;
1209//  	  return false;
1210//    }
1211
1212    //fully assoc and cam check
1213    if (is_cache && assoc==0)
1214        fully_assoc =true;
1215    else
1216        fully_assoc = false;
1217
1218    if (pure_cam==true && assoc!=0)
1219    {
1220          cerr << "Pure CAM must have associativity as 0" << endl;
1221          return false;
1222    }
1223
1224    if (assoc==0 && (pure_cam==false && is_cache ==false))
1225    {
1226          cerr << "Only CAM or Fully associative cache can have associativity as 0" << endl;
1227          return false;
1228    }
1229
1230    if ((fully_assoc==true || pure_cam==true)
1231                  &&  (data_arr_ram_cell_tech_type!= tag_arr_ram_cell_tech_type
1232                                 || data_arr_peri_global_tech_type != tag_arr_peri_global_tech_type  ))
1233    {
1234          cerr << "CAM and fully associative cache must have same device type for both data and tag array" << endl;
1235          return false;
1236    }
1237
1238    if ((fully_assoc==true || pure_cam==true)
1239                  &&  (data_arr_ram_cell_tech_type== lp_dram || data_arr_ram_cell_tech_type== comm_dram))
1240    {
1241          cerr << "DRAM based CAM and fully associative cache are not supported" << endl;
1242          return false;
1243    }
1244
1245    if ((fully_assoc==true || pure_cam==true)
1246                  &&  (is_main_mem==true))
1247    {
1248          cerr << "CAM and fully associative cache cannot be as main memory" << endl;
1249          return false;
1250    }
1251
1252    if ((fully_assoc || pure_cam) && SCHP<1)
1253    {
1254          cerr << "CAM and fully associative must have at least 1 search port" << endl;
1255          return false;
1256    }
1257
1258   if (RWP==0 && ERP==0 && SCHP>0 && ((fully_assoc || pure_cam)))
1259    {
1260          ERP=SCHP;
1261    }
1262
1263//    if ((!(fully_assoc || pure_cam)) && SCHP>=1)
1264//    {
1265//	  cerr << "None CAM and fully associative cannot have search ports" << endl;
1266//	  return false;
1267//    }
1268
1269  if (assoc == 0)
1270  {
1271    A = C/B;
1272    //fully_assoc = true;
1273  }
1274  else
1275  {
1276    if (assoc == 1)
1277    {
1278      A = 1;
1279      //fully_assoc = false;
1280    }
1281    else
1282    {
1283      //fully_assoc = false;
1284      A = assoc;
1285      if (is_pow2(A) == false)
1286      {
1287        cerr << "Associativity must be a power of 2" << endl;
1288        return false;
1289      }
1290    }
1291  }
1292
1293  if (C/(B*A) <= 1 && assoc!=0)
1294  {
1295    cerr << "Number of sets is too small: " << endl;
1296    cerr << " Need to either increase cache size, or decrease associativity or block size" << endl;
1297    cerr << " (or use fully associative cache)" << endl;
1298    return false;
1299  }
1300
1301  block_sz = B;
1302
1303  /*dt: testing sequential access mode*/
1304  if(seq_access)
1305  {
1306    tag_assoc  = A;
1307    data_assoc = 1;
1308    is_seq_acc = true;
1309  }
1310  else
1311  {
1312    tag_assoc  = A;
1313    data_assoc = A;
1314    is_seq_acc = false;
1315  }
1316
1317  if (assoc==0)
1318  {
1319    data_assoc = 1;
1320  }
1321  num_rw_ports     = RWP;
1322  num_rd_ports     = ERP;
1323  num_wr_ports     = EWP;
1324  num_se_rd_ports  = NSER;
1325  if (!(fully_assoc || pure_cam))
1326    num_search_ports = 0;
1327  nsets            = C/(B*A);
1328
1329  if (temp < 300 || temp > 400 || temp%10 != 0)
1330  {
1331    cerr << temp << " Temperature must be between 300 and 400 Kelvin and multiple of 10." << endl;
1332    return false;
1333  }
1334
1335  if (nsets < 1)
1336  {
1337    cerr << "Less than one set..." << endl;
1338    return false;
1339  }
1340
1341  return true;
1342}
1343
1344
1345
1346void output_data_csv(const uca_org_t & fin_res)
1347{
1348  //TODO: the csv output should remain
1349  fstream file("out.csv", ios::in);
1350  bool    print_index = file.fail();
1351  file.close();
1352
1353  file.open("out.csv", ios::out|ios::app);
1354  if (file.fail() == true)
1355  {
1356    cerr << "File out.csv could not be opened successfully" << endl;
1357  }
1358  else
1359  {
1360    if (print_index == true)
1361    {
1362      file << "Tech node (nm), ";
1363      file << "Capacity (bytes), ";
1364      file << "Number of banks, ";
1365      file << "Associativity, ";
1366      file << "Output width (bits), ";
1367      file << "Access time (ns), ";
1368      file << "Random cycle time (ns), ";
1369//      file << "Multisubbank interleave cycle time (ns), ";
1370
1371//      file << "Delay request network (ns), ";
1372//      file << "Delay inside mat (ns), ";
1373//      file << "Delay reply network (ns), ";
1374//      file << "Tag array access time (ns), ";
1375//      file << "Data array access time (ns), ";
1376//      file << "Refresh period (microsec), ";
1377//      file << "DRAM array availability (%), ";
1378      file << "Dynamic search energy (nJ), ";
1379      file << "Dynamic read energy (nJ), ";
1380      file << "Dynamic write energy (nJ), ";
1381//      file << "Tag Dynamic read energy (nJ), ";
1382//      file << "Data Dynamic read energy (nJ), ";
1383//      file << "Dynamic read power (mW), ";
1384      file << "Standby leakage per bank(mW), ";
1385//      file << "Leakage per bank with leak power management (mW), ";
1386//      file << "Leakage per bank with leak power management (mW), ";
1387//      file << "Refresh power as percentage of standby leakage, ";
1388      file << "Area (mm2), ";
1389      file << "Ndwl, ";
1390      file << "Ndbl, ";
1391      file << "Nspd, ";
1392      file << "Ndcm, ";
1393      file << "Ndsam_level_1, ";
1394      file << "Ndsam_level_2, ";
1395      file << "Data arrary area efficiency %, ";
1396      file << "Ntwl, ";
1397      file << "Ntbl, ";
1398      file << "Ntspd, ";
1399      file << "Ntcm, ";
1400      file << "Ntsam_level_1, ";
1401      file << "Ntsam_level_2, ";
1402      file << "Tag arrary area efficiency %, ";
1403
1404//      file << "Resistance per unit micron (ohm-micron), ";
1405//      file << "Capacitance per unit micron (fF per micron), ";
1406//      file << "Unit-length wire delay (ps), ";
1407//      file << "FO4 delay (ps), ";
1408//      file << "delay route to bank (including crossb delay) (ps), ";
1409//      file << "Crossbar delay (ps), ";
1410//      file << "Dyn read energy per access from closed page (nJ), ";
1411//      file << "Dyn read energy per access from open page (nJ), ";
1412//      file << "Leak power of an subbank with page closed (mW), ";
1413//      file << "Leak power of a subbank with page  open (mW), ";
1414//      file << "Leak power of request and reply networks (mW), ";
1415//      file << "Number of subbanks, ";
1416//      file << "Page size in bits, ";
1417//      file << "Activate power, ";
1418//      file << "Read power, ";
1419//      file << "Write power, ";
1420//      file << "Precharge power, ";
1421//      file << "tRCD, ";
1422//      file << "CAS latency, ";
1423//      file << "Precharge delay, ";
1424//      file << "Perc dyn energy bitlines, ";
1425//      file << "perc dyn energy wordlines, ";
1426//      file << "perc dyn energy outside mat, ";
1427//      file << "Area opt (perc), ";
1428//      file << "Delay opt (perc), ";
1429//      file << "Repeater opt (perc), ";
1430//      file << "Aspect ratio";
1431      file << endl;
1432    }
1433    file << g_ip->F_sz_nm << ", ";
1434    file << g_ip->cache_sz << ", ";
1435    file << g_ip->nbanks << ", ";
1436    file << g_ip->tag_assoc << ", ";
1437    file << g_ip->out_w << ", ";
1438    file << fin_res.access_time*1e+9 << ", ";
1439    file << fin_res.cycle_time*1e+9 << ", ";
1440//    file << fin_res.data_array2->multisubbank_interleave_cycle_time*1e+9 << ", ";
1441//    file << fin_res.data_array2->delay_request_network*1e+9 << ", ";
1442//    file << fin_res.data_array2->delay_inside_mat*1e+9 <<  ", ";
1443//    file << fin_res.data_array2.delay_reply_network*1e+9 << ", ";
1444
1445//    if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram))
1446//        {
1447//    	  file << fin_res.tag_array2->access_time*1e+9 << ", ";
1448//        }
1449//    else
1450//    {
1451//    	file << 0 << ", ";
1452//    }
1453//    file << fin_res.data_array2->access_time*1e+9 << ", ";
1454//    file << fin_res.data_array2->dram_refresh_period*1e+6 << ", ";
1455//    file << fin_res.data_array2->dram_array_availability <<  ", ";
1456    if (g_ip->fully_assoc || g_ip->pure_cam)
1457    {
1458        file << fin_res.power.searchOp.dynamic*1e+9 << ", ";
1459    }
1460        else
1461    {
1462                file << "N/A" << ", ";
1463    }
1464    file << fin_res.power.readOp.dynamic*1e+9 << ", ";
1465    file << fin_res.power.writeOp.dynamic*1e+9 << ", ";
1466//    if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram))
1467//        {
1468//        	file << fin_res.tag_array2->power.readOp.dynamic*1e+9 << ", ";
1469//        }
1470//        	else
1471//        {
1472//        		file << "NA" << ", ";
1473//        }
1474//    file << fin_res.data_array2->power.readOp.dynamic*1e+9 << ", ";
1475//    if (g_ip->fully_assoc || g_ip->pure_cam)
1476//        {
1477//    	    file << fin_res.power.searchOp.dynamic*1000/fin_res.cycle_time << ", ";
1478//        }
1479//        	else
1480//        {
1481//        	file << fin_res.power.readOp.dynamic*1000/fin_res.cycle_time << ", ";
1482//        }
1483
1484    file <<( fin_res.power.readOp.leakage + fin_res.power.readOp.gate_leakage )*1000 << ", ";
1485//    file << fin_res.leak_power_with_sleep_transistors_in_mats*1000 << ", ";
1486//    file << fin_res.data_array.refresh_power / fin_res.data_array.total_power.readOp.leakage << ", ";
1487    file << fin_res.area*1e-6 << ", ";
1488
1489    file << fin_res.data_array2->Ndwl << ", ";
1490    file << fin_res.data_array2->Ndbl << ", ";
1491    file << fin_res.data_array2->Nspd << ", ";
1492    file << fin_res.data_array2->deg_bl_muxing << ", ";
1493    file << fin_res.data_array2->Ndsam_lev_1 << ", ";
1494    file << fin_res.data_array2->Ndsam_lev_2 << ", ";
1495    file << fin_res.data_array2->area_efficiency << ", ";
1496    if (!(g_ip->fully_assoc || g_ip->pure_cam || g_ip->pure_ram))
1497    {
1498    file << fin_res.tag_array2->Ndwl << ", ";
1499    file << fin_res.tag_array2->Ndbl << ", ";
1500    file << fin_res.tag_array2->Nspd << ", ";
1501    file << fin_res.tag_array2->deg_bl_muxing << ", ";
1502    file << fin_res.tag_array2->Ndsam_lev_1 << ", ";
1503    file << fin_res.tag_array2->Ndsam_lev_2 << ", ";
1504    file << fin_res.tag_array2->area_efficiency << ", ";
1505    }
1506    else
1507    {
1508        file << "N/A" << ", ";
1509        file << "N/A"<< ", ";
1510        file << "N/A" << ", ";
1511        file << "N/A" << ", ";
1512        file << "N/A" << ", ";
1513        file << "N/A" << ", ";
1514        file << "N/A" << ", ";
1515    }
1516
1517//    file << g_tp.wire_inside_mat.R_per_um << ", ";
1518//    file << g_tp.wire_inside_mat.C_per_um / 1e-15 << ", ";
1519//    file << g_tp.unit_len_wire_del / 1e-12 << ", ";
1520//    file << g_tp.FO4 / 1e-12 << ", ";
1521//    file << fin_res.data_array.delay_route_to_bank / 1e-9 << ", ";
1522//    file << fin_res.data_array.delay_crossbar / 1e-9 << ", ";
1523//    file << fin_res.data_array.dyn_read_energy_from_closed_page / 1e-9 << ", ";
1524//    file << fin_res.data_array.dyn_read_energy_from_open_page / 1e-9 << ", ";
1525//    file << fin_res.data_array.leak_power_subbank_closed_page / 1e-3 << ", ";
1526//    file << fin_res.data_array.leak_power_subbank_open_page / 1e-3 << ", ";
1527//    file << fin_res.data_array.leak_power_request_and_reply_networks / 1e-3 << ", ";
1528//    file << fin_res.data_array.number_subbanks << ", " ;
1529//    file << fin_res.data_array.page_size_in_bits << ", " ;
1530//    file << fin_res.data_array.activate_energy * 1e9 << ", " ;
1531//    file << fin_res.data_array.read_energy * 1e9 << ", " ;
1532//    file << fin_res.data_array.write_energy * 1e9 << ", " ;
1533//    file << fin_res.data_array.precharge_energy * 1e9 << ", " ;
1534//    file << fin_res.data_array.trcd * 1e9 << ", " ;
1535//    file << fin_res.data_array.cas_latency * 1e9 << ", " ;
1536//    file << fin_res.data_array.precharge_delay * 1e9 << ", " ;
1537//    file << fin_res.data_array.all_banks_height / fin_res.data_array.all_banks_width;
1538    file<<endl;
1539  }
1540  file.close();
1541}
1542
1543
1544
1545void output_UCA(uca_org_t *fr)
1546{
1547  //    if (NUCA)
1548  if (0) {
1549    cout << "\n\n Detailed Bank Stats:\n";
1550    cout << "    Bank Size (bytes): %d\n" <<
1551                                     (int) (g_ip->cache_sz);
1552  }
1553  else {
1554    if (g_ip->data_arr_ram_cell_tech_type == 3) {
1555      cout << "\n---------- CACTI version 6.5, Uniform Cache Access " <<
1556        "Logic Process Based DRAM Model ----------\n";
1557    }
1558    else if (g_ip->data_arr_ram_cell_tech_type == 4) {
1559      cout << "\n---------- CACTI version 6.5, Uniform" <<
1560        "Cache Access Commodity DRAM Model ----------\n";
1561    }
1562    else {
1563      cout << "\n---------- CACTI version 6.5, Uniform Cache Access "
1564        "SRAM Model ----------\n";
1565    }
1566    cout << "\nCache Parameters:\n";
1567    cout << "    Total cache size (bytes): " <<
1568      (int) (g_ip->cache_sz) << endl;
1569  }
1570
1571  cout << "    Number of banks: " << (int) g_ip->nbanks << endl;
1572  if (g_ip->fully_assoc|| g_ip->pure_cam)
1573    cout << "    Associativity: fully associative\n";
1574  else {
1575    if (g_ip->tag_assoc == 1)
1576      cout << "    Associativity: direct mapped\n";
1577    else
1578      cout << "    Associativity: " <<
1579        g_ip->tag_assoc << endl;
1580  }
1581
1582
1583  cout << "    Block size (bytes): " << g_ip->line_sz << endl;
1584  cout << "    Read/write Ports: " <<
1585    g_ip->num_rw_ports << endl;
1586  cout << "    Read ports: " <<
1587    g_ip->num_rd_ports << endl;
1588  cout << "    Write ports: " <<
1589    g_ip->num_wr_ports << endl;
1590  if (g_ip->fully_assoc|| g_ip->pure_cam)
1591          cout << "    search ports: " <<
1592              g_ip->num_search_ports << endl;
1593  cout << "    Technology size (nm): " <<
1594    g_ip->F_sz_nm << endl << endl;
1595
1596  cout << "    Access time (ns): " << fr->access_time*1e9 << endl;
1597  cout << "    Cycle time (ns):  " << fr->cycle_time*1e9 << endl;
1598  if (g_ip->data_arr_ram_cell_tech_type >= 4) {
1599    cout << "    Precharge Delay (ns): " << fr->data_array2->precharge_delay*1e9 << endl;
1600    cout << "    Activate Energy (nJ): " << fr->data_array2->activate_energy*1e9 << endl;
1601    cout << "    Read Energy (nJ): " << fr->data_array2->read_energy*1e9 << endl;
1602    cout << "    Write Energy (nJ): " << fr->data_array2->write_energy*1e9 << endl;
1603    cout << "    Precharge Energy (nJ): " << fr->data_array2->precharge_energy*1e9 << endl;
1604    cout << "    Leakage Power Closed Page (mW): " << fr->data_array2->leak_power_subbank_closed_page*1e3 << endl;
1605    cout << "    Leakage Power Open Page (mW): " << fr->data_array2->leak_power_subbank_open_page*1e3 << endl;
1606    cout << "    Leakage Power I/O (mW): " << fr->data_array2->leak_power_request_and_reply_networks*1e3 << endl;
1607    cout << "    Refresh power (mW): " <<
1608      fr->data_array2->refresh_power*1e3 << endl;
1609  }
1610  else {
1611          if ((g_ip->fully_assoc|| g_ip->pure_cam))
1612          {
1613                  cout << "    Total dynamic associative search energy per access (nJ): " <<
1614                  fr->power.searchOp.dynamic*1e9 << endl;
1615//		  cout << "    Total dynamic read energy per access (nJ): " <<
1616//		  fr->power.readOp.dynamic*1e9 << endl;
1617//		  cout << "    Total dynamic write energy per access (nJ): " <<
1618//		  fr->power.writeOp.dynamic*1e9 << endl;
1619          }
1620//	  else
1621//	  {
1622                  cout << "    Total dynamic read energy per access (nJ): " <<
1623                  fr->power.readOp.dynamic*1e9 << endl;
1624                  cout << "    Total dynamic write energy per access (nJ): " <<
1625                  fr->power.writeOp.dynamic*1e9 << endl;
1626//	  }
1627          cout << "    Total leakage power of a bank"
1628          " (mW): " << fr->power.readOp.leakage*1e3 << endl;
1629          cout << "    Total gate leakage power of a bank"
1630          " (mW): " << fr->power.readOp.gate_leakage*1e3 << endl;
1631  }
1632
1633  if (g_ip->data_arr_ram_cell_tech_type ==3 || g_ip->data_arr_ram_cell_tech_type ==4)
1634  {
1635  }
1636  cout <<  "    Cache height x width (mm): " <<
1637    fr->cache_ht*1e-3 << " x " << fr->cache_len*1e-3 << endl << endl;
1638
1639
1640  cout << "    Best Ndwl : " << fr->data_array2->Ndwl << endl;
1641  cout << "    Best Ndbl : " << fr->data_array2->Ndbl << endl;
1642  cout << "    Best Nspd : " << fr->data_array2->Nspd << endl;
1643  cout << "    Best Ndcm : " << fr->data_array2->deg_bl_muxing << endl;
1644  cout << "    Best Ndsam L1 : " << fr->data_array2->Ndsam_lev_1 << endl;
1645  cout << "    Best Ndsam L2 : " << fr->data_array2->Ndsam_lev_2 << endl << endl;
1646
1647  if ((!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)) && !g_ip->is_main_mem)
1648  {
1649    cout << "    Best Ntwl : " << fr->tag_array2->Ndwl << endl;
1650    cout << "    Best Ntbl : " << fr->tag_array2->Ndbl << endl;
1651    cout << "    Best Ntspd : " << fr->tag_array2->Nspd << endl;
1652    cout << "    Best Ntcm : " << fr->tag_array2->deg_bl_muxing << endl;
1653    cout << "    Best Ntsam L1 : " << fr->tag_array2->Ndsam_lev_1 << endl;
1654    cout << "    Best Ntsam L2 : " << fr->tag_array2->Ndsam_lev_2 << endl;
1655  }
1656
1657  switch (fr->data_array2->wt) {
1658    case (0):
1659      cout <<  "    Data array, H-tree wire type: Delay optimized global wires\n";
1660      break;
1661    case (1):
1662      cout <<  "    Data array, H-tree wire type: Global wires with 5\% delay penalty\n";
1663      break;
1664    case (2):
1665      cout <<  "    Data array, H-tree wire type: Global wires with 10\% delay penalty\n";
1666      break;
1667    case (3):
1668      cout <<  "    Data array, H-tree wire type: Global wires with 20\% delay penalty\n";
1669      break;
1670    case (4):
1671      cout <<  "    Data array, H-tree wire type: Global wires with 30\% delay penalty\n";
1672      break;
1673    case (5):
1674      cout <<  "    Data array, wire type: Low swing wires\n";
1675      break;
1676    default:
1677      cout << "ERROR - Unknown wire type " << (int) fr->data_array2->wt <<endl;
1678      exit(0);
1679  }
1680
1681  if (!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)) {
1682    switch (fr->tag_array2->wt) {
1683      case (0):
1684        cout <<  "    Tag array, H-tree wire type: Delay optimized global wires\n";
1685        break;
1686      case (1):
1687        cout <<  "    Tag array, H-tree wire type: Global wires with 5\% delay penalty\n";
1688        break;
1689      case (2):
1690        cout <<  "    Tag array, H-tree wire type: Global wires with 10\% delay penalty\n";
1691        break;
1692      case (3):
1693        cout <<  "    Tag array, H-tree wire type: Global wires with 20\% delay penalty\n";
1694        break;
1695      case (4):
1696        cout <<  "    Tag array, H-tree wire type: Global wires with 30\% delay penalty\n";
1697        break;
1698      case (5):
1699        cout <<  "    Tag array, wire type: Low swing wires\n";
1700        break;
1701      default:
1702        cout << "ERROR - Unknown wire type " << (int) fr->tag_array2->wt <<endl;
1703        exit(-1);
1704    }
1705  }
1706
1707  if (g_ip->print_detail)
1708  {
1709    //if(g_ip->fully_assoc) return;
1710
1711    /* Delay stats */
1712    /* data array stats */
1713    cout << endl << "Time Components:" << endl << endl;
1714
1715    cout << "  Data side (with Output driver) (ns): " <<
1716      fr->data_array2->access_time/1e-9 << endl;
1717
1718    cout <<  "\tH-tree input delay (ns): " <<
1719      fr->data_array2->delay_route_to_bank * 1e9 +
1720      fr->data_array2->delay_input_htree * 1e9 << endl;
1721
1722    if (!(g_ip->pure_cam || g_ip->fully_assoc))
1723    {
1724      cout <<  "\tDecoder + wordline delay (ns): " <<
1725        fr->data_array2->delay_row_predecode_driver_and_block * 1e9 +
1726        fr->data_array2->delay_row_decoder * 1e9 << endl;
1727    }
1728    else
1729    {
1730        cout <<  "\tCAM search delay (ns): " <<
1731          fr->data_array2->delay_matchlines * 1e9 << endl;
1732    }
1733
1734    cout <<  "\tBitline delay (ns): " <<
1735      fr->data_array2->delay_bitlines/1e-9 << endl;
1736
1737    cout <<  "\tSense Amplifier delay (ns): " <<
1738      fr->data_array2->delay_sense_amp * 1e9 << endl;
1739
1740
1741    cout <<  "\tH-tree output delay (ns): " <<
1742      fr->data_array2->delay_subarray_output_driver * 1e9 +
1743      fr->data_array2->delay_dout_htree * 1e9 << endl;
1744
1745    if ((!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)) && !g_ip->is_main_mem)
1746    {
1747      /* tag array stats */
1748      cout << endl << "  Tag side (with Output driver) (ns): " <<
1749        fr->tag_array2->access_time/1e-9 << endl;
1750
1751      cout <<  "\tH-tree input delay (ns): " <<
1752        fr->tag_array2->delay_route_to_bank * 1e9 +
1753        fr->tag_array2->delay_input_htree * 1e9 << endl;
1754
1755      cout <<  "\tDecoder + wordline delay (ns): " <<
1756        fr->tag_array2->delay_row_predecode_driver_and_block * 1e9 +
1757        fr->tag_array2->delay_row_decoder * 1e9 << endl;
1758
1759      cout <<  "\tBitline delay (ns): " <<
1760        fr->tag_array2->delay_bitlines/1e-9 << endl;
1761
1762      cout <<  "\tSense Amplifier delay (ns): " <<
1763        fr->tag_array2->delay_sense_amp * 1e9 << endl;
1764
1765      cout <<  "\tComparator delay (ns): " <<
1766        fr->tag_array2->delay_comparator * 1e9 << endl;
1767
1768      cout <<  "\tH-tree output delay (ns): " <<
1769        fr->tag_array2->delay_subarray_output_driver * 1e9 +
1770        fr->tag_array2->delay_dout_htree * 1e9 << endl;
1771    }
1772
1773
1774
1775    /* Energy/Power stats */
1776    cout << endl << endl << "Power Components:" << endl << endl;
1777
1778    if (!(g_ip->pure_cam || g_ip->fully_assoc))
1779    {
1780        cout << "  Data array: Total dynamic read energy/access  (nJ): " <<
1781              fr->data_array2->power.readOp.dynamic * 1e9 << endl;
1782        cout << "\tTotal leakage read/write power of a bank (mW): " <<
1783                fr->data_array2->power.readOp.leakage * 1e3 << endl;
1784
1785        cout << "\tTotal energy in H-tree (that includes both "
1786              "address and data transfer) (nJ): " <<
1787                (fr->data_array2->power_addr_input_htree.readOp.dynamic +
1788                 fr->data_array2->power_data_output_htree.readOp.dynamic +
1789                 fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl;
1790
1791        cout << "\tTotal leakage power in H-tree (that includes both "
1792              "address and data network) ((mW)): " <<
1793                (fr->data_array2->power_addr_input_htree.readOp.leakage +
1794                 fr->data_array2->power_data_output_htree.readOp.leakage +
1795                 fr->data_array2->power_routing_to_bank.readOp.leakage) * 1e3 << endl;
1796
1797        cout << "\tTotal gate leakage power in H-tree (that includes both "
1798              "address and data network) ((mW)): " <<
1799                (fr->data_array2->power_addr_input_htree.readOp.gate_leakage +
1800                 fr->data_array2->power_data_output_htree.readOp.gate_leakage +
1801                 fr->data_array2->power_routing_to_bank.readOp.gate_leakage) * 1e3 << endl;
1802
1803        cout << "\tOutput Htree inside bank Energy (nJ): " <<
1804           fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl;
1805        cout <<  "\tDecoder (nJ): " <<
1806           fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 +
1807           fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl;
1808        cout <<  "\tWordline (nJ): " <<
1809           fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl;
1810        cout <<  "\tBitline mux & associated drivers (nJ): " <<
1811           fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 +
1812           fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 +
1813           fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl;
1814        cout <<  "\tSense amp mux & associated drivers (nJ): " <<
1815           fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 +
1816           fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 +
1817           fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9  +
1818           fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 +
1819           fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 +
1820           fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl;
1821
1822        cout <<  "\tBitlines precharge and equalization circuit (nJ): " <<
1823                   fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl;
1824        cout <<  "\tBitlines (nJ): " <<
1825           fr->data_array2->power_bitlines.readOp.dynamic * 1e9 << endl;
1826        cout <<  "\tSense amplifier energy (nJ): " <<
1827           fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl;
1828        cout <<  "\tSub-array output driver (nJ): " <<
1829           fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl;
1830    }
1831
1832        else if (g_ip->pure_cam)
1833        {
1834
1835                cout << "  CAM array:"<<endl;
1836                cout << "  Total dynamic associative search energy/access  (nJ): " <<
1837                      fr->data_array2->power.searchOp.dynamic * 1e9 << endl;
1838                cout << "\tTotal energy in H-tree (that includes both "
1839                              "match key and data transfer) (nJ): " <<
1840                      (fr->data_array2->power_htree_in_search.searchOp.dynamic +
1841                       fr->data_array2->power_htree_out_search.searchOp.dynamic +
1842                       fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9 << endl;
1843                cout << "\tKeyword input and result output Htrees inside bank Energy (nJ): " <<
1844                      (fr->data_array2->power_htree_in_search.searchOp.dynamic +
1845                               fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9 << endl;
1846                cout <<  "\tSearchlines (nJ): " <<
1847                           fr->data_array2->power_searchline.searchOp.dynamic * 1e9 +
1848                           fr->data_array2->power_searchline_precharge.searchOp.dynamic * 1e9 << endl;
1849                cout <<  "\tMatchlines  (nJ): " <<
1850                       fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 +
1851                           fr->data_array2->power_matchline_precharge.searchOp.dynamic * 1e9 << endl;
1852                cout <<  "\tSub-array output driver (nJ): " <<
1853                           fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic * 1e9 << endl;
1854
1855
1856                cout <<endl<< "  Total dynamic read energy/access  (nJ): " <<
1857                      fr->data_array2->power.readOp.dynamic * 1e9 << endl;
1858                cout << "\tTotal energy in H-tree (that includes both "
1859                              "address and data transfer) (nJ): " <<
1860                      (fr->data_array2->power_addr_input_htree.readOp.dynamic +
1861                       fr->data_array2->power_data_output_htree.readOp.dynamic +
1862                       fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl;
1863                cout << "\tOutput Htree inside bank Energy (nJ): " <<
1864                           fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl;
1865                cout <<  "\tDecoder (nJ): " <<
1866                           fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 +
1867                           fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl;
1868                cout <<  "\tWordline (nJ): " <<
1869                           fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl;
1870                cout <<  "\tBitline mux & associated drivers (nJ): " <<
1871                           fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 +
1872                           fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 +
1873                           fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl;
1874                cout <<  "\tSense amp mux & associated drivers (nJ): " <<
1875                           fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 +
1876                           fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 +
1877                           fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9  +
1878                           fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 +
1879                           fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 +
1880                           fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl;
1881                cout <<  "\tBitlines (nJ): " <<
1882                           fr->data_array2->power_bitlines.readOp.dynamic * 1e9 +
1883                           fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9<< endl;
1884                cout <<  "\tSense amplifier energy (nJ): " <<
1885                           fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl;
1886                cout <<  "\tSub-array output driver (nJ): " <<
1887                           fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl;
1888
1889                cout << endl <<"  Total leakage power of a bank (mW): " <<
1890                      fr->data_array2->power.readOp.leakage * 1e3 << endl;
1891        }
1892        else
1893        {
1894                cout << "  Fully associative array:"<<endl;
1895                cout << "  Total dynamic associative search energy/access  (nJ): " <<
1896                  fr->data_array2->power.searchOp.dynamic * 1e9 << endl;
1897                cout << "\tTotal energy in H-tree (that includes both "
1898                              "match key and data transfer) (nJ): " <<
1899                      (fr->data_array2->power_htree_in_search.searchOp.dynamic +
1900                       fr->data_array2->power_htree_out_search.searchOp.dynamic +
1901                       fr->data_array2->power_routing_to_bank.searchOp.dynamic) * 1e9 << endl;
1902                cout << "\tKeyword input and result output Htrees inside bank Energy (nJ): " <<
1903                      (fr->data_array2->power_htree_in_search.searchOp.dynamic +
1904                               fr->data_array2->power_htree_out_search.searchOp.dynamic) * 1e9 << endl;
1905                cout <<  "\tSearchlines (nJ): " <<
1906                           fr->data_array2->power_searchline.searchOp.dynamic * 1e9 +
1907                           fr->data_array2->power_searchline_precharge.searchOp.dynamic * 1e9 << endl;
1908                cout <<  "\tMatchlines  (nJ): " <<
1909                       fr->data_array2->power_matchlines.searchOp.dynamic * 1e9 +
1910                           fr->data_array2->power_matchline_precharge.searchOp.dynamic * 1e9 << endl;
1911                cout <<  "\tData portion wordline (nJ): " <<
1912                           fr->data_array2->power_matchline_to_wordline_drv.searchOp.dynamic * 1e9 << endl;
1913                cout <<  "\tData Bitlines (nJ): " <<
1914                           fr->data_array2->power_bitlines.searchOp.dynamic * 1e9 +
1915                           fr->data_array2->power_prechg_eq_drivers.searchOp.dynamic * 1e9 << endl;
1916                cout <<  "\tSense amplifier energy (nJ): " <<
1917                           fr->data_array2->power_sense_amps.searchOp.dynamic * 1e9 << endl;
1918                cout <<  "\tSub-array output driver (nJ): " <<
1919                           fr->data_array2->power_output_drivers_at_subarray.searchOp.dynamic * 1e9 << endl;
1920
1921
1922                cout <<endl<< "  Total dynamic read energy/access  (nJ): " <<
1923                      fr->data_array2->power.readOp.dynamic * 1e9 << endl;
1924                cout << "\tTotal energy in H-tree (that includes both "
1925                              "address and data transfer) (nJ): " <<
1926                      (fr->data_array2->power_addr_input_htree.readOp.dynamic +
1927                       fr->data_array2->power_data_output_htree.readOp.dynamic +
1928                       fr->data_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl;
1929                cout << "\tOutput Htree inside bank Energy (nJ): " <<
1930                           fr->data_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl;
1931                cout <<  "\tDecoder (nJ): " <<
1932                           fr->data_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 +
1933                           fr->data_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl;
1934                cout <<  "\tWordline (nJ): " <<
1935                           fr->data_array2->power_row_decoders.readOp.dynamic * 1e9 << endl;
1936                cout <<  "\tBitline mux & associated drivers (nJ): " <<
1937                           fr->data_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 +
1938                           fr->data_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 +
1939                           fr->data_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl;
1940                cout <<  "\tSense amp mux & associated drivers (nJ): " <<
1941                           fr->data_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 +
1942                           fr->data_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 +
1943                           fr->data_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9  +
1944                           fr->data_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 +
1945                           fr->data_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 +
1946                           fr->data_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl;
1947                cout <<  "\tBitlines (nJ): " <<
1948                           fr->data_array2->power_bitlines.readOp.dynamic * 1e9 +
1949                           fr->data_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9<< endl;
1950                cout <<  "\tSense amplifier energy (nJ): " <<
1951                           fr->data_array2->power_sense_amps.readOp.dynamic * 1e9 << endl;
1952                cout <<  "\tSub-array output driver (nJ): " <<
1953                           fr->data_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl;
1954
1955                cout << endl <<"  Total leakage power of a bank (mW): " <<
1956                  fr->data_array2->power.readOp.leakage * 1e3 << endl;
1957      }
1958
1959
1960    if ((!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)) && !g_ip->is_main_mem)
1961    {
1962      cout << endl << "  Tag array:  Total dynamic read energy/access (nJ): " <<
1963        fr->tag_array2->power.readOp.dynamic * 1e9 << endl;
1964      cout << "\tTotal leakage read/write power of a bank (mW): " <<
1965          fr->tag_array2->power.readOp.leakage * 1e3 << endl;
1966      cout << "\tTotal energy in H-tree (that includes both "
1967        "address and data transfer) (nJ): " <<
1968          (fr->tag_array2->power_addr_input_htree.readOp.dynamic +
1969           fr->tag_array2->power_data_output_htree.readOp.dynamic +
1970           fr->tag_array2->power_routing_to_bank.readOp.dynamic) * 1e9 << endl;
1971
1972      cout << "\tTotal leakage power in H-tree (that includes both "
1973              "address and data network) ((mW)): " <<
1974                (fr->tag_array2->power_addr_input_htree.readOp.leakage +
1975                 fr->tag_array2->power_data_output_htree.readOp.leakage +
1976                 fr->tag_array2->power_routing_to_bank.readOp.leakage) * 1e3 << endl;
1977
1978          cout << "\tTotal gate leakage power in H-tree (that includes both "
1979              "address and data network) ((mW)): " <<
1980                (fr->tag_array2->power_addr_input_htree.readOp.gate_leakage +
1981                 fr->tag_array2->power_data_output_htree.readOp.gate_leakage +
1982                 fr->tag_array2->power_routing_to_bank.readOp.gate_leakage) * 1e3 << endl;
1983
1984      cout << "\tOutput Htree inside a bank Energy (nJ): " <<
1985        fr->tag_array2->power_data_output_htree.readOp.dynamic * 1e9 << endl;
1986      cout <<  "\tDecoder (nJ): " <<
1987        fr->tag_array2->power_row_predecoder_drivers.readOp.dynamic * 1e9 +
1988        fr->tag_array2->power_row_predecoder_blocks.readOp.dynamic * 1e9 << endl;
1989      cout <<  "\tWordline (nJ): " <<
1990        fr->tag_array2->power_row_decoders.readOp.dynamic * 1e9 << endl;
1991      cout <<  "\tBitline mux & associated drivers (nJ): " <<
1992        fr->tag_array2->power_bit_mux_predecoder_drivers.readOp.dynamic * 1e9 +
1993        fr->tag_array2->power_bit_mux_predecoder_blocks.readOp.dynamic * 1e9 +
1994        fr->tag_array2->power_bit_mux_decoders.readOp.dynamic * 1e9 << endl;
1995      cout <<  "\tSense amp mux & associated drivers (nJ): " <<
1996        fr->tag_array2->power_senseamp_mux_lev_1_predecoder_drivers.readOp.dynamic * 1e9 +
1997        fr->tag_array2->power_senseamp_mux_lev_1_predecoder_blocks.readOp.dynamic * 1e9 +
1998        fr->tag_array2->power_senseamp_mux_lev_1_decoders.readOp.dynamic * 1e9  +
1999        fr->tag_array2->power_senseamp_mux_lev_2_predecoder_drivers.readOp.dynamic * 1e9 +
2000        fr->tag_array2->power_senseamp_mux_lev_2_predecoder_blocks.readOp.dynamic * 1e9 +
2001        fr->tag_array2->power_senseamp_mux_lev_2_decoders.readOp.dynamic * 1e9 << endl;
2002      cout <<  "\tBitlines precharge and equalization circuit (nJ): " <<
2003        fr->tag_array2->power_prechg_eq_drivers.readOp.dynamic * 1e9 << endl;
2004      cout <<  "\tBitlines (nJ): " <<
2005        fr->tag_array2->power_bitlines.readOp.dynamic * 1e9 << endl;
2006      cout <<  "\tSense amplifier energy (nJ): " <<
2007        fr->tag_array2->power_sense_amps.readOp.dynamic * 1e9 << endl;
2008      cout <<  "\tSub-array output driver (nJ): " <<
2009        fr->tag_array2->power_output_drivers_at_subarray.readOp.dynamic * 1e9 << endl;
2010    }
2011
2012    cout << endl << endl <<  "Area Components:" << endl << endl;
2013    /* Data array area stats */
2014    if (!(g_ip->pure_cam || g_ip->fully_assoc))
2015        cout <<  "  Data array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl;
2016    else if (g_ip->pure_cam)
2017        cout <<  "  CAM array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl;
2018    else
2019        cout <<  "  Fully associative cache array: Area (mm2): " << fr->data_array2->area * 1e-6 << endl;
2020    cout <<  "\tHeight (mm): " <<
2021      fr->data_array2->all_banks_height*1e-3 << endl;
2022    cout <<  "\tWidth (mm): " <<
2023      fr->data_array2->all_banks_width*1e-3 << endl;
2024    if (g_ip->print_detail) {
2025      cout <<  "\tArea efficiency (Memory cell area/Total area) - " <<
2026        fr->data_array2->area_efficiency << " %" << endl;
2027      cout << "\t\tMAT Height (mm): " <<
2028        fr->data_array2->mat_height*1e-3 << endl;
2029      cout << "\t\tMAT Length (mm): " <<
2030        fr->data_array2->mat_length*1e-3 << endl;
2031      cout << "\t\tSubarray Height (mm): " <<
2032        fr->data_array2->subarray_height*1e-3 << endl;
2033      cout << "\t\tSubarray Length (mm): " <<
2034        fr->data_array2->subarray_length*1e-3 << endl;
2035    }
2036
2037    /* Tag array area stats */
2038    if ((!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)) && !g_ip->is_main_mem)
2039    {
2040      cout << endl << "  Tag array: Area (mm2): " << fr->tag_array2->area * 1e-6 << endl;
2041      cout <<  "\tHeight (mm): " <<
2042        fr->tag_array2->all_banks_height*1e-3 << endl;
2043      cout <<  "\tWidth (mm): " <<
2044        fr->tag_array2->all_banks_width*1e-3 << endl;
2045      if (g_ip->print_detail)
2046      {
2047        cout <<  "\tArea efficiency (Memory cell area/Total area) - " <<
2048          fr->tag_array2->area_efficiency << " %" << endl;
2049      cout << "\t\tMAT Height (mm): " <<
2050        fr->tag_array2->mat_height*1e-3 << endl;
2051      cout << "\t\tMAT Length (mm): " <<
2052        fr->tag_array2->mat_length*1e-3 << endl;
2053      cout << "\t\tSubarray Height (mm): " <<
2054        fr->tag_array2->subarray_height*1e-3 << endl;
2055      cout << "\t\tSubarray Length (mm): " <<
2056        fr->tag_array2->subarray_length*1e-3 << endl;
2057      }
2058    }
2059    Wire wpr;
2060    wpr.print_wire();
2061
2062    //cout << "FO4 = " << g_tp.FO4 << endl;
2063  }
2064}
2065
2066//McPAT's plain interface, please keep !!!
2067uca_org_t cacti_interface(InputParameter  * const local_interface)
2068{
2069//  g_ip = new InputParameter();
2070  //g_ip->add_ecc_b_ = true;
2071
2072  uca_org_t fin_res;
2073  fin_res.valid = false;
2074
2075  g_ip = local_interface;
2076
2077
2078//  g_ip->data_arr_ram_cell_tech_type    = data_arr_ram_cell_tech_flavor_in;
2079//  g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in;
2080//  g_ip->tag_arr_ram_cell_tech_type     = tag_arr_ram_cell_tech_flavor_in;
2081//  g_ip->tag_arr_peri_global_tech_type  = tag_arr_peri_global_tech_flavor_in;
2082//
2083//  g_ip->ic_proj_type     = interconnect_projection_type_in;
2084//  g_ip->wire_is_mat_type = wire_inside_mat_type_in;
2085//  g_ip->wire_os_mat_type = wire_outside_mat_type_in;
2086//  g_ip->burst_len        = BURST_LENGTH_in;
2087//  g_ip->int_prefetch_w   = INTERNAL_PREFETCH_WIDTH_in;
2088//  g_ip->page_sz_bits     = PAGE_SIZE_BITS_in;
2089//
2090//  g_ip->cache_sz            = cache_size;
2091//  g_ip->line_sz             = line_size;
2092//  g_ip->assoc               = associativity;
2093//  g_ip->nbanks              = banks;
2094//  g_ip->out_w               = output_width;
2095//  g_ip->specific_tag        = specific_tag;
2096//  if (tag_width == 0) {
2097//    g_ip->tag_w = 42;
2098//  }
2099//  else {
2100//    g_ip->tag_w               = tag_width;
2101//  }
2102//
2103//  g_ip->access_mode         = access_mode;
2104//  g_ip->delay_wt = obj_func_delay;
2105//  g_ip->dynamic_power_wt = obj_func_dynamic_power;
2106//  g_ip->leakage_power_wt = obj_func_leakage_power;
2107//  g_ip->area_wt = obj_func_area;
2108//  g_ip->cycle_time_wt    = obj_func_cycle_time;
2109//  g_ip->delay_dev = dev_func_delay;
2110//  g_ip->dynamic_power_dev = dev_func_dynamic_power;
2111//  g_ip->leakage_power_dev = dev_func_leakage_power;
2112//  g_ip->area_dev = dev_func_area;
2113//  g_ip->cycle_time_dev    = dev_func_cycle_time;
2114//  g_ip->temp = temp;
2115//
2116//  g_ip->F_sz_nm         = tech_node;
2117//  g_ip->F_sz_um         = tech_node / 1000;
2118//  g_ip->is_main_mem     = (main_mem != 0) ? true : false;
2119//  g_ip->is_cache        = (cache ==1) ? true : false;
2120//  g_ip->pure_ram        = (cache ==0) ? true : false;
2121//  g_ip->pure_cam        = (cache ==2) ? true : false;
2122//  g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false;
2123//  g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in;
2124//  g_ip->broadcast_addr_din_over_ver_htrees = BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in;
2125//
2126//  g_ip->num_rw_ports    = rw_ports;
2127//  g_ip->num_rd_ports    = excl_read_ports;
2128//  g_ip->num_wr_ports    = excl_write_ports;
2129//  g_ip->num_se_rd_ports = single_ended_read_ports;
2130//  g_ip->num_search_ports = search_ports;
2131//
2132//  g_ip->print_detail = 1;
2133//    g_ip->nuca = 0;
2134//    g_ip->is_cache=true;
2135//
2136//  if (force_wiretype == 0)
2137//  {
2138//	  g_ip->wt = Global;
2139//      g_ip->force_wiretype = false;
2140//  }
2141//  else
2142//  {   g_ip->force_wiretype = true;
2143//	  if (wiretype==10) {
2144//		  g_ip->wt = Global_10;
2145//	        }
2146//	  if (wiretype==20) {
2147//		  g_ip->wt = Global_20;
2148//	        }
2149//	  if (wiretype==30) {
2150//		  g_ip->wt = Global_30;
2151//	        }
2152//	  if (wiretype==5) {
2153//	      g_ip->wt = Global_5;
2154//	        }
2155//	  if (wiretype==0) {
2156//		  g_ip->wt = Low_swing;
2157//	  }
2158//  }
2159//  //g_ip->wt = Global_5;
2160//  if (force_config == 0)
2161//    {
2162//  	  g_ip->force_cache_config = false;
2163//    }
2164//    else
2165//    {
2166//    	g_ip->force_cache_config = true;
2167//    	g_ip->ndbl=ndbl;
2168//    	g_ip->ndwl=ndwl;
2169//    	g_ip->nspd=nspd;
2170//    	g_ip->ndcm=ndcm;
2171//    	g_ip->ndsam1=ndsam1;
2172//    	g_ip->ndsam2=ndsam2;
2173//
2174//
2175//    }
2176//
2177//  if (ecc==0){
2178//	  g_ip->add_ecc_b_=false;
2179//  }
2180//  else
2181//  {
2182//	  g_ip->add_ecc_b_=true;
2183//  }
2184
2185
2186  g_ip->error_checking();
2187
2188
2189  init_tech_params(g_ip->F_sz_um, false);
2190  Wire winit; // Do not delete this line. It initializes wires.
2191
2192  solve(&fin_res);
2193
2194//  g_ip->display_ip();
2195//  output_UCA(&fin_res);
2196//  output_data_csv(fin_res);
2197
2198 // delete (g_ip);
2199
2200  return fin_res;
2201}
2202
2203//McPAT's plain interface, please keep !!!
2204uca_org_t init_interface(InputParameter* const local_interface)
2205{
2206 // g_ip = new InputParameter();
2207  //g_ip->add_ecc_b_ = true;
2208
2209  uca_org_t fin_res;
2210  fin_res.valid = false;
2211
2212   g_ip = local_interface;
2213
2214
2215//  g_ip->data_arr_ram_cell_tech_type    = data_arr_ram_cell_tech_flavor_in;
2216//  g_ip->data_arr_peri_global_tech_type = data_arr_peri_global_tech_flavor_in;
2217//  g_ip->tag_arr_ram_cell_tech_type     = tag_arr_ram_cell_tech_flavor_in;
2218//  g_ip->tag_arr_peri_global_tech_type  = tag_arr_peri_global_tech_flavor_in;
2219//
2220//  g_ip->ic_proj_type     = interconnect_projection_type_in;
2221//  g_ip->wire_is_mat_type = wire_inside_mat_type_in;
2222//  g_ip->wire_os_mat_type = wire_outside_mat_type_in;
2223//  g_ip->burst_len        = BURST_LENGTH_in;
2224//  g_ip->int_prefetch_w   = INTERNAL_PREFETCH_WIDTH_in;
2225//  g_ip->page_sz_bits     = PAGE_SIZE_BITS_in;
2226//
2227//  g_ip->cache_sz            = cache_size;
2228//  g_ip->line_sz             = line_size;
2229//  g_ip->assoc               = associativity;
2230//  g_ip->nbanks              = banks;
2231//  g_ip->out_w               = output_width;
2232//  g_ip->specific_tag        = specific_tag;
2233//  if (tag_width == 0) {
2234//    g_ip->tag_w = 42;
2235//  }
2236//  else {
2237//    g_ip->tag_w               = tag_width;
2238//  }
2239//
2240//  g_ip->access_mode         = access_mode;
2241//  g_ip->delay_wt = obj_func_delay;
2242//  g_ip->dynamic_power_wt = obj_func_dynamic_power;
2243//  g_ip->leakage_power_wt = obj_func_leakage_power;
2244//  g_ip->area_wt = obj_func_area;
2245//  g_ip->cycle_time_wt    = obj_func_cycle_time;
2246//  g_ip->delay_dev = dev_func_delay;
2247//  g_ip->dynamic_power_dev = dev_func_dynamic_power;
2248//  g_ip->leakage_power_dev = dev_func_leakage_power;
2249//  g_ip->area_dev = dev_func_area;
2250//  g_ip->cycle_time_dev    = dev_func_cycle_time;
2251//  g_ip->temp = temp;
2252//
2253//  g_ip->F_sz_nm         = tech_node;
2254//  g_ip->F_sz_um         = tech_node / 1000;
2255//  g_ip->is_main_mem     = (main_mem != 0) ? true : false;
2256//  g_ip->is_cache        = (cache ==1) ? true : false;
2257//  g_ip->pure_ram        = (cache ==0) ? true : false;
2258//  g_ip->pure_cam        = (cache ==2) ? true : false;
2259//  g_ip->rpters_in_htree = (REPEATERS_IN_HTREE_SEGMENTS_in != 0) ? true : false;
2260//  g_ip->ver_htree_wires_over_array = VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in;
2261//  g_ip->broadcast_addr_din_over_ver_htrees = BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in;
2262//
2263//  g_ip->num_rw_ports    = rw_ports;
2264//  g_ip->num_rd_ports    = excl_read_ports;
2265//  g_ip->num_wr_ports    = excl_write_ports;
2266//  g_ip->num_se_rd_ports = single_ended_read_ports;
2267//  g_ip->num_search_ports = search_ports;
2268//
2269//  g_ip->print_detail = 1;
2270//  g_ip->nuca = 0;
2271//
2272//  if (force_wiretype == 0)
2273//  {
2274//	  g_ip->wt = Global;
2275//      g_ip->force_wiretype = false;
2276//  }
2277//  else
2278//  {   g_ip->force_wiretype = true;
2279//	  if (wiretype==10) {
2280//		  g_ip->wt = Global_10;
2281//	        }
2282//	  if (wiretype==20) {
2283//		  g_ip->wt = Global_20;
2284//	        }
2285//	  if (wiretype==30) {
2286//		  g_ip->wt = Global_30;
2287//	        }
2288//	  if (wiretype==5) {
2289//	      g_ip->wt = Global_5;
2290//	        }
2291//	  if (wiretype==0) {
2292//		  g_ip->wt = Low_swing;
2293//	  }
2294//  }
2295//  //g_ip->wt = Global_5;
2296//  if (force_config == 0)
2297//    {
2298//  	  g_ip->force_cache_config = false;
2299//    }
2300//    else
2301//    {
2302//    	g_ip->force_cache_config = true;
2303//    	g_ip->ndbl=ndbl;
2304//    	g_ip->ndwl=ndwl;
2305//    	g_ip->nspd=nspd;
2306//    	g_ip->ndcm=ndcm;
2307//    	g_ip->ndsam1=ndsam1;
2308//    	g_ip->ndsam2=ndsam2;
2309//
2310//
2311//    }
2312//
2313//  if (ecc==0){
2314//	  g_ip->add_ecc_b_=false;
2315//  }
2316//  else
2317//  {
2318//	  g_ip->add_ecc_b_=true;
2319//  }
2320
2321
2322  g_ip->error_checking();
2323
2324  init_tech_params(g_ip->F_sz_um, false);
2325  Wire winit; // Do not delete this line. It initializes wires.
2326  //solve(&fin_res);
2327  //g_ip->display_ip();
2328
2329  //solve(&fin_res);
2330  //output_UCA(&fin_res);
2331  //output_data_csv(fin_res);
2332 // delete (g_ip);
2333
2334  return fin_res;
2335}
2336
2337void reconfigure(InputParameter *local_interface, uca_org_t *fin_res)
2338{
2339  // Copy the InputParameter to global interface (g_ip) and do error checking.
2340  g_ip = local_interface;
2341  g_ip->error_checking();
2342
2343  // Initialize technology parameters
2344  init_tech_params(g_ip->F_sz_um,false);
2345
2346  Wire winit; // Do not delete this line. It initializes wires.
2347
2348  // This corresponds to solve() in the initialization process.
2349  update(fin_res);
2350}
2351