htree2.h revision 10152:52c552138ba1 
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31
32
33#ifndef __HTREE2_H__
34#define __HTREE2_H__
35
36#include "assert.h"
37#include "basic_circuit.h"
38#include "cacti_interface.h"
39#include "component.h"
40#include "parameter.h"
41#include "subarray.h"
42#include "wire.h"
43
44// leakge power includes entire htree in a bank (when uca_tree == false)
45// leakge power includes only part to one bank when uca_tree == true
46
47class Htree2 : public Component
48{
49  public:
50    Htree2(enum Wire_type wire_model,
51        double mat_w, double mat_h, int add, int data_in, int search_data_in, int data_out, int search_data_out, int bl, int wl,
52        enum Htree_type h_type, bool uca_tree_ = false, bool search_tree_ = false,
53        TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
54    ~Htree2() {};
55
56    void in_htree();
57    void out_htree();
58
59    // repeaters only at h-tree nodes
60    void limited_in_htree();
61    void limited_out_htree();
62    void input_nand(double s1, double s2, double l);
63    void output_buffer(double s1, double s2, double l);
64
65    double in_rise_time, out_rise_time;
66
67    void set_in_rise_time(double rt)
68    {
69      in_rise_time = rt;
70    }
71
72    double max_unpipelined_link_delay;
73    powerDef power_bit;
74
75
76  private:
77    double wire_bw;
78    double init_wire_bw;  // bus width at root
79    enum Htree_type tree_type;
80    double htree_hnodes;
81    double htree_vnodes;
82    double mat_width;
83    double mat_height;
84    int add_bits, data_in_bits,search_data_in_bits,data_out_bits,  search_data_out_bits;
85    int ndbl, ndwl;
86    bool uca_tree; // should have full bandwidth to access all banks in the array simultaneously
87    bool search_tree;
88
89    enum Wire_type wt;
90    double min_w_nmos;
91    double min_w_pmos;
92
93    TechnologyParameter::DeviceType *deviceType;
94
95};
96
97#endif
98