cacti_interface.h revision 10152
1/***************************************************************************** 2 * McPAT/CACTI 3 * SOFTWARE LICENSE AGREEMENT 4 * Copyright 2012 Hewlett-Packard Development Company, L.P. 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 29 * 30 ***************************************************************************/ 31 32 33 34#ifndef __CACTI_INTERFACE_H__ 35#define __CACTI_INTERFACE_H__ 36 37#include <iostream> 38#include <list> 39#include <map> 40#include <string> 41#include <vector> 42 43#include "const.h" 44 45using namespace std; 46 47 48class min_values_t; 49class mem_array; 50class uca_org_t; 51 52 53class powerComponents 54{ 55 public: 56 double dynamic; 57 double leakage; 58 double gate_leakage; 59 double short_circuit; 60 double longer_channel_leakage; 61 62 powerComponents() : dynamic(0), leakage(0), gate_leakage(0), short_circuit(0), longer_channel_leakage(0) { } 63 powerComponents(const powerComponents & obj) { *this = obj; } 64 powerComponents & operator=(const powerComponents & rhs) 65 { 66 dynamic = rhs.dynamic; 67 leakage = rhs.leakage; 68 gate_leakage = rhs.gate_leakage; 69 short_circuit = rhs.short_circuit; 70 longer_channel_leakage = rhs.longer_channel_leakage; 71 return *this; 72 } 73 void reset() { dynamic = 0; leakage = 0; gate_leakage = 0; short_circuit = 0;longer_channel_leakage = 0;} 74 75 friend powerComponents operator+(const powerComponents & x, const powerComponents & y); 76 friend powerComponents operator*(const powerComponents & x, double const * const y); 77}; 78 79 80 81class powerDef 82{ 83 public: 84 powerComponents readOp; 85 powerComponents writeOp; 86 powerComponents searchOp;//Sheng: for CAM and FA 87 88 powerDef() : readOp(), writeOp(), searchOp() { } 89 void reset() { readOp.reset(); writeOp.reset(); searchOp.reset();} 90 91 friend powerDef operator+(const powerDef & x, const powerDef & y); 92 friend powerDef operator*(const powerDef & x, double const * const y); 93}; 94 95enum Wire_type 96{ 97 Global /* gloabl wires with repeaters */, 98 Global_5 /* 5% delay penalty */, 99 Global_10 /* 10% delay penalty */, 100 Global_20 /* 20% delay penalty */, 101 Global_30 /* 30% delay penalty */, 102 Low_swing /* differential low power wires with high area overhead */, 103 Semi_global /* mid-level wires with repeaters*/, 104 Transmission /* tranmission lines with high area overhead */, 105 Optical /* optical wires */, 106 Invalid_wtype 107}; 108 109 110 111class InputParameter 112{ 113 public: 114 void parse_cfg(const string & infile); 115 116 bool error_checking(); // return false if the input parameters are problematic 117 void display_ip(); 118 119 unsigned int cache_sz; // in bytes 120 unsigned int line_sz; 121 unsigned int assoc; 122 unsigned int nbanks; 123 unsigned int out_w;// == nr_bits_out 124 bool specific_tag; 125 unsigned int tag_w; 126 unsigned int access_mode; 127 unsigned int obj_func_dyn_energy; 128 unsigned int obj_func_dyn_power; 129 unsigned int obj_func_leak_power; 130 unsigned int obj_func_cycle_t; 131 132 double F_sz_nm; // feature size in nm 133 double F_sz_um; // feature size in um 134 unsigned int num_rw_ports; 135 unsigned int num_rd_ports; 136 unsigned int num_wr_ports; 137 unsigned int num_se_rd_ports; // number of single ended read ports 138 unsigned int num_search_ports; // Sheng: number of search ports for CAM 139 bool is_main_mem; 140 bool is_cache; 141 bool pure_ram; 142 bool pure_cam; 143 bool rpters_in_htree; // if there are repeaters in htree segment 144 unsigned int ver_htree_wires_over_array; 145 unsigned int broadcast_addr_din_over_ver_htrees; 146 unsigned int temp; 147 148 unsigned int ram_cell_tech_type; 149 unsigned int peri_global_tech_type; 150 unsigned int data_arr_ram_cell_tech_type; 151 unsigned int data_arr_peri_global_tech_type; 152 unsigned int tag_arr_ram_cell_tech_type; 153 unsigned int tag_arr_peri_global_tech_type; 154 155 unsigned int burst_len; 156 unsigned int int_prefetch_w; 157 unsigned int page_sz_bits; 158 159 unsigned int ic_proj_type; // interconnect_projection_type 160 unsigned int wire_is_mat_type; // wire_inside_mat_type 161 unsigned int wire_os_mat_type; // wire_outside_mat_type 162 enum Wire_type wt; 163 int force_wiretype; 164 bool print_input_args; 165 unsigned int nuca_cache_sz; // TODO 166 int ndbl, ndwl, nspd, ndsam1, ndsam2, ndcm; 167 bool force_cache_config; 168 169 int cache_level; 170 int cores; 171 int nuca_bank_count; 172 int force_nuca_bank; 173 174 int delay_wt, dynamic_power_wt, leakage_power_wt, 175 cycle_time_wt, area_wt; 176 int delay_wt_nuca, dynamic_power_wt_nuca, leakage_power_wt_nuca, 177 cycle_time_wt_nuca, area_wt_nuca; 178 179 int delay_dev, dynamic_power_dev, leakage_power_dev, 180 cycle_time_dev, area_dev; 181 int delay_dev_nuca, dynamic_power_dev_nuca, leakage_power_dev_nuca, 182 cycle_time_dev_nuca, area_dev_nuca; 183 int ed; //ED or ED2 optimization 184 int nuca; 185 186 bool fast_access; 187 unsigned int block_sz; // bytes 188 unsigned int tag_assoc; 189 unsigned int data_assoc; 190 bool is_seq_acc; 191 bool fully_assoc; 192 unsigned int nsets; // == number_of_sets 193 int print_detail; 194 195 196 bool add_ecc_b_; 197 //parameters for design constraint 198 double throughput; 199 double latency; 200 bool pipelinable; 201 int pipeline_stages; 202 int per_stage_vector; 203 bool with_clock_grid; 204}; 205 206 207typedef struct{ 208 int Ndwl; 209 int Ndbl; 210 double Nspd; 211 int deg_bl_muxing; 212 int Ndsam_lev_1; 213 int Ndsam_lev_2; 214 int number_activated_mats_horizontal_direction; 215 int number_subbanks; 216 int page_size_in_bits; 217 double delay_route_to_bank; 218 double delay_crossbar; 219 double delay_addr_din_horizontal_htree; 220 double delay_addr_din_vertical_htree; 221 double delay_row_predecode_driver_and_block; 222 double delay_row_decoder; 223 double delay_bitlines; 224 double delay_sense_amp; 225 double delay_subarray_output_driver; 226 double delay_bit_mux_predecode_driver_and_block; 227 double delay_bit_mux_decoder; 228 double delay_senseamp_mux_lev_1_predecode_driver_and_block; 229 double delay_senseamp_mux_lev_1_decoder; 230 double delay_senseamp_mux_lev_2_predecode_driver_and_block; 231 double delay_senseamp_mux_lev_2_decoder; 232 double delay_input_htree; 233 double delay_output_htree; 234 double delay_dout_vertical_htree; 235 double delay_dout_horizontal_htree; 236 double delay_comparator; 237 double access_time; 238 double cycle_time; 239 double multisubbank_interleave_cycle_time; 240 double delay_request_network; 241 double delay_inside_mat; 242 double delay_reply_network; 243 double trcd; 244 double cas_latency; 245 double precharge_delay; 246 powerDef power_routing_to_bank; 247 powerDef power_addr_input_htree; 248 powerDef power_data_input_htree; 249 powerDef power_data_output_htree; 250 powerDef power_addr_horizontal_htree; 251 powerDef power_datain_horizontal_htree; 252 powerDef power_dataout_horizontal_htree; 253 powerDef power_addr_vertical_htree; 254 powerDef power_datain_vertical_htree; 255 powerDef power_row_predecoder_drivers; 256 powerDef power_row_predecoder_blocks; 257 powerDef power_row_decoders; 258 powerDef power_bit_mux_predecoder_drivers; 259 powerDef power_bit_mux_predecoder_blocks; 260 powerDef power_bit_mux_decoders; 261 powerDef power_senseamp_mux_lev_1_predecoder_drivers; 262 powerDef power_senseamp_mux_lev_1_predecoder_blocks; 263 powerDef power_senseamp_mux_lev_1_decoders; 264 powerDef power_senseamp_mux_lev_2_predecoder_drivers; 265 powerDef power_senseamp_mux_lev_2_predecoder_blocks; 266 powerDef power_senseamp_mux_lev_2_decoders; 267 powerDef power_bitlines; 268 powerDef power_sense_amps; 269 powerDef power_prechg_eq_drivers; 270 powerDef power_output_drivers_at_subarray; 271 powerDef power_dataout_vertical_htree; 272 powerDef power_comparators; 273 powerDef power_crossbar; 274 powerDef total_power; 275 double area; 276 double all_banks_height; 277 double all_banks_width; 278 double bank_height; 279 double bank_width; 280 double subarray_memory_cell_area_height; 281 double subarray_memory_cell_area_width; 282 double mat_height; 283 double mat_width; 284 double routing_area_height_within_bank; 285 double routing_area_width_within_bank; 286 double area_efficiency; 287// double perc_power_dyn_routing_to_bank; 288// double perc_power_dyn_addr_horizontal_htree; 289// double perc_power_dyn_datain_horizontal_htree; 290// double perc_power_dyn_dataout_horizontal_htree; 291// double perc_power_dyn_addr_vertical_htree; 292// double perc_power_dyn_datain_vertical_htree; 293// double perc_power_dyn_row_predecoder_drivers; 294// double perc_power_dyn_row_predecoder_blocks; 295// double perc_power_dyn_row_decoders; 296// double perc_power_dyn_bit_mux_predecoder_drivers; 297// double perc_power_dyn_bit_mux_predecoder_blocks; 298// double perc_power_dyn_bit_mux_decoders; 299// double perc_power_dyn_senseamp_mux_lev_1_predecoder_drivers; 300// double perc_power_dyn_senseamp_mux_lev_1_predecoder_blocks; 301// double perc_power_dyn_senseamp_mux_lev_1_decoders; 302// double perc_power_dyn_senseamp_mux_lev_2_predecoder_drivers; 303// double perc_power_dyn_senseamp_mux_lev_2_predecoder_blocks; 304// double perc_power_dyn_senseamp_mux_lev_2_decoders; 305// double perc_power_dyn_bitlines; 306// double perc_power_dyn_sense_amps; 307// double perc_power_dyn_prechg_eq_drivers; 308// double perc_power_dyn_subarray_output_drivers; 309// double perc_power_dyn_dataout_vertical_htree; 310// double perc_power_dyn_comparators; 311// double perc_power_dyn_crossbar; 312// double perc_power_dyn_spent_outside_mats; 313// double perc_power_leak_routing_to_bank; 314// double perc_power_leak_addr_horizontal_htree; 315// double perc_power_leak_datain_horizontal_htree; 316// double perc_power_leak_dataout_horizontal_htree; 317// double perc_power_leak_addr_vertical_htree; 318// double perc_power_leak_datain_vertical_htree; 319// double perc_power_leak_row_predecoder_drivers; 320// double perc_power_leak_row_predecoder_blocks; 321// double perc_power_leak_row_decoders; 322// double perc_power_leak_bit_mux_predecoder_drivers; 323// double perc_power_leak_bit_mux_predecoder_blocks; 324// double perc_power_leak_bit_mux_decoders; 325// double perc_power_leak_senseamp_mux_lev_1_predecoder_drivers; 326// double perc_power_leak_senseamp_mux_lev_1_predecoder_blocks; 327// double perc_power_leak_senseamp_mux_lev_1_decoders; 328// double perc_power_leak_senseamp_mux_lev_2_predecoder_drivers; 329// double perc_power_leak_senseamp_mux_lev_2_predecoder_blocks; 330// double perc_power_leak_senseamp_mux_lev_2_decoders; 331// double perc_power_leak_bitlines; 332// double perc_power_leak_sense_amps; 333// double perc_power_leak_prechg_eq_drivers; 334// double perc_power_leak_subarray_output_drivers; 335// double perc_power_leak_dataout_vertical_htree; 336// double perc_power_leak_comparators; 337// double perc_power_leak_crossbar; 338// double perc_leak_mats; 339// double perc_active_mats; 340 double refresh_power; 341 double dram_refresh_period; 342 double dram_array_availability; 343 double dyn_read_energy_from_closed_page; 344 double dyn_read_energy_from_open_page; 345 double leak_power_subbank_closed_page; 346 double leak_power_subbank_open_page; 347 double leak_power_request_and_reply_networks; 348 double activate_energy; 349 double read_energy; 350 double write_energy; 351 double precharge_energy; 352} results_mem_array; 353 354 355class uca_org_t 356{ 357 public: 358 mem_array * tag_array2; 359 mem_array * data_array2; 360 double access_time; 361 double cycle_time; 362 double area; 363 double area_efficiency; 364 powerDef power; 365 double leak_power_with_sleep_transistors_in_mats; 366 double cache_ht; 367 double cache_len; 368 char file_n[100]; 369 double vdd_periph_global; 370 bool valid; 371 results_mem_array tag_array; 372 results_mem_array data_array; 373 374 uca_org_t(); 375 void find_delay(); 376 void find_energy(); 377 void find_area(); 378 void find_cyc(); 379 void adjust_area();//for McPAT only to adjust routing overhead 380 void cleanup(); 381 ~uca_org_t(){}; 382}; 383 384void reconfigure(InputParameter *local_interface, uca_org_t *fin_res); 385 386uca_org_t cacti_interface(const string & infile_name); 387//McPAT's plain interface, please keep !!! 388uca_org_t cacti_interface(InputParameter * const local_interface); 389//McPAT's plain interface, please keep !!! 390uca_org_t init_interface(InputParameter * const local_interface); 391//McPAT's plain interface, please keep !!! 392uca_org_t cacti_interface( 393 int cache_size, 394 int line_size, 395 int associativity, 396 int rw_ports, 397 int excl_read_ports, 398 int excl_write_ports, 399 int single_ended_read_ports, 400 int search_ports, 401 int banks, 402 double tech_node, 403 int output_width, 404 int specific_tag, 405 int tag_width, 406 int access_mode, 407 int cache, 408 int main_mem, 409 int obj_func_delay, 410 int obj_func_dynamic_power, 411 int obj_func_leakage_power, 412 int obj_func_cycle_time, 413 int obj_func_area, 414 int dev_func_delay, 415 int dev_func_dynamic_power, 416 int dev_func_leakage_power, 417 int dev_func_area, 418 int dev_func_cycle_time, 419 int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate 420 int temp, 421 int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing 422 int data_arr_ram_cell_tech_flavor_in, 423 int data_arr_peri_global_tech_flavor_in, 424 int tag_arr_ram_cell_tech_flavor_in, 425 int tag_arr_peri_global_tech_flavor_in, 426 int interconnect_projection_type_in, 427 int wire_inside_mat_type_in, 428 int wire_outside_mat_type_in, 429 int REPEATERS_IN_HTREE_SEGMENTS_in, 430 int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, 431 int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, 432 int PAGE_SIZE_BITS_in, 433 int BURST_LENGTH_in, 434 int INTERNAL_PREFETCH_WIDTH_in, 435 int force_wiretype, 436 int wiretype, 437 int force_config, 438 int ndwl, 439 int ndbl, 440 int nspd, 441 int ndcm, 442 int ndsam1, 443 int ndsam2, 444 int ecc); 445// int cache_size, 446// int line_size, 447// int associativity, 448// int rw_ports, 449// int excl_read_ports, 450// int excl_write_ports, 451// int single_ended_read_ports, 452// int banks, 453// double tech_node, 454// int output_width, 455// int specific_tag, 456// int tag_width, 457// int access_mode, 458// int cache, 459// int main_mem, 460// int obj_func_delay, 461// int obj_func_dynamic_power, 462// int obj_func_leakage_power, 463// int obj_func_area, 464// int obj_func_cycle_time, 465// int dev_func_delay, 466// int dev_func_dynamic_power, 467// int dev_func_leakage_power, 468// int dev_func_area, 469// int dev_func_cycle_time, 470// int temp, 471// int data_arr_ram_cell_tech_flavor_in, 472// int data_arr_peri_global_tech_flavor_in, 473// int tag_arr_ram_cell_tech_flavor_in, 474// int tag_arr_peri_global_tech_flavor_in, 475// int interconnect_projection_type_in, 476// int wire_inside_mat_type_in, 477// int wire_outside_mat_type_in, 478// int REPEATERS_IN_HTREE_SEGMENTS_in, 479// int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, 480// int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, 481//// double MAXAREACONSTRAINT_PERC_in, 482//// double MAXACCTIMECONSTRAINT_PERC_in, 483//// double MAX_PERC_DIFF_IN_DELAY_FROM_BEST_DELAY_REPEATER_SOLUTION_in, 484// int PAGE_SIZE_BITS_in, 485// int BURST_LENGTH_in, 486// int INTERNAL_PREFETCH_WIDTH_in); 487 488//Naveen's interface 489uca_org_t cacti_interface( 490 int cache_size, 491 int line_size, 492 int associativity, 493 int rw_ports, 494 int excl_read_ports, 495 int excl_write_ports, 496 int single_ended_read_ports, 497 int banks, 498 double tech_node, 499 int page_sz, 500 int burst_length, 501 int pre_width, 502 int output_width, 503 int specific_tag, 504 int tag_width, 505 int access_mode, //0 normal, 1 seq, 2 fast 506 int cache, //scratch ram or cache 507 int main_mem, 508 int obj_func_delay, 509 int obj_func_dynamic_power, 510 int obj_func_leakage_power, 511 int obj_func_area, 512 int obj_func_cycle_time, 513 int dev_func_delay, 514 int dev_func_dynamic_power, 515 int dev_func_leakage_power, 516 int dev_func_area, 517 int dev_func_cycle_time, 518 int ed_ed2_none, // 0 - ED, 1 - ED^2, 2 - use weight and deviate 519 int temp, 520 int wt, //0 - default(search across everything), 1 - global, 2 - 5% delay penalty, 3 - 10%, 4 - 20 %, 5 - 30%, 6 - low-swing 521 int data_arr_ram_cell_tech_flavor_in, 522 int data_arr_peri_global_tech_flavor_in, 523 int tag_arr_ram_cell_tech_flavor_in, 524 int tag_arr_peri_global_tech_flavor_in, 525 int interconnect_projection_type_in, // 0 - aggressive, 1 - normal 526 int wire_inside_mat_type_in, 527 int wire_outside_mat_type_in, 528 int is_nuca, // 0 - UCA, 1 - NUCA 529 int core_count, 530 int cache_level, // 0 - L2, 1 - L3 531 int nuca_bank_count, 532 int nuca_obj_func_delay, 533 int nuca_obj_func_dynamic_power, 534 int nuca_obj_func_leakage_power, 535 int nuca_obj_func_area, 536 int nuca_obj_func_cycle_time, 537 int nuca_dev_func_delay, 538 int nuca_dev_func_dynamic_power, 539 int nuca_dev_func_leakage_power, 540 int nuca_dev_func_area, 541 int nuca_dev_func_cycle_time, 542 int REPEATERS_IN_HTREE_SEGMENTS_in,//TODO for now only wires with repeaters are supported 543 int p_input); 544 545class mem_array 546{ 547 public: 548 int Ndcm; 549 int Ndwl; 550 int Ndbl; 551 double Nspd; 552 int deg_bl_muxing; 553 int Ndsam_lev_1; 554 int Ndsam_lev_2; 555 double access_time; 556 double cycle_time; 557 double multisubbank_interleave_cycle_time; 558 double area_ram_cells; 559 double area; 560 powerDef power; 561 double delay_senseamp_mux_decoder; 562 double delay_before_subarray_output_driver; 563 double delay_from_subarray_output_driver_to_output; 564 double height; 565 double width; 566 567 double mat_height; 568 double mat_length; 569 double subarray_length; 570 double subarray_height; 571 572 double delay_route_to_bank, 573 delay_input_htree, 574 delay_row_predecode_driver_and_block, 575 delay_row_decoder, 576 delay_bitlines, 577 delay_sense_amp, 578 delay_subarray_output_driver, 579 delay_dout_htree, 580 delay_comparator, 581 delay_matchlines; 582 583 double all_banks_height, 584 all_banks_width, 585 area_efficiency; 586 587 powerDef power_routing_to_bank; 588 powerDef power_addr_input_htree; 589 powerDef power_data_input_htree; 590 powerDef power_data_output_htree; 591 powerDef power_htree_in_search; 592 powerDef power_htree_out_search; 593 powerDef power_row_predecoder_drivers; 594 powerDef power_row_predecoder_blocks; 595 powerDef power_row_decoders; 596 powerDef power_bit_mux_predecoder_drivers; 597 powerDef power_bit_mux_predecoder_blocks; 598 powerDef power_bit_mux_decoders; 599 powerDef power_senseamp_mux_lev_1_predecoder_drivers; 600 powerDef power_senseamp_mux_lev_1_predecoder_blocks; 601 powerDef power_senseamp_mux_lev_1_decoders; 602 powerDef power_senseamp_mux_lev_2_predecoder_drivers; 603 powerDef power_senseamp_mux_lev_2_predecoder_blocks; 604 powerDef power_senseamp_mux_lev_2_decoders; 605 powerDef power_bitlines; 606 powerDef power_sense_amps; 607 powerDef power_prechg_eq_drivers; 608 powerDef power_output_drivers_at_subarray; 609 powerDef power_dataout_vertical_htree; 610 powerDef power_comparators; 611 612 powerDef power_cam_bitline_precharge_eq_drv; 613 powerDef power_searchline; 614 powerDef power_searchline_precharge; 615 powerDef power_matchlines; 616 powerDef power_matchline_precharge; 617 powerDef power_matchline_to_wordline_drv; 618 619 min_values_t *arr_min; 620 enum Wire_type wt; 621 622 // dram stats 623 double activate_energy, read_energy, write_energy, precharge_energy, 624 refresh_power, leak_power_subbank_closed_page, leak_power_subbank_open_page, 625 leak_power_request_and_reply_networks; 626 627 double precharge_delay; 628 629 static bool lt(const mem_array * m1, const mem_array * m2); 630}; 631 632 633#endif 634