cache.cfg revision 10152
1# Cache size
2//-size (bytes) 2048
3//-size (bytes) 4096
4//-size (bytes) 32768
5//-size (bytes) 262144
6//-size (bytes) 1048576
7//-size (bytes) 2097152
8//-size (bytes) 4194304
9//-size (bytes) 8388608
10//-size (bytes) 16777216
11//-size (bytes) 33554432
12//-size (bytes) 134217728
13//-size (bytes) 67108864
14-size (bytes) 1073741824
15
16# Line size
17//-block size (bytes) 8
18-block size (bytes) 64
19
20# To model Fully Associative cache, set associativity to zero
21//-associativity 0
22//-associativity 2
23//-associativity 4
24-associativity 8
25//-associativity 16
26
27-read-write port 1
28-exclusive read port 0
29-exclusive write port 0
30-single ended read ports 0
31
32# Multiple banks connected using a bus
33-UCA bank count 1
34-technology (u) 0.022
35//-technology (u) 0.040
36//-technology (u) 0.032
37//-technology (u) 0.090
38
39# following three parameters are meaningful only for main memories
40
41-page size (bits) 8192 
42-burst length 8
43-internal prefetch width 8
44
45# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
46-Data array cell type - "itrs-hp"
47//-Data array cell type - "itrs-lstp"
48//-Data array cell type - "itrs-lop"
49
50# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
51-Data array peripheral type - "itrs-hp"
52//-Data array peripheral type - "itrs-lstp"
53//-Data array peripheral type - "itrs-lop"
54
55# following parameter can have one of five values -- (itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram)
56-Tag array cell type - "itrs-hp"
57//-Tag array cell type - "itrs-lstp"
58//-Tag array cell type - "itrs-lop"
59
60# following parameter can have one of three values -- (itrs-hp, itrs-lstp, itrs-lop)
61-Tag array peripheral type - "itrs-hp"
62//-Tag array peripheral type - "itrs-lstp"
63//-Tag array peripheral type - "itrs-lop
64
65# Bus width include data bits and address bits required by the decoder
66//-output/input bus width 16
67-output/input bus width 512
68
69// 300-400 in steps of 10
70-operating temperature (K) 360
71
72# Type of memory - cache (with a tag array) or ram (scratch ram similar to a register file) 
73# or main memory (no tag array and every access will happen at a page granularity Ref: CACTI 5.3 report)
74-cache type "cache"
75//-cache type "ram"
76//-cache type "main memory"
77
78# to model special structure like branch target buffers, directory, etc. 
79# change the tag size parameter
80# if you want cacti to calculate the tagbits, set the tag size to "default"
81-tag size (b) "default"
82//-tag size (b) 22
83
84# fast - data and tag access happen in parallel
85# sequential - data array is accessed after accessing the tag array
86# normal - data array lookup and tag access happen in parallel
87#          final data block is broadcasted in data array h-tree 
88#          after getting the signal from the tag array
89//-access mode (normal, sequential, fast) - "fast"
90-access mode (normal, sequential, fast) - "normal"
91//-access mode (normal, sequential, fast) - "sequential"
92
93
94# DESIGN OBJECTIVE for UCA (or banks in NUCA)
95-design objective (weight delay, dynamic power, leakage power, cycle time, area) 0:0:0:100:0
96
97# Percentage deviation from the minimum value 
98# Ex: A deviation value of 10:1000:1000:1000:1000 will try to find an organization
99# that compromises at most 10% delay. 
100# NOTE: Try reasonable values for % deviation. Inconsistent deviation
101# percentage values will not produce any valid organizations. For example,
102# 0:0:100:100:100 will try to identify an organization that has both
103# least delay and dynamic power. Since such an organization is not possible, CACTI will
104# throw an error. Refer CACTI-6 Technical report for more details
105-deviate (delay, dynamic power, leakage power, cycle time, area) 20:100000:100000:100000:100000
106
107# Objective for NUCA
108-NUCAdesign objective (weight delay, dynamic power, leakage power, cycle time, area) 100:100:0:0:100
109-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) 10:10000:10000:10000:10000
110
111# Set optimize tag to ED or ED^2 to obtain a cache configuration optimized for
112# energy-delay or energy-delay sq. product
113# Note: Optimize tag will disable weight or deviate values mentioned above
114# Set it to NONE to let weight and deviate values determine the 
115# appropriate cache configuration
116//-Optimize ED or ED^2 (ED, ED^2, NONE): "ED"
117-Optimize ED or ED^2 (ED, ED^2, NONE): "ED^2"
118//-Optimize ED or ED^2 (ED, ED^2, NONE): "NONE"
119
120-Cache model (NUCA, UCA)  - "UCA"
121//-Cache model (NUCA, UCA)  - "NUCA"
122
123# In order for CACTI to find the optimal NUCA bank value the following
124# variable should be assigned 0.
125-NUCA bank count 0
126
127# NOTE: for nuca network frequency is set to a default value of 
128# 5GHz in time.c. CACTI automatically
129# calculates the maximum possible frequency and downgrades this value if necessary
130
131# By default CACTI considers both full-swing and low-swing 
132# wires to find an optimal configuration. However, it is possible to 
133# restrict the search space by changing the signalling from "default" to 
134# "fullswing" or "lowswing" type.
135//-Wire signalling (fullswing, lowswing, default) - "Global_10"
136-Wire signalling (fullswing, lowswing, default) - "default"
137//-Wire signalling (fullswing, lowswing, default) - "lowswing"
138
139//-Wire inside mat - "global"
140-Wire inside mat - "semi-global"
141//-Wire outside mat - "global"
142-Wire outside mat - "semi-global"
143
144//-Interconnect projection - "conservative"
145-Interconnect projection - "aggressive"
146
147# Contention in network (which is a function of core count and cache level) is one of
148# the critical factor used for deciding the optimal bank count value
149# core count can be 4, 8, or 16
150//-Core count 4
151-Core count 8
152//-Core count 16
153-Cache level (L2/L3) - "L3"
154
155-Add ECC - "true"
156
157//-Print level (DETAILED, CONCISE) - "CONCISE"
158-Print level (DETAILED, CONCISE) - "DETAILED"
159
160# for debugging
161//-Print input parameters - "true"
162-Print input parameters - "false"
163# force CACTI to model the cache with the 
164# following Ndbl, Ndwl, Nspd, Ndsam,
165# and Ndcm values
166//-Force cache config - "true"
167-Force cache config - "false"
168-Ndwl 1
169-Ndbl 1
170-Nspd 0
171-Ndcm 1
172-Ndsam1 0
173-Ndsam2 0
174
175
176